[PATCH] D68411: Add support for intrinsics llvm.ppc.dcbfl and llvm.ppc.dcbflp

[Anil Mahmud via Phabricator via llvm-commits]

anil9 created this revision.
anil9 added reviewers: PowerPC, rzurob, hfinkel.
Herald added subscribers: llvm-commits, jsji, MaskRay, kbarton, hiraditya, nemanjai.
Herald added a project: LLVM.

Added support for the intrinsic llvm.ppc.dcbfl and llvm.ppc.dcbflp these will be used for emitting cache control instructions dcbfl and dcbflp which are actually mnemonics for using dcbf instruction with different immediate arguments.

dcbf ra, rb, 1 -> dcbfl ra, rb
dcbflp ra, rb, 3 -> dcbflp, ra, rb


https://reviews.llvm.org/D68411

Files:
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/dcbfl.ll
  llvm/test/CodeGen/PowerPC/dcbflp.ll


Index: llvm/test/CodeGen/PowerPC/dcbflp.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/dcbflp.ll
@@ -0,0 +1,15 @@
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s \
+; RUN:     -verify-machineinstrs -ppc-asm-full-reg-names \
+; RUN:     -ppc-vsr-nums-as-vr | FileCheck %s
+
+; Function Attrs: nounwind
+define void @dcbflp_test(i8* %a) {
+entry:
+  tail call void @llvm.ppc.dcbflp(i8* %a)
+; CHECK-LABEL: @dcbflp_test
+; CHECK: dcbflp 0, r3
+; CHECK-NEXT: blr
+ret void
+}
+
+declare void @llvm.ppc.dcbflp(i8*)
Index: llvm/test/CodeGen/PowerPC/dcbfl.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/dcbfl.ll
@@ -0,0 +1,15 @@
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s \
+; RUN:     -verify-machineinstrs -ppc-asm-full-reg-names \
+; RUN:     -ppc-vsr-nums-as-vr | FileCheck %s
+
+; Function Attrs: nounwind
+define void @dcbfl_test(i8* %a) {
+entry:
+  tail call void @llvm.ppc.dcbfl(i8* %a)
+; CHECK-LABEL: @dcbfl_test
+; CHECK: dcbfl 0, r3
+; CHECK-NEXT: blr
+ret void
+}
+
+declare void @llvm.ppc.dcbfl(i8*)
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -4337,6 +4337,11 @@
 def DCBFL  : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>;
 def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>;
 
+def : Pat<(int_ppc_dcbfl xoaddr:$dst),
+          (DCBFL xoaddr:$dst)>;
+def : Pat<(int_ppc_dcbflp xoaddr:$dst),
+          (DCBFLP xoaddr:$dst)>;
+
 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===================================================================
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -20,6 +20,8 @@
   def int_ppc_dcba  : Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbf  : GCCBuiltin<"__builtin_dcbf">,
                       Intrinsic<[], [llvm_ptr_ty], []>;
+  def int_ppc_dcbfl : Intrinsic<[], [llvm_ptr_ty], []>;
+  def int_ppc_dcbflp: Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbi  : Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbst : Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbt  : Intrinsic<[], [llvm_ptr_ty],


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