[PATCH] D68374: [X86] Add v32i8 shuffle lowering strategy to recognize two v4i64 vectors truncated to v4i8 and concatenated into the lower 8 bytes with undef/zero upper bytes.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:15539
+    return SDValue();
+  }
+
----------------
isSequentialOrUndefInRange(Mask, 0, 8, 0, 8) ?


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:15542
+  // Upper bits need to be zeroable.
+  for (int i = 8; i != 24; ++i)
+    if (!Zeroable[i])
----------------
Zeroable.extractBits(16, 8).isAllOnesValue() ?


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68374/new/

https://reviews.llvm.org/D68374