[PATCH] D68372: AMDGPU/GlobalISel: Split 64-bit vector extracts during RegBankSelect

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: tstellar, nhaehnle, kerbowa, scott.linder.
Herald added subscribers: Petar.Avramovic, t-tye, tpr, dstuttard, rovka, yaxunl, wdng, jvesely, kzhuravl.

Register indexing 64-bit elements is possible on the SALU, but not the
VALU. Handle splitting this into two 32-bit indexes. Extend waterfall
loop handling to allow moving a range of instructions.

I realized after implementing this that it would probably be better to just directly select the indexing instructions here, but this is a first step


https://reviews.llvm.org/D68372

Files:
  lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
  test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir

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