[PATCH] D67694: [Power9] Fix the missing pseudo instruction scheduling information for power9

[Jinsong Ji via Phabricator via llvm-commits]

jsji requested changes to this revision.
jsji added a comment.
This revision now requires changes to proceed.

This basically LGTM.

However, I'd like us to add more tests before we land it.

The change might not change the final schedule for existing codegen testcases , 
but the information during scheduling should change, 
so I think it shouldn't be too hard to come up with a few MIR tests that show the impact,
especially for toc related Pseudoes and floating point load/store psedudoes (eg: `DFSTOREf32`, `DFLOADf32`).



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Comment at: llvm/lib/Target/PowerPC/PPCInstrFormats.td:2168
 class PPCPostRAExpPseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
-    : PPCEmitTimePseudo<OOL, IOL, asmstr, pattern> {
+    : PPCEmitTimePseudoWithSchedInfo<OOL, IOL, asmstr, pattern> {
   let isPseudo = 1;
----------------
We did have SchedInfo in `P9InstrResources.td` before, so are they ignored? and always using the default latency?



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