[llvm] r373362 - [NFC][InstCombine] (Better) tests for sign-bit-smearing pattern
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 1 10:49:58 PDT 2019
Author: lebedevri
Date: Tue Oct 1 10:49:58 2019
New Revision: 373362
URL: http://llvm.org/viewvc/llvm-project?rev=373362&view=rev
Log:
[NFC][InstCombine] (Better) tests for sign-bit-smearing pattern
https://rise4fun.com/Alive/JRU
https://rise4fun.com/Alive/yR4 <- we can preserve 'exact'
Added:
llvm/trunk/test/Transforms/InstCombine/high-bit-signmask-with-trunc.ll
llvm/trunk/test/Transforms/InstCombine/high-bit-signmask.ll
Added: llvm/trunk/test/Transforms/InstCombine/high-bit-signmask-with-trunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/high-bit-signmask-with-trunc.ll?rev=373362&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/high-bit-signmask-with-trunc.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/high-bit-signmask-with-trunc.ll Tue Oct 1 10:49:58 2019
@@ -0,0 +1,153 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt %s -instcombine -S | FileCheck %s
+
+define i32 @t0(i64 %x) {
+; CHECK-LABEL: @t0(
+; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X:%.*]], 63
+; CHECK-NEXT: [[T1:%.*]] = trunc i64 [[T0]] to i32
+; CHECK-NEXT: [[R:%.*]] = sub nsw i32 0, [[T1]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %t0 = lshr i64 %x, 63
+ %t1 = trunc i64 %t0 to i32
+ %r = sub i32 0, %t1
+ ret i32 %r
+}
+define i32 @t1_exact(i64 %x) {
+; CHECK-LABEL: @t1_exact(
+; CHECK-NEXT: [[T0:%.*]] = lshr exact i64 [[X:%.*]], 63
+; CHECK-NEXT: [[T1:%.*]] = trunc i64 [[T0]] to i32
+; CHECK-NEXT: [[R:%.*]] = sub nsw i32 0, [[T1]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %t0 = lshr exact i64 %x, 63
+ %t1 = trunc i64 %t0 to i32
+ %r = sub i32 0, %t1
+ ret i32 %r
+}
+define i32 @t2(i64 %x) {
+; CHECK-LABEL: @t2(
+; CHECK-NEXT: [[T0:%.*]] = ashr i64 [[X:%.*]], 63
+; CHECK-NEXT: [[T1:%.*]] = trunc i64 [[T0]] to i32
+; CHECK-NEXT: [[R:%.*]] = sub i32 0, [[T1]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %t0 = ashr i64 %x, 63
+ %t1 = trunc i64 %t0 to i32
+ %r = sub i32 0, %t1
+ ret i32 %r
+}
+define i32 @t3_exact(i64 %x) {
+; CHECK-LABEL: @t3_exact(
+; CHECK-NEXT: [[T0:%.*]] = ashr exact i64 [[X:%.*]], 63
+; CHECK-NEXT: [[T1:%.*]] = trunc i64 [[T0]] to i32
+; CHECK-NEXT: [[R:%.*]] = sub i32 0, [[T1]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %t0 = ashr exact i64 %x, 63
+ %t1 = trunc i64 %t0 to i32
+ %r = sub i32 0, %t1
+ ret i32 %r
+}
+
+define <2 x i32> @t4(<2 x i64> %x) {
+; CHECK-LABEL: @t4(
+; CHECK-NEXT: [[T0:%.*]] = lshr <2 x i64> [[X:%.*]], <i64 63, i64 63>
+; CHECK-NEXT: [[T1:%.*]] = trunc <2 x i64> [[T0]] to <2 x i32>
+; CHECK-NEXT: [[R:%.*]] = sub nsw <2 x i32> zeroinitializer, [[T1]]
+; CHECK-NEXT: ret <2 x i32> [[R]]
+;
+ %t0 = lshr <2 x i64> %x, <i64 63, i64 63>
+ %t1 = trunc <2 x i64> %t0 to <2 x i32>
+ %r = sub <2 x i32> zeroinitializer, %t1
+ ret <2 x i32> %r
+}
+
+define <2 x i32> @t5(<2 x i64> %x) {
+; CHECK-LABEL: @t5(
+; CHECK-NEXT: [[T0:%.*]] = lshr <2 x i64> [[X:%.*]], <i64 63, i64 undef>
+; CHECK-NEXT: [[T1:%.*]] = trunc <2 x i64> [[T0]] to <2 x i32>
+; CHECK-NEXT: [[R:%.*]] = sub <2 x i32> <i32 0, i32 undef>, [[T1]]
+; CHECK-NEXT: ret <2 x i32> [[R]]
+;
+ %t0 = lshr <2 x i64> %x, <i64 63, i64 undef>
+ %t1 = trunc <2 x i64> %t0 to <2 x i32>
+ %r = sub <2 x i32> <i32 0, i32 undef>, %t1
+ ret <2 x i32> %r
+}
+
+declare void @use64(i64)
+declare void @use32(i32)
+
+define i32 @t6(i64 %x) {
+; CHECK-LABEL: @t6(
+; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X:%.*]], 63
+; CHECK-NEXT: call void @use64(i64 [[T0]])
+; CHECK-NEXT: [[T1:%.*]] = trunc i64 [[T0]] to i32
+; CHECK-NEXT: [[R:%.*]] = sub nsw i32 0, [[T1]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %t0 = lshr i64 %x, 63
+ call void @use64(i64 %t0)
+ %t1 = trunc i64 %t0 to i32
+ %r = sub i32 0, %t1
+ ret i32 %r
+}
+
+define i32 @n7(i64 %x) {
+; CHECK-LABEL: @n7(
+; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X:%.*]], 63
+; CHECK-NEXT: [[T1:%.*]] = trunc i64 [[T0]] to i32
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[R:%.*]] = sub nsw i32 0, [[T1]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %t0 = lshr i64 %x, 63
+ %t1 = trunc i64 %t0 to i32
+ call void @use32(i32 %t1)
+ %r = sub i32 0, %t1
+ ret i32 %r
+}
+
+define i32 @n8(i64 %x) {
+; CHECK-LABEL: @n8(
+; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X:%.*]], 63
+; CHECK-NEXT: call void @use64(i64 [[T0]])
+; CHECK-NEXT: [[T1:%.*]] = trunc i64 [[T0]] to i32
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[R:%.*]] = sub nsw i32 0, [[T1]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %t0 = lshr i64 %x, 63
+ call void @use64(i64 %t0)
+ %t1 = trunc i64 %t0 to i32
+ call void @use32(i32 %t1)
+ %r = sub i32 0, %t1
+ ret i32 %r
+}
+
+define i32 @n9(i64 %x) {
+; CHECK-LABEL: @n9(
+; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X:%.*]], 62
+; CHECK-NEXT: [[T1:%.*]] = trunc i64 [[T0]] to i32
+; CHECK-NEXT: [[R:%.*]] = sub nsw i32 0, [[T1]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %t0 = lshr i64 %x, 62
+ %t1 = trunc i64 %t0 to i32
+ %r = sub i32 0, %t1
+ ret i32 %r
+}
+
+define i32 @n10(i64 %x) {
+; CHECK-LABEL: @n10(
+; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X:%.*]], 63
+; CHECK-NEXT: [[T1:%.*]] = trunc i64 [[T0]] to i32
+; CHECK-NEXT: [[R:%.*]] = xor i32 [[T1]], 1
+; CHECK-NEXT: ret i32 [[R]]
+;
+ %t0 = lshr i64 %x, 63
+ %t1 = trunc i64 %t0 to i32
+ %r = sub i32 1, %t1
+ ret i32 %r
+}
Added: llvm/trunk/test/Transforms/InstCombine/high-bit-signmask.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/high-bit-signmask.ll?rev=373362&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/high-bit-signmask.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/high-bit-signmask.ll Tue Oct 1 10:49:58 2019
@@ -0,0 +1,126 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt %s -instcombine -S | FileCheck %s
+
+define i64 @t0(i64 %x) {
+; CHECK-LABEL: @t0(
+; CHECK-NEXT: [[R:%.*]] = ashr i64 [[X:%.*]], 63
+; CHECK-NEXT: ret i64 [[R]]
+;
+ %t0 = lshr i64 %x, 63
+ %r = sub i64 0, %t0
+ ret i64 %r
+}
+define i64 @t0_exact(i64 %x) {
+; CHECK-LABEL: @t0_exact(
+; CHECK-NEXT: [[R:%.*]] = ashr i64 [[X:%.*]], 63
+; CHECK-NEXT: ret i64 [[R]]
+;
+ %t0 = lshr exact i64 %x, 63
+ %r = sub i64 0, %t0
+ ret i64 %r
+}
+define i64 @t2(i64 %x) {
+; CHECK-LABEL: @t2(
+; CHECK-NEXT: [[R:%.*]] = lshr i64 [[X:%.*]], 63
+; CHECK-NEXT: ret i64 [[R]]
+;
+ %t0 = ashr i64 %x, 63
+ %r = sub i64 0, %t0
+ ret i64 %r
+}
+define i64 @t3_exact(i64 %x) {
+; CHECK-LABEL: @t3_exact(
+; CHECK-NEXT: [[R:%.*]] = lshr i64 [[X:%.*]], 63
+; CHECK-NEXT: ret i64 [[R]]
+;
+ %t0 = ashr exact i64 %x, 63
+ %r = sub i64 0, %t0
+ ret i64 %r
+}
+
+define <2 x i64> @t4(<2 x i64> %x) {
+; CHECK-LABEL: @t4(
+; CHECK-NEXT: [[R:%.*]] = ashr <2 x i64> [[X:%.*]], <i64 63, i64 63>
+; CHECK-NEXT: ret <2 x i64> [[R]]
+;
+ %t0 = lshr <2 x i64> %x, <i64 63, i64 63>
+ %r = sub <2 x i64> zeroinitializer, %t0
+ ret <2 x i64> %r
+}
+
+define <2 x i64> @t5(<2 x i64> %x) {
+; CHECK-LABEL: @t5(
+; CHECK-NEXT: [[T0:%.*]] = lshr <2 x i64> [[X:%.*]], <i64 63, i64 undef>
+; CHECK-NEXT: [[R:%.*]] = sub <2 x i64> <i64 0, i64 undef>, [[T0]]
+; CHECK-NEXT: ret <2 x i64> [[R]]
+;
+ %t0 = lshr <2 x i64> %x, <i64 63, i64 undef>
+ %r = sub <2 x i64> <i64 0, i64 undef>, %t0
+ ret <2 x i64> %r
+}
+
+declare void @use64(i64)
+declare void @use32(i64)
+
+define i64 @t6(i64 %x) {
+; CHECK-LABEL: @t6(
+; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X:%.*]], 63
+; CHECK-NEXT: call void @use64(i64 [[T0]])
+; CHECK-NEXT: [[R:%.*]] = ashr i64 [[X]], 63
+; CHECK-NEXT: ret i64 [[R]]
+;
+ %t0 = lshr i64 %x, 63
+ call void @use64(i64 %t0)
+ %r = sub i64 0, %t0
+ ret i64 %r
+}
+
+define i64 @n7(i64 %x) {
+; CHECK-LABEL: @n7(
+; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X:%.*]], 63
+; CHECK-NEXT: call void @use32(i64 [[T0]])
+; CHECK-NEXT: [[R:%.*]] = ashr i64 [[X]], 63
+; CHECK-NEXT: ret i64 [[R]]
+;
+ %t0 = lshr i64 %x, 63
+ call void @use32(i64 %t0)
+ %r = sub i64 0, %t0
+ ret i64 %r
+}
+
+define i64 @n8(i64 %x) {
+; CHECK-LABEL: @n8(
+; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X:%.*]], 63
+; CHECK-NEXT: call void @use64(i64 [[T0]])
+; CHECK-NEXT: call void @use32(i64 [[T0]])
+; CHECK-NEXT: [[R:%.*]] = ashr i64 [[X]], 63
+; CHECK-NEXT: ret i64 [[R]]
+;
+ %t0 = lshr i64 %x, 63
+ call void @use64(i64 %t0)
+ call void @use32(i64 %t0)
+ %r = sub i64 0, %t0
+ ret i64 %r
+}
+
+define i64 @n9(i64 %x) {
+; CHECK-LABEL: @n9(
+; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X:%.*]], 62
+; CHECK-NEXT: [[R:%.*]] = sub nsw i64 0, [[T0]]
+; CHECK-NEXT: ret i64 [[R]]
+;
+ %t0 = lshr i64 %x, 62
+ %r = sub i64 0, %t0
+ ret i64 %r
+}
+
+define i64 @n10(i64 %x) {
+; CHECK-LABEL: @n10(
+; CHECK-NEXT: [[T0:%.*]] = lshr i64 [[X:%.*]], 63
+; CHECK-NEXT: [[R:%.*]] = xor i64 [[T0]], 1
+; CHECK-NEXT: ret i64 [[R]]
+;
+ %t0 = lshr i64 %x, 63
+ %r = sub i64 1, %t0
+ ret i64 %r
+}
More information about the llvm-commits
mailing list