[PATCH] D68098: [AArch64][SVE] Adding patterns for floating point SVE add instructions.

[Ehsan Amiri via Phabricator via llvm-commits]

amehsan added a comment.

In D68098#1687669 <https://reviews.llvm.org/D68098#1687669>, @huntergr wrote:

> LGTM.
>
> You can add the extra multiclass for `ftsmul` if you wish, but it's not needed until someone implements a matching pattern for that instruction. We only match it against an ACLE intrinsic downstream, not common SDag nodes.


Thanks for the review and useful comments.


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