[llvm] r373234 - [X86] Add ANY_EXTEND to switch in ReplaceNodeResults, but just fall back to default handling.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Mon Sep 30 10:14:22 2019
New Revision: 373234

URL: http://llvm.org/viewvc/llvm-project?rev=373234&view=rev
Log:
[X86] Add ANY_EXTEND to switch in ReplaceNodeResults, but just fall back to default handling.

ANY_EXTEND of v8i8 is marked Custom on AVX512 for handling extends
from v8i8. But the type legalization infrastructure will call
ReplaceNodeResults for v8i8 results. We should just defer it the
default handling instead of asserting in the default of the switch.

Fixes PR43509.

Added:
    llvm/trunk/test/CodeGen/X86/pr43509.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=373234&r1=373233&r2=373234&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Sep 30 10:14:22 2019
@@ -27887,6 +27887,12 @@ void X86TargetLowering::ReplaceNodeResul
     }
     return;
   }
+  case ISD::ANY_EXTEND:
+    // Right now, only MVT::v8i8 has Custom action for an illegal type.
+    // It's intended to custom handle the input type.
+    assert(N->getValueType(0) == MVT::v8i8 &&
+           "Do not know how to legalize this Node");
+    return;
   case ISD::SIGN_EXTEND:
   case ISD::ZERO_EXTEND: {
     EVT VT = N->getValueType(0);

Added: llvm/trunk/test/CodeGen/X86/pr43509.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr43509.ll?rev=373234&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr43509.ll (added)
+++ llvm/trunk/test/CodeGen/X86/pr43509.ll Mon Sep 30 10:14:22 2019
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skx | FileCheck %s
+
+define <8 x i8> @foo(<8 x float> %arg) {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %bb
+; CHECK-NEXT:    vcmpgtps {{.*}}(%rip){1to8}, %ymm0, %k0
+; CHECK-NEXT:    vpmovm2b %k0, %xmm1
+; CHECK-NEXT:    vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT:    vcmpltps %ymm2, %ymm0, %k1
+; CHECK-NEXT:    vmovdqu8 {{.*}}(%rip), %xmm0 {%k1} {z}
+; CHECK-NEXT:    vpand %xmm0, %xmm1, %xmm0
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
+bb:
+  %tmp = xor <8 x i8> zeroinitializer, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  %tmp1 = fcmp reassoc nsz contract ogt <8 x float> %arg, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>
+  %tmp2 = zext <8 x i1> %tmp1 to <8 x i8>
+  %tmp3 = and <8 x i8> %tmp, %tmp2
+  %tmp4 = fcmp reassoc nsz contract ogt <8 x float> zeroinitializer, %arg
+  %tmp5 = or <8 x i1> zeroinitializer, %tmp4
+  %tmp6 = zext <8 x i1> %tmp5 to <8 x i8>
+  %tmp7 = and <8 x i8> %tmp3, %tmp6
+  ret <8 x i8> %tmp7
+}