[PATCH] D68200: [AMDGPU] Extend buffer intrinsics with swizzling

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

I thought this was a property of the resource descriptor? Why do you need to add it to the intrinsic?



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Comment at: include/llvm/IR/IntrinsicsAMDGPU.td:903
    llvm_i32_ty],      // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc on gfx10+)
+                      // swizzled buffer(imm; bit 3 = swz)
   [IntrReadMem, ImmArg<3>], "", [SDNPMemOperand]>,
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Need to use immarg for all of these


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Comment at: lib/Target/AMDGPU/SILoadStoreOptimizer.cpp:522
 
+  /* Do not merge VMEM buffer instructions with "swizzled" bit set. */
+  int swizzled = AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), AMDGPU::OpName::swz);
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Single line comment


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  rL LLVM

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  https://reviews.llvm.org/D68200/new/

https://reviews.llvm.org/D68200