[PATCH] D68098: [AArch64][SVE] Adding patterns for floating point SVE add instructions.

[Graham Hunter via Phabricator via llvm-commits]

huntergr added a comment.

Hi!

Thanks for taking an interest in SVE codegen. The tests look fine, but we had a different approach in mind for generating many of the patterns.  In this case instead of making separate `def : Pat<` lines for each type, we add an SDPatternOperator and pattern to the multiclass for that instruction type.

So FADD_ZZZ is an instance of sve_fp_3op_u_zd, and by changing that definition in SVEInstrFormats.td to look like the following code we create matchers for all the instructions using that template.

  class sve_fp_3op_u_zd<bits<2> sz, bits<3> opc, string asm,
                        ZPRRegOp zprty,
                        ValueType vt, ValueType vt2, SDPatternOperator op>
  : I<(outs zprty:$Zd), (ins  zprty:$Zn, zprty:$Zm),
    asm, "\t$Zd, $Zn, $Zm",
    "",
    [(set (vt zprty:$Zd), (op (vt zprty:$Zn), (vt2 zprty:$Zm)))]>, Sched<[]> {
    bits<5> Zd;
    bits<5> Zm;
    bits<5> Zn;
    let Inst{31-24} = 0b01100101;
    let Inst{23-22} = sz;
    let Inst{21}    = 0b0;
    let Inst{20-16} = Zm;
    let Inst{15-13} = 0b000;
    let Inst{12-10} = opc;
    let Inst{9-5}   = Zn;
    let Inst{4-0}   = Zd;
  }
  
  multiclass sve_fp_3op_u_zd<bits<3> opc, string asm, SDPatternOperator op> {
    def _H : sve_fp_3op_u_zd<0b01, opc, asm, ZPR16, nxv8f16, nxv8f16, op>;
    def _S : sve_fp_3op_u_zd<0b10, opc, asm, ZPR32, nxv4f32, nxv4f32, op>;
    def _D : sve_fp_3op_u_zd<0b11, opc, asm, ZPR64, nxv2f64, nxv2f64, op>;
  }

The instruction instantiations in AArch64SVEInstrInfo.td would then need to pass in the correct SDPatternOperator, with a `null_frag` operator for the others right now so that you don't add untested matchers:

   defm FADD_ZZZ    : sve_fp_3op_u_zd<0b000, "fadd", fadd>;
   defm FSUB_ZZZ    : sve_fp_3op_u_zd<0b001, "fsub", null_frag>;
   defm FMUL_ZZZ    : sve_fp_3op_u_zd<0b010, "fmul", null_frag>;
  ....

Please let me know if my explanation isn't clear enough :)


Repository:
  rL LLVM

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https://reviews.llvm.org/D68098