[PATCH] D67950: [TableGen] Fix a bug that MCSchedClassDesc is interfered between different SchedModel

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang created this revision.
steven.zhang added reviewers: jsji, atrick, RKSimon, craig.topper, javed.absar, PowerPC, nemanjai.
Herald added a subscriber: zzheng.
Herald added a project: LLVM.

Assume that, ModelA has scheduling resource for InstA and ModelB has scheduling resource for InstB. This is what the llvm::MCSchedClassDesc looks like:

  llvm::MCSchedClassDesc ModelASchedClasses[] = {
  ...
  InstA, 0, ...
  InstB, -1,...
  };
  
  llvm::MCSchedClassDesc ModelBSchedClasses[] = {
  ...
  InstA, -1,...
  InstB, 0,...
  };

The -1 means invalid num of macro ops, while it is valid if it is >=0. This is what we look like now:

  llvm::MCSchedClassDesc ModelASchedClasses[] = {
  ...
  InstA, 0, ...
  InstB, 0,...
  };
  
  llvm::MCSchedClassDesc ModelBSchedClasses[] = {
  ...
  InstA, 0,...
  InstB, 0,...
  };

And compiler hit the assertion here because the SCDesc is valid now for both InstA and InstB.

  if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
        && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()
        && SchedModel.isComplete()) {
      errs() << "DefIdx " << DefIdx << " exceeds machine model writes for "
             << *DefMI << " (Try with MCSchedModel.CompleteModel set to false)";
      llvm_unreachable("incomplete machine model");
    }


https://reviews.llvm.org/D67950

Files:
  llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll
  llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll
  llvm/test/TableGen/InvalidMCSchedClassDesc.td
  llvm/utils/TableGen/SubtargetEmitter.cpp

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