[PATCH] D51932: [AMDGPU] Fix-up cases where writelane has 2 SGPR operands

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: lib/Target/AMDGPU/SIFixSGPRCopies.cpp:820
+          bool Resolved = false;
+          for (auto MO : {&Src0, &Src1}) {
+            if (MRI.hasOneDef(MO->getReg())) {
----------------
No auto


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Comment at: lib/Target/AMDGPU/SIFixSGPRCopies.cpp:821-822
+          for (auto MO : {&Src0, &Src1}) {
+            if (MRI.hasOneDef(MO->getReg())) {
+              const MachineOperand &Def = *(MRI.def_begin(MO->getReg()));
+              if (MO->isReg() && Def.isReg() &&
----------------
The hasOneDef check is suspicious. You should be able to check getVRegDef and just a null check. This is missing a guard for virtual registers


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D51932/new/

https://reviews.llvm.org/D51932