[PATCH] D67741: [MTE] Handle MTE instructions in AArch64LoadStoreOptimizer.

Thu Sep 19 13:56:35 PDT 2019

eugenis added a comment.

I've noticed that the spec does not say that STGP with the same source and address register is unpredictable, and instead defines it to update the writeback register after the source register is read. This lets us merge STGP forward, but not backward. Implemented with tests.

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Comment at: llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp:211
+  case AArch64::STGOffset:
+  case AArch64::STZGOffset:
+  case AArch64::ST2GOffset:
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ostannard wrote:
> STZG and STZ2G store zero to the memory contents, so don't belong in this list according to the comment above. After reading the rest of the patch, I think it's the comment that's wrong, these instructions are allowed to write regular memory, but not with contents which depend on the address part of the input register.
Good point! Reworded the comment.

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Comment at: llvm/test/CodeGen/AArch64/ldst-opt-mte.mir:4
+
+### STG and its offset limits
+
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ostannard wrote:
> We should also test a mis-aligned offset (e.g. `$x0 = ADDXri $x0, 8, 0`) as well as the edges of the range.
Added a test for mis-aligned offset. What do you mean by the edges of the range? There are tests for extreme values of the offset in ADDXri, see test_STG_post2 .. test_STG_post5 below and the same for STGP.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67741/new/

https://reviews.llvm.org/D67741