[www-releases] r372328 - Check in 9.0.0 source and docs
Hans Wennborg via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 19 07:32:55 PDT 2019
Added: www-releases/trunk/9.0.0/docs/AMDGPU/gfx9_vsrc64_0.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/9.0.0/docs/AMDGPU/gfx9_vsrc64_0.html?rev=372328&view=auto
==============================================================================
--- www-releases/trunk/9.0.0/docs/AMDGPU/gfx9_vsrc64_0.html (added)
+++ www-releases/trunk/9.0.0/docs/AMDGPU/gfx9_vsrc64_0.html Thu Sep 19 07:32:46 2019
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+ <div class="section" id="vsrc">
+<span id="amdgpu-synid9-vsrc64-0"></span><h1>vsrc<a class="headerlink" href="#vsrc" title="Permalink to this headline">¶</a></h1>
+<p>Instruction input.</p>
+<p><em>Size:</em> 2 dwords.</p>
+<p><em>Operands:</em> <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-v"><span class="std std-ref">v</span></a></p>
+</div>
+
+
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\ No newline at end of file
Added: www-releases/trunk/9.0.0/docs/AMDGPU/gfx9_waitcnt.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/9.0.0/docs/AMDGPU/gfx9_waitcnt.html?rev=372328&view=auto
==============================================================================
--- www-releases/trunk/9.0.0/docs/AMDGPU/gfx9_waitcnt.html (added)
+++ www-releases/trunk/9.0.0/docs/AMDGPU/gfx9_waitcnt.html Thu Sep 19 07:32:46 2019
@@ -0,0 +1,170 @@
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+ <title>waitcnt — LLVM 9 documentation</title>
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+
+ <div class="section" id="waitcnt">
+<span id="amdgpu-synid9-waitcnt"></span><h1>waitcnt<a class="headerlink" href="#waitcnt" title="Permalink to this headline">¶</a></h1>
+<p>Counts of outstanding instructions to wait for.</p>
+<p>The bits of this operand have the following meaning:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="18%" />
+<col width="82%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Bits</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>3:0</td>
+<td>VM_CNT: vector memory operations count, lower bits.</td>
+</tr>
+<tr class="row-odd"><td>6:4</td>
+<td>EXP_CNT: export count.</td>
+</tr>
+<tr class="row-even"><td>11:8</td>
+<td>LGKM_CNT: LDS, GDS, Constant and Message count.</td>
+</tr>
+<tr class="row-odd"><td>15:14</td>
+<td>VM_CNT: vector memory operations count, upper bits.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>This operand may be specified as a positive 16-bit <a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer_number</span></a>
+or as a combination of the following symbolic helpers:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="24%" />
+<col width="76%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>vmcnt(<<em>N</em>>)</td>
+<td>VM_CNT value. <em>N</em> must not exceed the largest VM_CNT value.</td>
+</tr>
+<tr class="row-odd"><td>expcnt(<<em>N</em>>)</td>
+<td>EXP_CNT value. <em>N</em> must not exceed the largest EXP_CNT value.</td>
+</tr>
+<tr class="row-even"><td>lgkmcnt(<<em>N</em>>)</td>
+<td>LGKM_CNT value. <em>N</em> must not exceed the largest LGKM_CNT value.</td>
+</tr>
+<tr class="row-odd"><td>vmcnt_sat(<<em>N</em>>)</td>
+<td>VM_CNT value computed as min(<em>N</em>, the largest VM_CNT value).</td>
+</tr>
+<tr class="row-even"><td>expcnt_sat(<<em>N</em>>)</td>
+<td>EXP_CNT value computed as min(<em>N</em>, the largest EXP_CNT value).</td>
+</tr>
+<tr class="row-odd"><td>lgkmcnt_sat(<<em>N</em>>)</td>
+<td>LGKM_CNT value computed as min(<em>N</em>, the largest LGKM_CNT value).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>These helpers may be specified in any order. Ampersands and commas may be used as optional separators.</p>
+<p><em>N</em> is either an
+<a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a> or an
+<a class="reference internal" href="../AMDGPUOperandSyntax.html#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expression</span></a>.</p>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">s_waitcnt</span> <span class="mi">0</span>
+<span class="n">s_waitcnt</span> <span class="n">vmcnt</span><span class="p">(</span><span class="mi">1</span><span class="p">)</span>
+<span class="n">s_waitcnt</span> <span class="n">expcnt</span><span class="p">(</span><span class="mi">2</span><span class="p">)</span> <span class="n">lgkmcnt</span><span class="p">(</span><span class="mi">3</span><span class="p">)</span>
+<span class="n">s_waitcnt</span> <span class="n">vmcnt</span><span class="p">(</span><span class="mi">1</span><span class="p">)</span> <span class="n">expcnt</span><span class="p">(</span><span class="mi">2</span><span class="p">)</span> <span class="n">lgkmcnt</span><span class="p">(</span><span class="mi">3</span><span class="p">)</span>
+<span class="n">s_waitcnt</span> <span class="n">vmcnt</span><span class="p">(</span><span class="mi">1</span><span class="p">),</span> <span class="n">expcnt</span><span class="p">(</span><span class="mi">2</span><span class="p">),</span> <span class="n">lgkmcnt</span><span class="p">(</span><span class="mi">3</span><span class="p">)</span>
+<span class="n">s_waitcnt</span> <span class="n">vmcnt</span><span class="p">(</span><span class="mi">1</span><span class="p">)</span> <span class="o">&</span> <span class="n">lgkmcnt_sat</span><span class="p">(</span><span class="mi">100</span><span class="p">)</span> <span class="o">&</span> <span class="n">expcnt</span><span class="p">(</span><span class="mi">2</span><span class="p">)</span>
+</pre></div>
+</div>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
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Added: www-releases/trunk/9.0.0/docs/AMDGPUInstructionNotation.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/9.0.0/docs/AMDGPUInstructionNotation.html?rev=372328&view=auto
==============================================================================
--- www-releases/trunk/9.0.0/docs/AMDGPUInstructionNotation.html (added)
+++ www-releases/trunk/9.0.0/docs/AMDGPUInstructionNotation.html Thu Sep 19 07:32:46 2019
@@ -0,0 +1,209 @@
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+ alt="LLVM Logo" width="250" height="88"/></a>
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+ <h3>Navigation</h3>
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+ <a href="genindex.html" title="General Index"
+ accesskey="I">index</a></li>
+ <li class="right" >
+ <a href="StackMaps.html" title="Stack maps and patch points in LLVM"
+ accesskey="N">next</a> |</li>
+ <li class="right" >
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+ accesskey="P">previous</a> |</li>
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+ <div class="body" role="main">
+
+ <div class="section" id="amdgpu-instructions-notation">
+<h1>AMDGPU Instructions Notation<a class="headerlink" href="#amdgpu-instructions-notation" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#introduction" id="id4">Introduction</a></li>
+<li><a class="reference internal" href="#instructions" id="id5">Instructions</a><ul>
+<li><a class="reference internal" href="#notation" id="id6">Notation</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#opcode" id="id7">Opcode</a><ul>
+<li><a class="reference internal" href="#id1" id="id8">Notation</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#operands" id="id9">Operands</a><ul>
+<li><a class="reference internal" href="#amdgpu-syn-instruction-operand-notation" id="id10">Notation</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#modifiers" id="id11">Modifiers</a><ul>
+<li><a class="reference internal" href="#amdgpu-syn-instruction-modifier-notation" id="id12">Notation</a></li>
+</ul>
+</li>
+</ul>
+</div>
+<div class="section" id="introduction">
+<span id="amdgpu-syn-instruction-notation"></span><h2><a class="toc-backref" href="#id4">Introduction</a><a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
+<p>This is an overview of notation used to describe the syntax of AMDGPU assembler instructions.</p>
+<p>This notation mimics the <a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instructions"><span class="std std-ref">syntax of assembler instructions</span></a>
+except that instead of real operands and modifiers it provides references to their description.</p>
+</div>
+<div class="section" id="instructions">
+<h2><a class="toc-backref" href="#id5">Instructions</a><a class="headerlink" href="#instructions" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="notation">
+<h3><a class="toc-backref" href="#id6">Notation</a><a class="headerlink" href="#notation" title="Permalink to this headline">¶</a></h3>
+<p>This is the notation used to describe AMDGPU instructions:</p>
+<blockquote>
+<div><code class="docutils literal notranslate"><span class="pre"><</span></code><a class="reference internal" href="#amdgpu-syn-opcode-notation"><span class="std std-ref">opcode description</span></a><code class="docutils literal notranslate"><span class="pre">></span> <span class="pre"><</span></code><a class="reference internal" href="#amdgpu-syn-instruction-operands-notation"><span class="std std-ref">operands description</span></a><code class="docutils literal notranslate"><span class="pre">></span> <span class="pre"><</span></code><a class="reference internal" href="#amdgpu-syn-instruction-modifiers-notation"><span class="std std-ref">modifiers description</span></a><code class="docutils literal notranslate"><span class="pre">></span></code></div></blockquote>
+</div>
+</div>
+<div class="section" id="opcode">
+<span id="amdgpu-syn-opcode-notation"></span><h2><a class="toc-backref" href="#id7">Opcode</a><a class="headerlink" href="#opcode" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="id1">
+<h3><a class="toc-backref" href="#id8">Notation</a><a class="headerlink" href="#id1" title="Permalink to this headline">¶</a></h3>
+<p>TBD</p>
+</div>
+</div>
+<div class="section" id="operands">
+<span id="amdgpu-syn-instruction-operands-notation"></span><h2><a class="toc-backref" href="#id9">Operands</a><a class="headerlink" href="#operands" title="Permalink to this headline">¶</a></h2>
+<p>An instruction may have zero or more <em>operands</em>. They are comma-separated in the description:</p>
+<blockquote>
+<div><code class="docutils literal notranslate"><span class="pre"><</span></code><a class="reference internal" href="#amdgpu-syn-instruction-operand-notation"><span class="std std-ref">description of operand 0</span></a><code class="docutils literal notranslate"><span class="pre">>,</span> <span class="pre"><</span></code><a class="reference internal" href="#amdgpu-syn-instruction-operand-notation"><span class="std std-ref">description of operand 1</span></a><code class="docutils literal notranslate"><span class="pre">>,</span> <span class="pre">...</span></code></div></blockquote>
+<p>The order of <em>operands</em> is fixed. <em>Operands</em> cannot be omitted
+except for special cases described below.</p>
+<div class="section" id="amdgpu-syn-instruction-operand-notation">
+<span id="id2"></span><h3><a class="toc-backref" href="#id10">Notation</a><a class="headerlink" href="#amdgpu-syn-instruction-operand-notation" title="Permalink to this headline">¶</a></h3>
+<p>An operand is described using the following notation:</p>
+<blockquote>
+<div><em><name><tag0><tag1>â¦</em></div></blockquote>
+<p>Where:</p>
+<ul class="simple">
+<li><em>name</em> is a link to a description of the operand.</li>
+<li><em>tags</em> are optional. They are used to indicate special operand properties:</li>
+</ul>
+<blockquote id="amdgpu-syn-instruction-operand-tags">
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="15%" />
+<col width="85%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Operand tag</th>
+<th class="head">Meaning</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>:opt</td>
+<td>An optional operand.</td>
+</tr>
+<tr class="row-odd"><td>:m</td>
+<td>An operand which may be used with
+<a class="reference internal" href="AMDGPUModifierSyntax.html#amdgpu-synid-vop3-operand-modifiers"><span class="std std-ref">VOP3 operand modifiers</span></a> or
+<a class="reference internal" href="AMDGPUModifierSyntax.html#amdgpu-synid-sdwa-operand-modifiers"><span class="std std-ref">SDWA operand modifiers</span></a>.</td>
+</tr>
+<tr class="row-even"><td>:dst</td>
+<td>An input operand which may also serve as a destination
+if <a class="reference internal" href="AMDGPUModifierSyntax.html#amdgpu-synid-glc"><span class="std std-ref">glc</span></a> modifier is specified.</td>
+</tr>
+<tr class="row-odd"><td>:fx</td>
+<td>This is an <em>f32</em> or <em>f16</em> operand depending on
+<a class="reference internal" href="AMDGPUModifierSyntax.html#amdgpu-synid-mad-mix-op-sel-hi"><span class="std std-ref">m_op_sel_hi</span></a> modifier.</td>
+</tr>
+<tr class="row-even"><td>:<type></td>
+<td>Operand <em>type</em> differs from <em>type</em>
+<a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">implied by the opcode name</span></a>.
+This tag specifies actual operand <em>type</em>.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">src1</span><span class="p">:</span><span class="n">m</span> <span class="o">//</span> <span class="n">src1</span> <span class="n">operand</span> <span class="n">may</span> <span class="n">be</span> <span class="n">used</span> <span class="k">with</span> <span class="n">operand</span> <span class="n">modifiers</span>
+<span class="n">vdata</span><span class="p">:</span><span class="n">dst</span> <span class="o">//</span> <span class="n">vdata</span> <span class="n">operand</span> <span class="n">may</span> <span class="n">be</span> <span class="n">used</span> <span class="k">as</span> <span class="n">both</span> <span class="n">source</span> <span class="ow">and</span> <span class="n">destination</span>
+<span class="n">vdst</span><span class="p">:</span><span class="n">u32</span> <span class="o">//</span> <span class="n">vdst</span> <span class="n">operand</span> <span class="n">has</span> <span class="n">u32</span> <span class="nb">type</span>
+</pre></div>
+</div>
+</div>
+</div>
+<div class="section" id="modifiers">
+<span id="amdgpu-syn-instruction-modifiers-notation"></span><h2><a class="toc-backref" href="#id11">Modifiers</a><a class="headerlink" href="#modifiers" title="Permalink to this headline">¶</a></h2>
+<p>An instruction may have zero or more optional <em>modifiers</em>. They are space-separated in the description:</p>
+<blockquote>
+<div><code class="docutils literal notranslate"><span class="pre"><</span></code><a class="reference internal" href="#amdgpu-syn-instruction-modifier-notation"><span class="std std-ref">description of modifier 0</span></a><code class="docutils literal notranslate"><span class="pre">></span> <span class="pre"><</span></code><a class="reference internal" href="#amdgpu-syn-instruction-modifier-notation"><span class="std std-ref">description of modifier 1</span></a><code class="docutils literal notranslate"><span class="pre">></span> <span class="pre">...</span></code></div></blockquote>
+<p>The order of <em>modifiers</em> is fixed.</p>
+<div class="section" id="amdgpu-syn-instruction-modifier-notation">
+<span id="id3"></span><h3><a class="toc-backref" href="#id12">Notation</a><a class="headerlink" href="#amdgpu-syn-instruction-modifier-notation" title="Permalink to this headline">¶</a></h3>
+<p>A <em>modifier</em> is described using the following notation:</p>
+<blockquote>
+<div><em><name></em></div></blockquote>
+<p>Where <em>name</em> is a link to a description of the <em>modifier</em>.</p>
+</div>
+</div>
+</div>
+
+
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+ <div class="section" id="amdgpu-instruction-syntax">
+<h1>AMDGPU Instruction Syntax<a class="headerlink" href="#amdgpu-instruction-syntax" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#instructions" id="id3">Instructions</a><ul>
+<li><a class="reference internal" href="#syntax" id="id4">Syntax</a></li>
+<li><a class="reference internal" href="#opcode-mnemonic" id="id5">Opcode Mnemonic</a></li>
+<li><a class="reference internal" href="#type-and-size-suffices" id="id6">Type and Size Suffices</a></li>
+<li><a class="reference internal" href="#encoding-suffices" id="id7">Encoding Suffices</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#operands" id="id8">Operands</a><ul>
+<li><a class="reference internal" href="#id1" id="id9">Syntax</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#modifiers" id="id10">Modifiers</a><ul>
+<li><a class="reference internal" href="#id2" id="id11">Syntax</a></li>
+</ul>
+</li>
+</ul>
+</div>
+<div class="section" id="instructions">
+<span id="amdgpu-syn-instructions"></span><h2><a class="toc-backref" href="#id3">Instructions</a><a class="headerlink" href="#instructions" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="syntax">
+<h3><a class="toc-backref" href="#id4">Syntax</a><a class="headerlink" href="#syntax" title="Permalink to this headline">¶</a></h3>
+<p>An instruction has the following syntax:</p>
+<blockquote>
+<div><code class="docutils literal notranslate"><span class="pre"><</span></code><em>opcode mnemonic</em><code class="docutils literal notranslate"><span class="pre">></span> <span class="pre"><</span></code><em>operand0</em><code class="docutils literal notranslate"><span class="pre">>,</span> <span class="pre"><</span></code><em>operand1</em><code class="docutils literal notranslate"><span class="pre">>,...</span> <span class="pre"><</span></code><em>modifier0</em><code class="docutils literal notranslate"><span class="pre">></span> <span class="pre"><</span></code><em>modifier1</em><code class="docutils literal notranslate"><span class="pre">>...</span></code></div></blockquote>
+<p><a class="reference internal" href="AMDGPUOperandSyntax.html"><span class="doc">Operands</span></a> are normally comma-separated while
+<a class="reference internal" href="AMDGPUModifierSyntax.html"><span class="doc">modifiers</span></a> are space-separated.</p>
+<p>The order of <em>operands</em> and <em>modifiers</em> is fixed.
+Most <em>modifiers</em> are optional and may be omitted.</p>
+</div>
+<div class="section" id="opcode-mnemonic">
+<span id="amdgpu-syn-instruction-mnemo"></span><h3><a class="toc-backref" href="#id5">Opcode Mnemonic</a><a class="headerlink" href="#opcode-mnemonic" title="Permalink to this headline">¶</a></h3>
+<p>Opcode mnemonic describes opcode semantics and may include one or more suffices in this order:</p>
+<ul class="simple">
+<li><a class="reference internal" href="#amdgpu-syn-instruction-type"><span class="std std-ref">Destination operand type suffix</span></a>.</li>
+<li><a class="reference internal" href="#amdgpu-syn-instruction-type"><span class="std std-ref">Source operand type suffix</span></a>.</li>
+<li><a class="reference internal" href="#amdgpu-syn-instruction-enc"><span class="std std-ref">Encoding suffix</span></a>.</li>
+</ul>
+</div>
+<div class="section" id="type-and-size-suffices">
+<span id="amdgpu-syn-instruction-type"></span><h3><a class="toc-backref" href="#id6">Type and Size Suffices</a><a class="headerlink" href="#type-and-size-suffices" title="Permalink to this headline">¶</a></h3>
+<p>Instructions which operate with data have an implied type of <em>data</em> operands.
+This data type is specified as a suffix of instruction mnemonic.</p>
+<p>There are instructions which have 2 type suffices:
+the first is the data type of the destination operand,
+the second is the data type of source <em>data</em> operand(s).</p>
+<p>Note that data type specified by an instruction does not apply
+to other kinds of operands such as <em>addresses</em>, <em>offsets</em> and so on.</p>
+<p>The following table enumerates the most frequently used type suffices.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="52%" />
+<col width="27%" />
+<col width="20%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Type Suffices</th>
+<th class="head">Packed instruction?</th>
+<th class="head">Data Type</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>_b512, _b256, _b128, _b64, _b32, _b16, _b8</td>
+<td>No</td>
+<td>Bits.</td>
+</tr>
+<tr class="row-odd"><td>_u64, _u32, _u16, _u8</td>
+<td>No</td>
+<td>Unsigned integer.</td>
+</tr>
+<tr class="row-even"><td>_i64, _i32, _i16, _i8</td>
+<td>No</td>
+<td>Signed integer.</td>
+</tr>
+<tr class="row-odd"><td>_f64, _f32, _f16</td>
+<td>No</td>
+<td>Floating-point.</td>
+</tr>
+<tr class="row-even"><td>_b16, _u16, _i16, _f16</td>
+<td>Yes</td>
+<td>Packed.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Instructions which have no type suffices are assumed to operate with typeless data.
+The size of data is specified by size suffices:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="23%" />
+<col width="26%" />
+<col width="51%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Size Suffix</th>
+<th class="head">Implied data type</th>
+<th class="head">Required register size in dwords</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>-</td>
+<td>b32</td>
+<td>1</td>
+</tr>
+<tr class="row-odd"><td>x2</td>
+<td>b64</td>
+<td>2</td>
+</tr>
+<tr class="row-even"><td>x3</td>
+<td>b96</td>
+<td>3</td>
+</tr>
+<tr class="row-odd"><td>x4</td>
+<td>b128</td>
+<td>4</td>
+</tr>
+<tr class="row-even"><td>x8</td>
+<td>b256</td>
+<td>8</td>
+</tr>
+<tr class="row-odd"><td>x16</td>
+<td>b512</td>
+<td>16</td>
+</tr>
+<tr class="row-even"><td>x</td>
+<td>b32</td>
+<td>1</td>
+</tr>
+<tr class="row-odd"><td>xy</td>
+<td>b64</td>
+<td>2</td>
+</tr>
+<tr class="row-even"><td>xyz</td>
+<td>b96</td>
+<td>3</td>
+</tr>
+<tr class="row-odd"><td>xyzw</td>
+<td>b128</td>
+<td>4</td>
+</tr>
+<tr class="row-even"><td>d16_x</td>
+<td>b16</td>
+<td>1</td>
+</tr>
+<tr class="row-odd"><td>d16_xy</td>
+<td>b16x2</td>
+<td>2 for GFX8.0, 1 for GFX8.1 and GFX9</td>
+</tr>
+<tr class="row-even"><td>d16_xyz</td>
+<td>b16x3</td>
+<td>3 for GFX8.0, 2 for GFX8.1 and GFX9</td>
+</tr>
+<tr class="row-odd"><td>d16_xyzw</td>
+<td>b16x4</td>
+<td>4 for GFX8.0, 2 for GFX8.1 and GFX9</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">There are exceptions from rules described above.
+Operands which have type different from type specified by the opcode are
+<a class="reference internal" href="AMDGPUInstructionNotation.html#amdgpu-syn-instruction-operand-tags"><span class="std std-ref">tagged</span></a> in the description.</p>
+</div>
+<p>Examples of instructions with different types of source and destination operands:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">s_bcnt0_i32_b64</span>
+<span class="n">v_cvt_f32_u32</span>
+</pre></div>
+</div>
+<p>Examples of instructions with one data type:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">v_max3_f32</span>
+<span class="n">v_max3_i16</span>
+</pre></div>
+</div>
+<p>Examples of instructions which operate with packed data:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">v_pk_add_u16</span>
+<span class="n">v_pk_add_i16</span>
+<span class="n">v_pk_add_f16</span>
+</pre></div>
+</div>
+<p>Examples of typeless instructions which operate on b128 data:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">buffer_store_dwordx4</span>
+<span class="n">flat_load_dwordx4</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="encoding-suffices">
+<span id="amdgpu-syn-instruction-enc"></span><h3><a class="toc-backref" href="#id7">Encoding Suffices</a><a class="headerlink" href="#encoding-suffices" title="Permalink to this headline">¶</a></h3>
+<p>Most <em>VOP1</em>, <em>VOP2</em> and <em>VOPC</em> instructions have several variants:
+they may also be encoded in <em>VOP3</em>, <em>DPP</em> and <em>SDWA</em> formats.</p>
+<p>The assembler will automatically use optimal encoding based on instruction operands.
+To force specific encoding, one can add a suffix to the opcode of the instruction:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="75%" />
+<col width="25%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Encoding</th>
+<th class="head">Encoding Suffix</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>Native 32-bit encoding (<em>VOP1</em>, <em>VOP2</em> or <em>VOPC</em>)</td>
+<td>_e32</td>
+</tr>
+<tr class="row-odd"><td><em>VOP3</em> (64-bit) encoding</td>
+<td>_e64</td>
+</tr>
+<tr class="row-even"><td><em>DPP</em> encoding</td>
+<td>_dpp</td>
+</tr>
+<tr class="row-odd"><td><em>SDWA</em> encoding</td>
+<td>_sdwa</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>These suffices are used in this reference to indicate the assumed encoding.
+When no suffix is specified, a native encoding is implied.</p>
+</div>
+</div>
+<div class="section" id="operands">
+<h2><a class="toc-backref" href="#id8">Operands</a><a class="headerlink" href="#operands" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="id1">
+<h3><a class="toc-backref" href="#id9">Syntax</a><a class="headerlink" href="#id1" title="Permalink to this headline">¶</a></h3>
+<p>Syntax of most operands is described <a class="reference internal" href="AMDGPUOperandSyntax.html"><span class="doc">in this document</span></a>.</p>
+<p>For detailed information about operands follow <em>operand links</em> in GPU-specific documents:</p>
+<ul class="simple">
+<li><a class="reference internal" href="AMDGPU/AMDGPUAsmGFX7.html"><span class="doc">GFX7</span></a></li>
+<li><a class="reference internal" href="AMDGPU/AMDGPUAsmGFX8.html"><span class="doc">GFX8</span></a></li>
+<li><a class="reference internal" href="AMDGPU/AMDGPUAsmGFX9.html"><span class="doc">GFX9</span></a></li>
+<li><a class="reference internal" href="AMDGPU/AMDGPUAsmGFX10.html"><span class="doc">GFX10</span></a></li>
+</ul>
+</div>
+</div>
+<div class="section" id="modifiers">
+<h2><a class="toc-backref" href="#id10">Modifiers</a><a class="headerlink" href="#modifiers" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="id2">
+<h3><a class="toc-backref" href="#id11">Syntax</a><a class="headerlink" href="#id2" title="Permalink to this headline">¶</a></h3>
+<p>Syntax of modifiers is described <a class="reference internal" href="AMDGPUModifierSyntax.html"><span class="doc">in this document</span></a>.</p>
+<p>Information about modifiers supported for individual instructions may be found in GPU-specific documents:</p>
+<ul class="simple">
+<li><a class="reference internal" href="AMDGPU/AMDGPUAsmGFX7.html"><span class="doc">GFX7</span></a></li>
+<li><a class="reference internal" href="AMDGPU/AMDGPUAsmGFX8.html"><span class="doc">GFX8</span></a></li>
+<li><a class="reference internal" href="AMDGPU/AMDGPUAsmGFX9.html"><span class="doc">GFX9</span></a></li>
+<li><a class="reference internal" href="AMDGPU/AMDGPUAsmGFX10.html"><span class="doc">GFX10</span></a></li>
+</ul>
+</div>
+</div>
+</div>
+
+
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+ <div class="section" id="syntax-of-amdgpu-instruction-modifiers">
+<h1>Syntax of AMDGPU Instruction Modifiers<a class="headerlink" href="#syntax-of-amdgpu-instruction-modifiers" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#conventions" id="id30">Conventions</a></li>
+<li><a class="reference internal" href="#modifiers" id="id31">Modifiers</a><ul>
+<li><a class="reference internal" href="#ds-modifiers" id="id32">DS Modifiers</a><ul>
+<li><a class="reference internal" href="#offset8" id="id33">offset8</a></li>
+<li><a class="reference internal" href="#offset16" id="id34">offset16</a></li>
+<li><a class="reference internal" href="#swizzle-pattern" id="id35">swizzle pattern</a></li>
+<li><a class="reference internal" href="#gds" id="id36">gds</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#exp-modifiers" id="id37">EXP Modifiers</a><ul>
+<li><a class="reference internal" href="#done" id="id38">done</a></li>
+<li><a class="reference internal" href="#compr" id="id39">compr</a></li>
+<li><a class="reference internal" href="#vm" id="id40">vm</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#flat-modifiers" id="id41">FLAT Modifiers</a><ul>
+<li><a class="reference internal" href="#offset12" id="id42">offset12</a></li>
+<li><a class="reference internal" href="#offset13s" id="id43">offset13s</a></li>
+<li><a class="reference internal" href="#offset12s" id="id44">offset12s</a></li>
+<li><a class="reference internal" href="#offset11" id="id45">offset11</a></li>
+<li><a class="reference internal" href="#dlc" id="id46">dlc</a></li>
+<li><a class="reference internal" href="#glc" id="id47">glc</a></li>
+<li><a class="reference internal" href="#lds" id="id48">lds</a></li>
+<li><a class="reference internal" href="#slc" id="id49">slc</a></li>
+<li><a class="reference internal" href="#tfe" id="id50">tfe</a></li>
+<li><a class="reference internal" href="#nv" id="id51">nv</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#mimg-modifiers" id="id52">MIMG Modifiers</a><ul>
+<li><a class="reference internal" href="#dmask" id="id53">dmask</a></li>
+<li><a class="reference internal" href="#unorm" id="id54">unorm</a></li>
+<li><a class="reference internal" href="#id1" id="id55">glc</a></li>
+<li><a class="reference internal" href="#id2" id="id56">slc</a></li>
+<li><a class="reference internal" href="#r128" id="id57">r128</a></li>
+<li><a class="reference internal" href="#id3" id="id58">tfe</a></li>
+<li><a class="reference internal" href="#lwe" id="id59">lwe</a></li>
+<li><a class="reference internal" href="#da" id="id60">da</a></li>
+<li><a class="reference internal" href="#d16" id="id61">d16</a></li>
+<li><a class="reference internal" href="#a16" id="id62">a16</a></li>
+<li><a class="reference internal" href="#dim" id="id63">dim</a></li>
+<li><a class="reference internal" href="#id4" id="id64">dlc</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#miscellaneous-modifiers" id="id65">Miscellaneous Modifiers</a><ul>
+<li><a class="reference internal" href="#amdgpu-synid-dlc" id="id66">dlc</a></li>
+<li><a class="reference internal" href="#amdgpu-synid-glc" id="id67">glc</a></li>
+<li><a class="reference internal" href="#amdgpu-synid-lds" id="id68">lds</a></li>
+<li><a class="reference internal" href="#amdgpu-synid-nv" id="id69">nv</a></li>
+<li><a class="reference internal" href="#amdgpu-synid-slc" id="id70">slc</a></li>
+<li><a class="reference internal" href="#amdgpu-synid-tfe" id="id71">tfe</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#mubuf-mtbuf-modifiers" id="id72">MUBUF/MTBUF Modifiers</a><ul>
+<li><a class="reference internal" href="#amdgpu-synid-idxen" id="id73">idxen</a></li>
+<li><a class="reference internal" href="#offen" id="id74">offen</a></li>
+<li><a class="reference internal" href="#addr64" id="id75">addr64</a></li>
+<li><a class="reference internal" href="#amdgpu-synid-buf-offset12" id="id76">offset12</a></li>
+<li><a class="reference internal" href="#id12" id="id77">glc</a></li>
+<li><a class="reference internal" href="#id13" id="id78">slc</a></li>
+<li><a class="reference internal" href="#id14" id="id79">lds</a></li>
+<li><a class="reference internal" href="#id15" id="id80">dlc</a></li>
+<li><a class="reference internal" href="#id16" id="id81">tfe</a></li>
+<li><a class="reference internal" href="#dfmt" id="id82">dfmt</a></li>
+<li><a class="reference internal" href="#nfmt" id="id83">nfmt</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#smrd-smem-modifiers" id="id84">SMRD/SMEM Modifiers</a><ul>
+<li><a class="reference internal" href="#id17" id="id85">glc</a></li>
+<li><a class="reference internal" href="#id18" id="id86">nv</a></li>
+<li><a class="reference internal" href="#id19" id="id87">dlc</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#vintrp-modifiers" id="id88">VINTRP Modifiers</a><ul>
+<li><a class="reference internal" href="#high" id="id89">high</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#dpp8-modifiers" id="id90">DPP8 Modifiers</a><ul>
+<li><a class="reference internal" href="#dpp8-sel" id="id91">dpp8_sel</a></li>
+<li><a class="reference internal" href="#fi" id="id92">fi</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#dpp-dpp16-modifiers" id="id93">DPP/DPP16 Modifiers</a><ul>
+<li><a class="reference internal" href="#dpp-ctrl" id="id94">dpp_ctrl</a></li>
+<li><a class="reference internal" href="#dpp16-ctrl" id="id95">dpp16_ctrl</a></li>
+<li><a class="reference internal" href="#row-mask" id="id96">row_mask</a></li>
+<li><a class="reference internal" href="#bank-mask" id="id97">bank_mask</a></li>
+<li><a class="reference internal" href="#bound-ctrl" id="id98">bound_ctrl</a></li>
+<li><a class="reference internal" href="#amdgpu-synid-fi16" id="id99">fi</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#sdwa-modifiers" id="id100">SDWA Modifiers</a><ul>
+<li><a class="reference internal" href="#clamp" id="id101">clamp</a></li>
+<li><a class="reference internal" href="#omod" id="id102">omod</a></li>
+<li><a class="reference internal" href="#dst-sel" id="id103">dst_sel</a></li>
+<li><a class="reference internal" href="#dst-unused" id="id104">dst_unused</a></li>
+<li><a class="reference internal" href="#src0-sel" id="id105">src0_sel</a></li>
+<li><a class="reference internal" href="#src1-sel" id="id106">src1_sel</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#sdwa-operand-modifiers" id="id107">SDWA Operand Modifiers</a><ul>
+<li><a class="reference internal" href="#abs" id="id108">abs</a></li>
+<li><a class="reference internal" href="#neg" id="id109">neg</a></li>
+<li><a class="reference internal" href="#sext" id="id110">sext</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#vop3-modifiers" id="id111">VOP3 Modifiers</a><ul>
+<li><a class="reference internal" href="#op-sel" id="id112">op_sel</a></li>
+<li><a class="reference internal" href="#amdgpu-synid-clamp" id="id113">clamp</a></li>
+<li><a class="reference internal" href="#amdgpu-synid-omod" id="id114">omod</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#vop3-operand-modifiers" id="id115">VOP3 Operand Modifiers</a><ul>
+<li><a class="reference internal" href="#amdgpu-synid-abs" id="id116">abs</a></li>
+<li><a class="reference internal" href="#amdgpu-synid-neg" id="id117">neg</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#vop3p-modifiers" id="id118">VOP3P Modifiers</a><ul>
+<li><a class="reference internal" href="#amdgpu-synid-op-sel" id="id119">op_sel</a></li>
+<li><a class="reference internal" href="#op-sel-hi" id="id120">op_sel_hi</a></li>
+<li><a class="reference internal" href="#neg-lo" id="id121">neg_lo</a></li>
+<li><a class="reference internal" href="#neg-hi" id="id122">neg_hi</a></li>
+<li><a class="reference internal" href="#id26" id="id123">clamp</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#vop3p-v-mad-mix-modifiers" id="id124">VOP3P V_MAD_MIX Modifiers</a><ul>
+<li><a class="reference internal" href="#m-op-sel" id="id125">m_op_sel</a></li>
+<li><a class="reference internal" href="#m-op-sel-hi" id="id126">m_op_sel_hi</a></li>
+<li><a class="reference internal" href="#id27" id="id127">abs</a></li>
+<li><a class="reference internal" href="#id28" id="id128">neg</a></li>
+<li><a class="reference internal" href="#id29" id="id129">clamp</a></li>
+</ul>
+</li>
+</ul>
+</li>
+</ul>
+</div>
+<div class="section" id="conventions">
+<h2><a class="toc-backref" href="#id30">Conventions</a><a class="headerlink" href="#conventions" title="Permalink to this headline">¶</a></h2>
+<p>The following notation is used throughout this document:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="24%" />
+<col width="76%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Notation</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>{0..N}</td>
+<td>Any integer value in the range from 0 to N (inclusive).</td>
+</tr>
+<tr class="row-odd"><td><x></td>
+<td>Syntax and meaning of <em>x</em> is explained elsewhere.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="modifiers">
+<span id="amdgpu-syn-modifiers"></span><h2><a class="toc-backref" href="#id31">Modifiers</a><a class="headerlink" href="#modifiers" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="ds-modifiers">
+<h3><a class="toc-backref" href="#id32">DS Modifiers</a><a class="headerlink" href="#ds-modifiers" title="Permalink to this headline">¶</a></h3>
+<div class="section" id="offset8">
+<span id="amdgpu-synid-ds-offset8"></span><h4><a class="toc-backref" href="#id33">offset8</a><a class="headerlink" href="#offset8" title="Permalink to this headline">¶</a></h4>
+<p>Specifies an immediate unsigned 8-bit offset, in bytes. The default value is 0.</p>
+<p>Used with DS instructions which have 2 addresses.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="26%" />
+<col width="74%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>offset:{0..0xFF}</td>
+<td>Specifies an unsigned 8-bit offset as a positive
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">offset</span><span class="p">:</span><span class="mi">255</span>
+<span class="n">offset</span><span class="p">:</span><span class="mh">0xff</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="offset16">
+<span id="amdgpu-synid-ds-offset16"></span><h4><a class="toc-backref" href="#id34">offset16</a><a class="headerlink" href="#offset16" title="Permalink to this headline">¶</a></h4>
+<p>Specifies an immediate unsigned 16-bit offset, in bytes. The default value is 0.</p>
+<p>Used with DS instructions which have 1 address.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="27%" />
+<col width="73%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>offset:{0..0xFFFF}</td>
+<td>Specifies an unsigned 16-bit offset as a positive
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">offset</span><span class="p">:</span><span class="mi">65535</span>
+<span class="n">offset</span><span class="p">:</span><span class="mh">0xffff</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="swizzle-pattern">
+<span id="amdgpu-synid-sw-offset16"></span><h4><a class="toc-backref" href="#id35">swizzle pattern</a><a class="headerlink" href="#swizzle-pattern" title="Permalink to this headline">¶</a></h4>
+<p>This is a special modifier which may be used with <em>ds_swizzle_b32</em> instruction only.
+It specifies a swizzle pattern in numeric or symbolic form. The default value is 0.</p>
+<p>See AMD documentation for more information.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="48%" />
+<col width="52%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>offset:{0..0xFFFF}</td>
+<td>Specifies a 16-bit swizzle pattern.</td>
+</tr>
+<tr class="row-odd"><td>offset:swizzle(QUAD_PERM,{0..3},{0..3},{0..3},{0..3})</td>
+<td><p class="first">Specifies a quad permute mode pattern</p>
+<p class="last">Each number is a lane <em>id</em>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>offset:swizzle(BITMASK_PERM, â<mask>â)</td>
+<td><p class="first">Specifies a bitmask permute mode pattern.</p>
+<p>The pattern converts a 5-bit lane <em>id</em> to another
+lane <em>id</em> with which the lane interacts.</p>
+<p><em>mask</em> is a 5 character sequence which
+specifies how to transform the bits of the
+lane <em>id</em>.</p>
+<p>The following characters are allowed:</p>
+<ul class="last simple">
+<li>â0â - set bit to 0.</li>
+<li>â1â - set bit to 1.</li>
+<li>âpâ - preserve bit.</li>
+<li>âiâ - inverse bit.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td>offset:swizzle(BROADCAST,{2..32},{0..N})</td>
+<td><p class="first">Specifies a broadcast mode.</p>
+<p>Broadcasts the value of any particular lane to
+all lanes in its group.</p>
+<p>The first numeric parameter is a group
+size and must be equal to 2, 4, 8, 16 or 32.</p>
+<p>The second numeric parameter is an index of the
+lane being broadcasted.</p>
+<p class="last">The index must not exceed group size.</p>
+</td>
+</tr>
+<tr class="row-even"><td>offset:swizzle(SWAP,{1..16})</td>
+<td><p class="first">Specifies a swap mode.</p>
+<p class="last">Swaps the neighboring groups of
+1, 2, 4, 8 or 16 lanes.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>offset:swizzle(REVERSE,{2..32})</td>
+<td><p class="first">Specifies a reverse mode.</p>
+<p class="last">Reverses the lanes for groups of 2, 4, 8, 16 or 32 lanes.</p>
+</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Numeric parameters may be specified as either <a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a> or
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expressions</span></a>.</p>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">offset</span><span class="p">:</span><span class="mi">255</span>
+<span class="n">offset</span><span class="p">:</span><span class="mh">0xffff</span>
+<span class="n">offset</span><span class="p">:</span><span class="n">swizzle</span><span class="p">(</span><span class="n">QUAD_PERM</span><span class="p">,</span> <span class="mi">0</span><span class="p">,</span> <span class="mi">1</span><span class="p">,</span> <span class="mi">2</span> <span class="p">,</span><span class="mi">3</span><span class="p">)</span>
+<span class="n">offset</span><span class="p">:</span><span class="n">swizzle</span><span class="p">(</span><span class="n">BITMASK_PERM</span><span class="p">,</span> <span class="s2">"01pi0"</span><span class="p">)</span>
+<span class="n">offset</span><span class="p">:</span><span class="n">swizzle</span><span class="p">(</span><span class="n">BROADCAST</span><span class="p">,</span> <span class="mi">2</span><span class="p">,</span> <span class="mi">0</span><span class="p">)</span>
+<span class="n">offset</span><span class="p">:</span><span class="n">swizzle</span><span class="p">(</span><span class="n">SWAP</span><span class="p">,</span> <span class="mi">8</span><span class="p">)</span>
+<span class="n">offset</span><span class="p">:</span><span class="n">swizzle</span><span class="p">(</span><span class="n">REVERSE</span><span class="p">,</span> <span class="mi">30</span> <span class="o">+</span> <span class="mi">2</span><span class="p">)</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="gds">
+<span id="amdgpu-synid-gds"></span><h4><a class="toc-backref" href="#id36">gds</a><a class="headerlink" href="#gds" title="Permalink to this headline">¶</a></h4>
+<p>Specifies whether to use GDS or LDS memory (LDS is the default).</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>gds</td>
+<td>Use GDS memory.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="exp-modifiers">
+<h3><a class="toc-backref" href="#id37">EXP Modifiers</a><a class="headerlink" href="#exp-modifiers" title="Permalink to this headline">¶</a></h3>
+<div class="section" id="done">
+<span id="amdgpu-synid-done"></span><h4><a class="toc-backref" href="#id38">done</a><a class="headerlink" href="#done" title="Permalink to this headline">¶</a></h4>
+<p>Specifies if this is the last export from the shader to the target. By default,
+<em>exp</em> instruction does not finish an export sequence.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>done</td>
+<td>Indicates the last export operation.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="compr">
+<span id="amdgpu-synid-compr"></span><h4><a class="toc-backref" href="#id39">compr</a><a class="headerlink" href="#compr" title="Permalink to this headline">¶</a></h4>
+<p>Indicates if the data are compressed (data are not compressed by default).</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>compr</td>
+<td>Data are compressed.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="vm">
+<span id="amdgpu-synid-vm"></span><h4><a class="toc-backref" href="#id40">vm</a><a class="headerlink" href="#vm" title="Permalink to this headline">¶</a></h4>
+<p>Specifies valid mask flag state (off by default).</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>vm</td>
+<td>Set valid mask flag.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="flat-modifiers">
+<h3><a class="toc-backref" href="#id41">FLAT Modifiers</a><a class="headerlink" href="#flat-modifiers" title="Permalink to this headline">¶</a></h3>
+<div class="section" id="offset12">
+<span id="amdgpu-synid-flat-offset12"></span><h4><a class="toc-backref" href="#id42">offset12</a><a class="headerlink" href="#offset12" title="Permalink to this headline">¶</a></h4>
+<p>Specifies an immediate unsigned 12-bit offset, in bytes. The default value is 0.</p>
+<p>Cannot be used with <em>global/scratch</em> opcodes. GFX9 only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="24%" />
+<col width="76%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>offset:{0..4095}</td>
+<td>Specifies a 12-bit unsigned offset as a positive
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">offset</span><span class="p">:</span><span class="mi">4095</span>
+<span class="n">offset</span><span class="p">:</span><span class="mh">0xff</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="offset13s">
+<span id="amdgpu-synid-flat-offset13s"></span><h4><a class="toc-backref" href="#id43">offset13s</a><a class="headerlink" href="#offset13s" title="Permalink to this headline">¶</a></h4>
+<p>Specifies an immediate signed 13-bit offset, in bytes. The default value is 0.</p>
+<p>Can be used with <em>global/scratch</em> opcodes only. GFX9 only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="34%" />
+<col width="66%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>offset:{-4096..4095}</td>
+<td>Specifies a 13-bit signed offset as an
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">offset</span><span class="p">:</span><span class="o">-</span><span class="mi">4000</span>
+<span class="n">offset</span><span class="p">:</span><span class="mh">0x10</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="offset12s">
+<span id="amdgpu-synid-flat-offset12s"></span><h4><a class="toc-backref" href="#id44">offset12s</a><a class="headerlink" href="#offset12s" title="Permalink to this headline">¶</a></h4>
+<p>Specifies an immediate signed 12-bit offset, in bytes. The default value is 0.</p>
+<p>Can be used with <em>global/scratch</em> opcodes only.</p>
+<p>GFX10 only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="34%" />
+<col width="66%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>offset:{-2048..2047}</td>
+<td>Specifies a 12-bit signed offset as an
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">offset</span><span class="p">:</span><span class="o">-</span><span class="mi">2000</span>
+<span class="n">offset</span><span class="p">:</span><span class="mh">0x10</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="offset11">
+<span id="amdgpu-synid-flat-offset11"></span><h4><a class="toc-backref" href="#id45">offset11</a><a class="headerlink" href="#offset11" title="Permalink to this headline">¶</a></h4>
+<p>Specifies an immediate unsigned 11-bit offset, in bytes. The default value is 0.</p>
+<p>Cannot be used with <em>global/scratch</em> opcodes.</p>
+<p>GFX10 only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="24%" />
+<col width="76%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>offset:{0..2047}</td>
+<td>Specifies an 11-bit unsigned offset as a positive
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">offset</span><span class="p">:</span><span class="mi">2047</span>
+<span class="n">offset</span><span class="p">:</span><span class="mh">0xff</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="dlc">
+<h4><a class="toc-backref" href="#id46">dlc</a><a class="headerlink" href="#dlc" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-dlc"><span class="std std-ref">here</span></a>. GFX10 only.</p>
+</div>
+<div class="section" id="glc">
+<h4><a class="toc-backref" href="#id47">glc</a><a class="headerlink" href="#glc" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-glc"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="lds">
+<h4><a class="toc-backref" href="#id48">lds</a><a class="headerlink" href="#lds" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-lds"><span class="std std-ref">here</span></a>. GFX10 only.</p>
+</div>
+<div class="section" id="slc">
+<h4><a class="toc-backref" href="#id49">slc</a><a class="headerlink" href="#slc" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-slc"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="tfe">
+<h4><a class="toc-backref" href="#id50">tfe</a><a class="headerlink" href="#tfe" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-tfe"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="nv">
+<h4><a class="toc-backref" href="#id51">nv</a><a class="headerlink" href="#nv" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-nv"><span class="std std-ref">here</span></a>.</p>
+</div>
+</div>
+<div class="section" id="mimg-modifiers">
+<h3><a class="toc-backref" href="#id52">MIMG Modifiers</a><a class="headerlink" href="#mimg-modifiers" title="Permalink to this headline">¶</a></h3>
+<div class="section" id="dmask">
+<span id="amdgpu-synid-dmask"></span><h4><a class="toc-backref" href="#id53">dmask</a><a class="headerlink" href="#dmask" title="Permalink to this headline">¶</a></h4>
+<p>Specifies which channels (image components) are used by the operation. By default, no channels
+are used.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="22%" />
+<col width="78%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>dmask:{0..15}</td>
+<td><p class="first">Specifies image channels as a positive
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</p>
+<p>Each bit corresponds to one of 4 image
+components (RGBA).</p>
+<p class="last">If the specified bit value
+is 0, the component is not used, value 1 means
+that the component is used.</p>
+</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>This modifier has some limitations depending on instruction kind:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="68%" />
+<col width="32%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Instruction Kind</th>
+<th class="head">Valid dmask Values</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>32-bit atomic <em>cmpswap</em></td>
+<td>0x3</td>
+</tr>
+<tr class="row-odd"><td>32-bit atomic instructions except for <em>cmpswap</em></td>
+<td>0x1</td>
+</tr>
+<tr class="row-even"><td>64-bit atomic <em>cmpswap</em></td>
+<td>0xF</td>
+</tr>
+<tr class="row-odd"><td>64-bit atomic instructions except for <em>cmpswap</em></td>
+<td>0x3</td>
+</tr>
+<tr class="row-even"><td><em>gather4</em></td>
+<td>0x1, 0x2, 0x4, 0x8</td>
+</tr>
+<tr class="row-odd"><td>Other instructions</td>
+<td>any value</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">dmask</span><span class="p">:</span><span class="mh">0xf</span>
+<span class="n">dmask</span><span class="p">:</span><span class="mb">0b1111</span>
+<span class="n">dmask</span><span class="p">:</span><span class="mi">3</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="unorm">
+<span id="amdgpu-synid-unorm"></span><h4><a class="toc-backref" href="#id54">unorm</a><a class="headerlink" href="#unorm" title="Permalink to this headline">¶</a></h4>
+<p>Specifies whether the address is normalized or not (the address is normalized by default).</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="38%" />
+<col width="63%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>unorm</td>
+<td>Force the address to be unnormalized.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="id1">
+<h4><a class="toc-backref" href="#id55">glc</a><a class="headerlink" href="#id1" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-glc"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="id2">
+<h4><a class="toc-backref" href="#id56">slc</a><a class="headerlink" href="#id2" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-slc"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="r128">
+<span id="amdgpu-synid-r128"></span><h4><a class="toc-backref" href="#id57">r128</a><a class="headerlink" href="#r128" title="Permalink to this headline">¶</a></h4>
+<p>Specifies texture resource size. The default size is 256 bits.</p>
+<p>GFX7, GFX8 and GFX10 only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="28%" />
+<col width="72%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>r128</td>
+<td>Specifies 128 bits texture resource size.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">Using this modifier should descrease <em>rsrc</em> operand size from 8 to 4 dwords, but assembler does not currently support this feature.</p>
+</div>
+</div>
+<div class="section" id="id3">
+<h4><a class="toc-backref" href="#id58">tfe</a><a class="headerlink" href="#id3" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-tfe"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="lwe">
+<span id="amdgpu-synid-lwe"></span><h4><a class="toc-backref" href="#id59">lwe</a><a class="headerlink" href="#lwe" title="Permalink to this headline">¶</a></h4>
+<p>Specifies LOD warning status (LOD warning is disabled by default).</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>lwe</td>
+<td>Enables LOD warning.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="da">
+<span id="amdgpu-synid-da"></span><h4><a class="toc-backref" href="#id60">da</a><a class="headerlink" href="#da" title="Permalink to this headline">¶</a></h4>
+<p>Specifies if an array index must be sent to TA. By default, array index is not sent.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>da</td>
+<td>Send an array-index to TA.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="d16">
+<span id="amdgpu-synid-d16"></span><h4><a class="toc-backref" href="#id61">d16</a><a class="headerlink" href="#d16" title="Permalink to this headline">¶</a></h4>
+<p>Specifies data size: 16 or 32 bits (32 bits by default). Not supported by GFX7.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>d16</td>
+<td><p class="first">Enables 16-bits data mode.</p>
+<p>On loads, convert data in memory to 16-bit
+format before storing it in VGPRs.</p>
+<p>For stores, convert 16-bit data in VGPRs to
+32 bits before going to memory.</p>
+<p>Note that GFX8.0 does not support data packing.
+Each 16-bit data element occupies 1 VGPR.</p>
+<p class="last">GFX8.1, GFX9 and GFX10 support data packing.
+Each pair of 16-bit data elements
+occupies 1 VGPR.</p>
+</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="a16">
+<span id="amdgpu-synid-a16"></span><h4><a class="toc-backref" href="#id62">a16</a><a class="headerlink" href="#a16" title="Permalink to this headline">¶</a></h4>
+<p>Specifies size of image address components: 16 or 32 bits (32 bits by default).
+GFX9 and GFX10 only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>a16</td>
+<td>Enables 16-bits image address components.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="dim">
+<span id="amdgpu-synid-dim"></span><h4><a class="toc-backref" href="#id63">dim</a><a class="headerlink" href="#dim" title="Permalink to this headline">¶</a></h4>
+<p>Specifies surface dimension. This is a mandatory modifier. There is no default value.</p>
+<p>GFX10 only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="35%" />
+<col width="65%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>dim:1D</td>
+<td>One-dimensional image.</td>
+</tr>
+<tr class="row-odd"><td>dim:2D</td>
+<td>Two-dimensional image.</td>
+</tr>
+<tr class="row-even"><td>dim:3D</td>
+<td>Three-dimensional image.</td>
+</tr>
+<tr class="row-odd"><td>dim:CUBE</td>
+<td>Cubemap array.</td>
+</tr>
+<tr class="row-even"><td>dim:1D_ARRAY</td>
+<td>One-dimensional image array.</td>
+</tr>
+<tr class="row-odd"><td>dim:2D_ARRAY</td>
+<td>Two-dimensional image array.</td>
+</tr>
+<tr class="row-even"><td>dim:2D_MSAA</td>
+<td>Two-dimensional multi-sample auto-aliasing image.</td>
+</tr>
+<tr class="row-odd"><td>dim:2D_MSAA_ARRAY</td>
+<td>Two-dimensional multi-sample auto-aliasing image array.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>The following table defines an alternative syntax which is supported
+for compatibility with SP3 assembler:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="35%" />
+<col width="65%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>dim:SQ_RSRC_IMG_1D</td>
+<td>One-dimensional image.</td>
+</tr>
+<tr class="row-odd"><td>dim:SQ_RSRC_IMG_2D</td>
+<td>Two-dimensional image.</td>
+</tr>
+<tr class="row-even"><td>dim:SQ_RSRC_IMG_3D</td>
+<td>Three-dimensional image.</td>
+</tr>
+<tr class="row-odd"><td>dim:SQ_RSRC_IMG_CUBE</td>
+<td>Cubemap array.</td>
+</tr>
+<tr class="row-even"><td>dim:SQ_RSRC_IMG_1D_ARRAY</td>
+<td>One-dimensional image array.</td>
+</tr>
+<tr class="row-odd"><td>dim:SQ_RSRC_IMG_2D_ARRAY</td>
+<td>Two-dimensional image array.</td>
+</tr>
+<tr class="row-even"><td>dim:SQ_RSRC_IMG_2D_MSAA</td>
+<td>Two-dimensional multi-sample auto-aliasing image.</td>
+</tr>
+<tr class="row-odd"><td>dim:SQ_RSRC_IMG_2D_MSAA_ARRAY</td>
+<td>Two-dimensional multi-sample auto-aliasing image array.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="id4">
+<h4><a class="toc-backref" href="#id64">dlc</a><a class="headerlink" href="#id4" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-dlc"><span class="std std-ref">here</span></a>. GFX10 only.</p>
+</div>
+</div>
+<div class="section" id="miscellaneous-modifiers">
+<h3><a class="toc-backref" href="#id65">Miscellaneous Modifiers</a><a class="headerlink" href="#miscellaneous-modifiers" title="Permalink to this headline">¶</a></h3>
+<div class="section" id="amdgpu-synid-dlc">
+<span id="id5"></span><h4><a class="toc-backref" href="#id66">dlc</a><a class="headerlink" href="#amdgpu-synid-dlc" title="Permalink to this headline">¶</a></h4>
+<p>Controls device level cache policy for memory operations. Used for synchronization.
+When specified, forces operation to bypass device level cache making the operation device
+level coherent. By default, instructions use device level cache.</p>
+<p>GFX10 only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>dlc</td>
+<td>Bypass device level cache.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="amdgpu-synid-glc">
+<span id="id6"></span><h4><a class="toc-backref" href="#id67">glc</a><a class="headerlink" href="#amdgpu-synid-glc" title="Permalink to this headline">¶</a></h4>
+<p>This modifier has different meaning for loads, stores, and atomic operations.
+The default value is off (0).</p>
+<p>See AMD documentation for details.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>glc</td>
+<td>Set glc bit to 1.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="amdgpu-synid-lds">
+<span id="id7"></span><h4><a class="toc-backref" href="#id68">lds</a><a class="headerlink" href="#amdgpu-synid-lds" title="Permalink to this headline">¶</a></h4>
+<p>Specifies where to store the result: VGPRs or LDS (VGPRs by default).</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="60%" />
+<col width="40%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>lds</td>
+<td>Store result in LDS.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="amdgpu-synid-nv">
+<span id="id8"></span><h4><a class="toc-backref" href="#id69">nv</a><a class="headerlink" href="#amdgpu-synid-nv" title="Permalink to this headline">¶</a></h4>
+<p>Specifies if instruction is operating on non-volatile memory. By default, memory is volatile.</p>
+<p>GFX9 only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>nv</td>
+<td>Indicates that instruction operates on
+non-volatile memory.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="amdgpu-synid-slc">
+<span id="id9"></span><h4><a class="toc-backref" href="#id70">slc</a><a class="headerlink" href="#amdgpu-synid-slc" title="Permalink to this headline">¶</a></h4>
+<p>Specifies cache policy. The default value is off (0).</p>
+<p>See AMD documentation for details.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>slc</td>
+<td>Set slc bit to 1.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="amdgpu-synid-tfe">
+<span id="id10"></span><h4><a class="toc-backref" href="#id71">tfe</a><a class="headerlink" href="#amdgpu-synid-tfe" title="Permalink to this headline">¶</a></h4>
+<p>Controls access to partially resident textures. The default value is off (0).</p>
+<p>See AMD documentation for details.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>tfe</td>
+<td>Set tfe bit to 1.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="mubuf-mtbuf-modifiers">
+<h3><a class="toc-backref" href="#id72">MUBUF/MTBUF Modifiers</a><a class="headerlink" href="#mubuf-mtbuf-modifiers" title="Permalink to this headline">¶</a></h3>
+<div class="section" id="amdgpu-synid-idxen">
+<span id="idxen"></span><h4><a class="toc-backref" href="#id73">idxen</a><a class="headerlink" href="#amdgpu-synid-idxen" title="Permalink to this headline">¶</a></h4>
+<p>Specifies whether address components include an index. By default, no components are used.</p>
+<p>Can be used together with <a class="reference internal" href="#amdgpu-synid-offen"><span class="std std-ref">offen</span></a>.</p>
+<p>Cannot be used with <a class="reference internal" href="#amdgpu-synid-addr64"><span class="std std-ref">addr64</span></a>.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>idxen</td>
+<td>Address components include an index.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="offen">
+<span id="amdgpu-synid-offen"></span><h4><a class="toc-backref" href="#id74">offen</a><a class="headerlink" href="#offen" title="Permalink to this headline">¶</a></h4>
+<p>Specifies whether address components include an offset. By default, no components are used.</p>
+<p>Can be used together with <a class="reference internal" href="#amdgpu-synid-idxen"><span class="std std-ref">idxen</span></a>.</p>
+<p>Cannot be used with <a class="reference internal" href="#amdgpu-synid-addr64"><span class="std std-ref">addr64</span></a>.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>offen</td>
+<td>Address components include an offset.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="addr64">
+<span id="amdgpu-synid-addr64"></span><h4><a class="toc-backref" href="#id75">addr64</a><a class="headerlink" href="#addr64" title="Permalink to this headline">¶</a></h4>
+<p>Specifies whether a 64-bit address is used. By default, no address is used.</p>
+<p>GFX7 only. Cannot be used with <a class="reference internal" href="#amdgpu-synid-offen"><span class="std std-ref">offen</span></a> and
+<a class="reference internal" href="#amdgpu-synid-idxen"><span class="std std-ref">idxen</span></a> modifiers.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>addr64</td>
+<td>A 64-bit address is used.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="amdgpu-synid-buf-offset12">
+<span id="id11"></span><h4><a class="toc-backref" href="#id76">offset12</a><a class="headerlink" href="#amdgpu-synid-buf-offset12" title="Permalink to this headline">¶</a></h4>
+<p>Specifies an immediate unsigned 12-bit offset, in bytes. The default value is 0.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="36%" />
+<col width="64%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>offset:{0..0xFFF}</td>
+<td>Specifies a 12-bit unsigned offset as a positive
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">offset</span><span class="p">:</span><span class="mi">0</span>
+<span class="n">offset</span><span class="p">:</span><span class="mh">0x10</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="id12">
+<h4><a class="toc-backref" href="#id77">glc</a><a class="headerlink" href="#id12" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-glc"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="id13">
+<h4><a class="toc-backref" href="#id78">slc</a><a class="headerlink" href="#id13" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-slc"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="id14">
+<h4><a class="toc-backref" href="#id79">lds</a><a class="headerlink" href="#id14" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-lds"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="id15">
+<h4><a class="toc-backref" href="#id80">dlc</a><a class="headerlink" href="#id15" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-dlc"><span class="std std-ref">here</span></a>. GFX10 only.</p>
+</div>
+<div class="section" id="id16">
+<h4><a class="toc-backref" href="#id81">tfe</a><a class="headerlink" href="#id16" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-tfe"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="dfmt">
+<span id="amdgpu-synid-dfmt"></span><h4><a class="toc-backref" href="#id82">dfmt</a><a class="headerlink" href="#dfmt" title="Permalink to this headline">¶</a></h4>
+<p>TBD</p>
+</div>
+<div class="section" id="nfmt">
+<span id="amdgpu-synid-nfmt"></span><h4><a class="toc-backref" href="#id83">nfmt</a><a class="headerlink" href="#nfmt" title="Permalink to this headline">¶</a></h4>
+<p>TBD</p>
+</div>
+</div>
+<div class="section" id="smrd-smem-modifiers">
+<h3><a class="toc-backref" href="#id84">SMRD/SMEM Modifiers</a><a class="headerlink" href="#smrd-smem-modifiers" title="Permalink to this headline">¶</a></h3>
+<div class="section" id="id17">
+<h4><a class="toc-backref" href="#id85">glc</a><a class="headerlink" href="#id17" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-glc"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="id18">
+<h4><a class="toc-backref" href="#id86">nv</a><a class="headerlink" href="#id18" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-nv"><span class="std std-ref">here</span></a>. GFX9 only.</p>
+</div>
+<div class="section" id="id19">
+<h4><a class="toc-backref" href="#id87">dlc</a><a class="headerlink" href="#id19" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-dlc"><span class="std std-ref">here</span></a>. GFX10 only.</p>
+</div>
+</div>
+<div class="section" id="vintrp-modifiers">
+<h3><a class="toc-backref" href="#id88">VINTRP Modifiers</a><a class="headerlink" href="#vintrp-modifiers" title="Permalink to this headline">¶</a></h3>
+<div class="section" id="high">
+<span id="amdgpu-synid-high"></span><h4><a class="toc-backref" href="#id89">high</a><a class="headerlink" href="#high" title="Permalink to this headline">¶</a></h4>
+<p>Specifies which half of the LDS word to use. Low half of LDS word is used by default.
+GFX9 and GFX10 only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="56%" />
+<col width="44%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>high</td>
+<td>Use high half of LDS word.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="dpp8-modifiers">
+<h3><a class="toc-backref" href="#id90">DPP8 Modifiers</a><a class="headerlink" href="#dpp8-modifiers" title="Permalink to this headline">¶</a></h3>
+<p>GFX10 only.</p>
+<div class="section" id="dpp8-sel">
+<span id="amdgpu-synid-dpp8-sel"></span><h4><a class="toc-backref" href="#id91">dpp8_sel</a><a class="headerlink" href="#dpp8-sel" title="Permalink to this headline">¶</a></h4>
+<p>Selects which lane to pull data from, within a group of 8 lanes. This is a mandatory modifier.
+There is no default value.</p>
+<p>GFX10 only.</p>
+<p>The <em>dpp8_sel</em> modifier must specify exactly 8 values, each ranging from 0 to 7.
+First value selects which lane to read from to supply data into lane 0.
+Second value controls value for lane 1 and so on.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="70%" />
+<col width="30%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>dpp8:[{0..7},{0..7},{0..7},{0..7},{0..7},{0..7},{0..7},{0..7}]</td>
+<td>Select lanes to read from.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">dpp8</span><span class="p">:[</span><span class="mi">7</span><span class="p">,</span><span class="mi">6</span><span class="p">,</span><span class="mi">5</span><span class="p">,</span><span class="mi">4</span><span class="p">,</span><span class="mi">3</span><span class="p">,</span><span class="mi">2</span><span class="p">,</span><span class="mi">1</span><span class="p">,</span><span class="mi">0</span><span class="p">]</span>
+<span class="n">dpp8</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span><span class="mi">1</span><span class="p">,</span><span class="mi">0</span><span class="p">,</span><span class="mi">1</span><span class="p">,</span><span class="mi">0</span><span class="p">,</span><span class="mi">1</span><span class="p">,</span><span class="mi">0</span><span class="p">,</span><span class="mi">1</span><span class="p">]</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="fi">
+<span id="amdgpu-synid-fi8"></span><h4><a class="toc-backref" href="#id92">fi</a><a class="headerlink" href="#fi" title="Permalink to this headline">¶</a></h4>
+<p>Controls interaction with inactive lanes for <em>dpp8</em> instructions. The default value is zero.</p>
+<p>Note. <em>Inactive</em> lanes are those whose <a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-exec"><span class="std std-ref">exec</span></a> mask bit is zero.</p>
+<p>GFX10 only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="40%" />
+<col width="60%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>fi:0</td>
+<td>Fetch zero when accessing data from inactive lanes.</td>
+</tr>
+<tr class="row-odd"><td>fi:1</td>
+<td>Fetch pre-exist values from inactive lanes.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="dpp-dpp16-modifiers">
+<h3><a class="toc-backref" href="#id93">DPP/DPP16 Modifiers</a><a class="headerlink" href="#dpp-dpp16-modifiers" title="Permalink to this headline">¶</a></h3>
+<p>GFX8, GFX9 and GFX10 only.</p>
+<div class="section" id="dpp-ctrl">
+<span id="amdgpu-synid-dpp-ctrl"></span><h4><a class="toc-backref" href="#id94">dpp_ctrl</a><a class="headerlink" href="#dpp-ctrl" title="Permalink to this headline">¶</a></h4>
+<p>Specifies how data are shared between threads. This is a mandatory modifier.
+There is no default value.</p>
+<p>GFX8 and GFX9 only. Use <a class="reference internal" href="#amdgpu-synid-dpp16-ctrl"><span class="std std-ref">dpp16_ctrl</span></a> for GFX10.</p>
+<p>Note. The lanes of a wavefront are organized in four <em>rows</em> and four <em>banks</em>.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>quad_perm:[{0..3},{0..3},{0..3},{0..3}]</td>
+<td>Full permute of 4 threads.</td>
+</tr>
+<tr class="row-odd"><td>row_mirror</td>
+<td>Mirror threads within row.</td>
+</tr>
+<tr class="row-even"><td>row_half_mirror</td>
+<td>Mirror threads within 1/2 row (8 threads).</td>
+</tr>
+<tr class="row-odd"><td>row_bcast:15</td>
+<td>Broadcast 15th thread of each row to next row.</td>
+</tr>
+<tr class="row-even"><td>row_bcast:31</td>
+<td>Broadcast thread 31 to rows 2 and 3.</td>
+</tr>
+<tr class="row-odd"><td>wave_shl:1</td>
+<td>Wavefront left shift by 1 thread.</td>
+</tr>
+<tr class="row-even"><td>wave_rol:1</td>
+<td>Wavefront left rotate by 1 thread.</td>
+</tr>
+<tr class="row-odd"><td>wave_shr:1</td>
+<td>Wavefront right shift by 1 thread.</td>
+</tr>
+<tr class="row-even"><td>wave_ror:1</td>
+<td>Wavefront right rotate by 1 thread.</td>
+</tr>
+<tr class="row-odd"><td>row_shl:{1..15}</td>
+<td>Row shift left by 1-15 threads.</td>
+</tr>
+<tr class="row-even"><td>row_shr:{1..15}</td>
+<td>Row shift right by 1-15 threads.</td>
+</tr>
+<tr class="row-odd"><td>row_ror:{1..15}</td>
+<td>Row rotate right by 1-15 threads.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Note: Numeric parameters may be specified as either
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a> or
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expressions</span></a>.</p>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">quad_perm</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span> <span class="mi">1</span><span class="p">,</span> <span class="mi">2</span><span class="p">,</span> <span class="mi">3</span><span class="p">]</span>
+<span class="n">row_shl</span><span class="p">:</span><span class="mi">3</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="dpp16-ctrl">
+<span id="amdgpu-synid-dpp16-ctrl"></span><h4><a class="toc-backref" href="#id95">dpp16_ctrl</a><a class="headerlink" href="#dpp16-ctrl" title="Permalink to this headline">¶</a></h4>
+<p>Specifies how data are shared between threads. This is a mandatory modifier.
+There is no default value.</p>
+<p>GFX10 only. Use <a class="reference internal" href="#amdgpu-synid-dpp-ctrl"><span class="std std-ref">dpp_ctrl</span></a> for GFX8 and GFX9.</p>
+<p>Note. The lanes of a wavefront are organized in four <em>rows</em> and four <em>banks</em>.
+(There are only two rows in <em>wave32</em> mode.)</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="43%" />
+<col width="57%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>quad_perm:[{0..3},{0..3},{0..3},{0..3}]</td>
+<td>Full permute of 4 threads.</td>
+</tr>
+<tr class="row-odd"><td>row_mirror</td>
+<td>Mirror threads within row.</td>
+</tr>
+<tr class="row-even"><td>row_half_mirror</td>
+<td>Mirror threads within 1/2 row (8 threads).</td>
+</tr>
+<tr class="row-odd"><td>row_share:{0..15}</td>
+<td>Share the value from the specified lane with other
+lanes in the row.</td>
+</tr>
+<tr class="row-even"><td>row_xmask:{0..15}</td>
+<td>Fetch from XOR(current lane id, specified lane id).</td>
+</tr>
+<tr class="row-odd"><td>row_shl:{1..15}</td>
+<td>Row shift left by 1-15 threads.</td>
+</tr>
+<tr class="row-even"><td>row_shr:{1..15}</td>
+<td>Row shift right by 1-15 threads.</td>
+</tr>
+<tr class="row-odd"><td>row_ror:{1..15}</td>
+<td>Row rotate right by 1-15 threads.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Note: Numeric parameters may be specified as either
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a> or
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expressions</span></a>.</p>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">quad_perm</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span> <span class="mi">1</span><span class="p">,</span> <span class="mi">2</span><span class="p">,</span> <span class="mi">3</span><span class="p">]</span>
+<span class="n">row_shl</span><span class="p">:</span><span class="mi">3</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="row-mask">
+<span id="amdgpu-synid-row-mask"></span><h4><a class="toc-backref" href="#id96">row_mask</a><a class="headerlink" href="#row-mask" title="Permalink to this headline">¶</a></h4>
+<p>Controls which rows are enabled for data sharing. By default, all rows are enabled.</p>
+<p>Note. The lanes of a wavefront are organized in four <em>rows</em> and four <em>banks</em>.
+(There are only two rows in <em>wave32</em> mode.)</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="43%" />
+<col width="57%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>row_mask:{0..15}</td>
+<td><p class="first">Specifies a <em>row mask</em> as a positive
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</p>
+<p>Each of 4 bits in the mask controls one
+row (0 - disabled, 1 - enabled).</p>
+<p class="last">In <em>wave32</em> mode the values should be limited to
+{0..7}.</p>
+</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">row_mask</span><span class="p">:</span><span class="mh">0xf</span>
+<span class="n">row_mask</span><span class="p">:</span><span class="mb">0b1010</span>
+<span class="n">row_mask</span><span class="p">:</span><span class="mb">0b1111</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="bank-mask">
+<span id="amdgpu-synid-bank-mask"></span><h4><a class="toc-backref" href="#id97">bank_mask</a><a class="headerlink" href="#bank-mask" title="Permalink to this headline">¶</a></h4>
+<p>Controls which banks are enabled for data sharing. By default, all banks are enabled.</p>
+<p>Note. The lanes of a wavefront are organized in four <em>rows</em> and four <em>banks</em>.
+(There are only two rows in <em>wave32</em> mode.)</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="42%" />
+<col width="58%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>bank_mask:{0..15}</td>
+<td><p class="first">Specifies a <em>bank mask</em> as a positive
+<a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</p>
+<p class="last">Each of 4 bits in the mask controls one
+bank (0 - disabled, 1 - enabled).</p>
+</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">bank_mask</span><span class="p">:</span><span class="mh">0x3</span>
+<span class="n">bank_mask</span><span class="p">:</span><span class="mb">0b0011</span>
+<span class="n">bank_mask</span><span class="p">:</span><span class="mb">0b1111</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="bound-ctrl">
+<span id="amdgpu-synid-bound-ctrl"></span><h4><a class="toc-backref" href="#id98">bound_ctrl</a><a class="headerlink" href="#bound-ctrl" title="Permalink to this headline">¶</a></h4>
+<p>Controls data sharing when accessing an invalid lane. By default, data sharing with
+invalid lanes is disabled.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>bound_ctrl:0</td>
+<td><p class="first">Enables data sharing with invalid lanes.</p>
+<p class="last">Accessing data from an invalid lane will
+return zero.</p>
+</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="amdgpu-synid-fi16">
+<span id="id20"></span><h4><a class="toc-backref" href="#id99">fi</a><a class="headerlink" href="#amdgpu-synid-fi16" title="Permalink to this headline">¶</a></h4>
+<p>Controls interaction with <em>inactive</em> lanes for <em>dpp16</em> instructions. The default value is zero.</p>
+<p>Note. <em>Inactive</em> lanes are those whose <a class="reference internal" href="AMDGPUOperandSyntax.html#amdgpu-synid-exec"><span class="std std-ref">exec</span></a> mask bit is zero.</p>
+<p>GFX10 only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="44%" />
+<col width="56%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>fi:0</td>
+<td>Interaction with inactive lanes is controlled by
+<a class="reference internal" href="#amdgpu-synid-bound-ctrl"><span class="std std-ref">bound_ctrl</span></a>.</td>
+</tr>
+<tr class="row-odd"><td>fi:1</td>
+<td>Fetch pre-exist values from inactive lanes.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="sdwa-modifiers">
+<h3><a class="toc-backref" href="#id100">SDWA Modifiers</a><a class="headerlink" href="#sdwa-modifiers" title="Permalink to this headline">¶</a></h3>
+<p>GFX8, GFX9 and GFX10 only.</p>
+<div class="section" id="clamp">
+<h4><a class="toc-backref" href="#id101">clamp</a><a class="headerlink" href="#clamp" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-clamp"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="omod">
+<h4><a class="toc-backref" href="#id102">omod</a><a class="headerlink" href="#omod" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-omod"><span class="std std-ref">here</span></a>.</p>
+<p>GFX9 and GFX10 only.</p>
+</div>
+<div class="section" id="dst-sel">
+<span id="amdgpu-synid-dst-sel"></span><h4><a class="toc-backref" href="#id103">dst_sel</a><a class="headerlink" href="#dst-sel" title="Permalink to this headline">¶</a></h4>
+<p>Selects which bits in the destination are affected. By default, all bits are affected.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>dst_sel:DWORD</td>
+<td>Use bits 31:0.</td>
+</tr>
+<tr class="row-odd"><td>dst_sel:BYTE_0</td>
+<td>Use bits 7:0.</td>
+</tr>
+<tr class="row-even"><td>dst_sel:BYTE_1</td>
+<td>Use bits 15:8.</td>
+</tr>
+<tr class="row-odd"><td>dst_sel:BYTE_2</td>
+<td>Use bits 23:16.</td>
+</tr>
+<tr class="row-even"><td>dst_sel:BYTE_3</td>
+<td>Use bits 31:24.</td>
+</tr>
+<tr class="row-odd"><td>dst_sel:WORD_0</td>
+<td>Use bits 15:0.</td>
+</tr>
+<tr class="row-even"><td>dst_sel:WORD_1</td>
+<td>Use bits 31:16.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="dst-unused">
+<span id="amdgpu-synid-dst-unused"></span><h4><a class="toc-backref" href="#id104">dst_unused</a><a class="headerlink" href="#dst-unused" title="Permalink to this headline">¶</a></h4>
+<p>Controls what to do with the bits in the destination which are not selected
+by <a class="reference internal" href="#amdgpu-synid-dst-sel"><span class="std std-ref">dst_sel</span></a>.
+By default, unused bits are preserved.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>dst_unused:UNUSED_PAD</td>
+<td>Pad with zeros.</td>
+</tr>
+<tr class="row-odd"><td>dst_unused:UNUSED_SEXT</td>
+<td>Sign-extend upper bits, zero lower bits.</td>
+</tr>
+<tr class="row-even"><td>dst_unused:UNUSED_PRESERVE</td>
+<td>Preserve bits.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="src0-sel">
+<span id="amdgpu-synid-src0-sel"></span><h4><a class="toc-backref" href="#id105">src0_sel</a><a class="headerlink" href="#src0-sel" title="Permalink to this headline">¶</a></h4>
+<p>Controls which bits in the src0 are used. By default, all bits are used.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>src0_sel:DWORD</td>
+<td>Use bits 31:0.</td>
+</tr>
+<tr class="row-odd"><td>src0_sel:BYTE_0</td>
+<td>Use bits 7:0.</td>
+</tr>
+<tr class="row-even"><td>src0_sel:BYTE_1</td>
+<td>Use bits 15:8.</td>
+</tr>
+<tr class="row-odd"><td>src0_sel:BYTE_2</td>
+<td>Use bits 23:16.</td>
+</tr>
+<tr class="row-even"><td>src0_sel:BYTE_3</td>
+<td>Use bits 31:24.</td>
+</tr>
+<tr class="row-odd"><td>src0_sel:WORD_0</td>
+<td>Use bits 15:0.</td>
+</tr>
+<tr class="row-even"><td>src0_sel:WORD_1</td>
+<td>Use bits 31:16.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="src1-sel">
+<span id="amdgpu-synid-src1-sel"></span><h4><a class="toc-backref" href="#id106">src1_sel</a><a class="headerlink" href="#src1-sel" title="Permalink to this headline">¶</a></h4>
+<p>Controls which bits in the src1 are used. By default, all bits are used.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>src1_sel:DWORD</td>
+<td>Use bits 31:0.</td>
+</tr>
+<tr class="row-odd"><td>src1_sel:BYTE_0</td>
+<td>Use bits 7:0.</td>
+</tr>
+<tr class="row-even"><td>src1_sel:BYTE_1</td>
+<td>Use bits 15:8.</td>
+</tr>
+<tr class="row-odd"><td>src1_sel:BYTE_2</td>
+<td>Use bits 23:16.</td>
+</tr>
+<tr class="row-even"><td>src1_sel:BYTE_3</td>
+<td>Use bits 31:24.</td>
+</tr>
+<tr class="row-odd"><td>src1_sel:WORD_0</td>
+<td>Use bits 15:0.</td>
+</tr>
+<tr class="row-even"><td>src1_sel:WORD_1</td>
+<td>Use bits 31:16.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="sdwa-operand-modifiers">
+<span id="amdgpu-synid-sdwa-operand-modifiers"></span><h3><a class="toc-backref" href="#id107">SDWA Operand Modifiers</a><a class="headerlink" href="#sdwa-operand-modifiers" title="Permalink to this headline">¶</a></h3>
+<p>Operand modifiers are not used separately. They are applied to source operands.</p>
+<p>GFX8, GFX9 and GFX10 only.</p>
+<div class="section" id="abs">
+<h4><a class="toc-backref" href="#id108">abs</a><a class="headerlink" href="#abs" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-abs"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="neg">
+<h4><a class="toc-backref" href="#id109">neg</a><a class="headerlink" href="#neg" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-neg"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="sext">
+<span id="amdgpu-synid-sext"></span><h4><a class="toc-backref" href="#id110">sext</a><a class="headerlink" href="#sext" title="Permalink to this headline">¶</a></h4>
+<p>Sign-extends value of a (sub-dword) operand to fill all 32 bits.
+Has no effect for 32-bit operands.</p>
+<p>Valid for integer operands only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>sext(<operand>)</td>
+<td>Sign-extend operand value.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">sext</span><span class="p">(</span><span class="n">v4</span><span class="p">)</span>
+<span class="n">sext</span><span class="p">(</span><span class="n">v255</span><span class="p">)</span>
+</pre></div>
+</div>
+</div>
+</div>
+<div class="section" id="vop3-modifiers">
+<h3><a class="toc-backref" href="#id111">VOP3 Modifiers</a><a class="headerlink" href="#vop3-modifiers" title="Permalink to this headline">¶</a></h3>
+<div class="section" id="op-sel">
+<span id="amdgpu-synid-vop3-op-sel"></span><h4><a class="toc-backref" href="#id112">op_sel</a><a class="headerlink" href="#op-sel" title="Permalink to this headline">¶</a></h4>
+<p>Selects the low [15:0] or high [31:16] operand bits for source and destination operands.
+By default, low bits are used for all operands.</p>
+<p>The number of values specified with the op_sel modifier must match the number of instruction
+operands (both source and destination). First value controls src0, second value controls src1
+and so on, except that the last value controls destination.
+The value 0 selects the low bits, while 1 selects the high bits.</p>
+<p>Note. op_sel modifier affects 16-bit operands only. For 32-bit operands the value specified
+by op_sel must be 0.</p>
+<p>GFX9 and GFX10 only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="40%" />
+<col width="60%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>op_sel:[{0..1},{0..1}]</td>
+<td>Select operand bits for instructions with 1 source operand.</td>
+</tr>
+<tr class="row-odd"><td>op_sel:[{0..1},{0..1},{0..1}]</td>
+<td>Select operand bits for instructions with 2 source operands.</td>
+</tr>
+<tr class="row-even"><td>op_sel:[{0..1},{0..1},{0..1},{0..1}]</td>
+<td>Select operand bits for instructions with 3 source operands.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">op_sel</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span><span class="mi">0</span><span class="p">]</span>
+<span class="n">op_sel</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span><span class="mi">1</span><span class="p">]</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="amdgpu-synid-clamp">
+<span id="id21"></span><h4><a class="toc-backref" href="#id113">clamp</a><a class="headerlink" href="#amdgpu-synid-clamp" title="Permalink to this headline">¶</a></h4>
+<p>Clamp meaning depends on instruction.</p>
+<p>For <em>v_cmp</em> instructions, clamp modifier indicates that the compare signals
+if a floating point exception occurs. By default, signaling is disabled.
+Not supported by GFX7.</p>
+<p>For integer operations, clamp modifier indicates that the result must be clamped
+to the largest and smallest representable value. By default, there is no clamping.
+Integer clamping is not supported by GFX7.</p>
+<p>For floating point operations, clamp modifier indicates that the result must be clamped
+to the range [0.0, 1.0]. By default, there is no clamping.</p>
+<p>Note. Clamp modifier is applied after <a class="reference internal" href="#amdgpu-synid-omod"><span class="std std-ref">output modifiers</span></a> (if any).</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>clamp</td>
+<td>Enables clamping (or signaling).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="amdgpu-synid-omod">
+<span id="id22"></span><h4><a class="toc-backref" href="#id114">omod</a><a class="headerlink" href="#amdgpu-synid-omod" title="Permalink to this headline">¶</a></h4>
+<p>Specifies if an output modifier must be applied to the result.
+By default, no output modifiers are applied.</p>
+<p>Note. Output modifiers are applied before <a class="reference internal" href="#amdgpu-synid-clamp"><span class="std std-ref">clamping</span></a> (if any).</p>
+<p>Output modifiers are valid for f32 and f64 floating point results only.
+They must not be used with f16.</p>
+<p>Note. <em>v_cvt_f16_f32</em> is an exception. This instruction produces f16 result
+but accepts output modifiers.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>mul:2</td>
+<td>Multiply the result by 2.</td>
+</tr>
+<tr class="row-odd"><td>mul:4</td>
+<td>Multiply the result by 4.</td>
+</tr>
+<tr class="row-even"><td>div:2</td>
+<td>Multiply the result by 0.5.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="vop3-operand-modifiers">
+<span id="amdgpu-synid-vop3-operand-modifiers"></span><h3><a class="toc-backref" href="#id115">VOP3 Operand Modifiers</a><a class="headerlink" href="#vop3-operand-modifiers" title="Permalink to this headline">¶</a></h3>
+<p>Operand modifiers are not used separately. They are applied to source operands.</p>
+<div class="section" id="amdgpu-synid-abs">
+<span id="id23"></span><h4><a class="toc-backref" href="#id116">abs</a><a class="headerlink" href="#amdgpu-synid-abs" title="Permalink to this headline">¶</a></h4>
+<p>Computes absolute value of its operand. Applied before <a class="reference internal" href="#amdgpu-synid-neg"><span class="std std-ref">neg</span></a> (if any).
+Valid for floating point operands only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>abs(<operand>)</td>
+<td>Get absolute value of operand.</td>
+</tr>
+<tr class="row-odd"><td>|<operand>|</td>
+<td>The same as above.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<pre class="literal-block">
+abs(v36)
+|v36|
+</pre>
+</div>
+<div class="section" id="amdgpu-synid-neg">
+<span id="id24"></span><h4><a class="toc-backref" href="#id117">neg</a><a class="headerlink" href="#amdgpu-synid-neg" title="Permalink to this headline">¶</a></h4>
+<p>Computes negative value of its operand. Applied after <a class="reference internal" href="#amdgpu-synid-abs"><span class="std std-ref">abs</span></a> (if any).
+Valid for floating point operands only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>neg(<operand>)</td>
+<td>Get negative value of operand.</td>
+</tr>
+<tr class="row-odd"><td>-<operand></td>
+<td>The same as above.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">neg</span><span class="p">(</span><span class="n">v</span><span class="p">[</span><span class="mi">0</span><span class="p">])</span>
+<span class="o">-</span><span class="n">v4</span>
+</pre></div>
+</div>
+</div>
+</div>
+<div class="section" id="vop3p-modifiers">
+<h3><a class="toc-backref" href="#id118">VOP3P Modifiers</a><a class="headerlink" href="#vop3p-modifiers" title="Permalink to this headline">¶</a></h3>
+<p>This section describes modifiers of <em>regular</em> VOP3P instructions.</p>
+<p><em>v_mad_mix_f32</em>, <em>v_mad_mixhi_f16</em> and <em>v_mad_mixlo_f16</em>
+instructions use these modifiers <a class="reference internal" href="#amdgpu-synid-mad-mix"><span class="std std-ref">in a special manner</span></a>.</p>
+<p>GFX9 and GFX10 only.</p>
+<div class="section" id="amdgpu-synid-op-sel">
+<span id="id25"></span><h4><a class="toc-backref" href="#id119">op_sel</a><a class="headerlink" href="#amdgpu-synid-op-sel" title="Permalink to this headline">¶</a></h4>
+<p>Selects the low [15:0] or high [31:16] operand bits as input to the operation
+which results in the lower-half of the destination.
+By default, low bits are used for all operands.</p>
+<p>The number of values specified by the <em>op_sel</em> modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.</p>
+<p>The value 0 selects the low bits, while 1 selects the high bits.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="35%" />
+<col width="65%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>op_sel:[{0..1}]</td>
+<td>Select operand bits for instructions with 1 source operand.</td>
+</tr>
+<tr class="row-odd"><td>op_sel:[{0..1},{0..1}]</td>
+<td>Select operand bits for instructions with 2 source operands.</td>
+</tr>
+<tr class="row-even"><td>op_sel:[{0..1},{0..1},{0..1}]</td>
+<td>Select operand bits for instructions with 3 source operands.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">op_sel</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span><span class="mi">0</span><span class="p">]</span>
+<span class="n">op_sel</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span><span class="mi">1</span><span class="p">,</span><span class="mi">0</span><span class="p">]</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="op-sel-hi">
+<span id="amdgpu-synid-op-sel-hi"></span><h4><a class="toc-backref" href="#id120">op_sel_hi</a><a class="headerlink" href="#op-sel-hi" title="Permalink to this headline">¶</a></h4>
+<p>Selects the low [15:0] or high [31:16] operand bits as input to the operation
+which results in the upper-half of the destination.
+By default, high bits are used for all operands.</p>
+<p>The number of values specified by the <em>op_sel_hi</em> modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.</p>
+<p>The value 0 selects the low bits, while 1 selects the high bits.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="36%" />
+<col width="64%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>op_sel_hi:[{0..1}]</td>
+<td>Select operand bits for instructions with 1 source operand.</td>
+</tr>
+<tr class="row-odd"><td>op_sel_hi:[{0..1},{0..1}]</td>
+<td>Select operand bits for instructions with 2 source operands.</td>
+</tr>
+<tr class="row-even"><td>op_sel_hi:[{0..1},{0..1},{0..1}]</td>
+<td>Select operand bits for instructions with 3 source operands.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">op_sel_hi</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span><span class="mi">0</span><span class="p">]</span>
+<span class="n">op_sel_hi</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span><span class="mi">0</span><span class="p">,</span><span class="mi">1</span><span class="p">]</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="neg-lo">
+<span id="amdgpu-synid-neg-lo"></span><h4><a class="toc-backref" href="#id121">neg_lo</a><a class="headerlink" href="#neg-lo" title="Permalink to this headline">¶</a></h4>
+<p>Specifies whether to change sign of operand values selected by
+<a class="reference internal" href="#amdgpu-synid-op-sel"><span class="std std-ref">op_sel</span></a>. These values are then used
+as input to the operation which results in the upper-half of the destination.</p>
+<p>The number of values specified by this modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.</p>
+<p>The value 0 indicates that the corresponding operand value is used unmodified,
+the value 1 indicates that negative value of the operand must be used.</p>
+<p>By default, operand values are used unmodified.</p>
+<p>This modifier is valid for floating point operands only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="33%" />
+<col width="67%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>neg_lo:[{0..1}]</td>
+<td>Select affected operands for instructions with 1 source operand.</td>
+</tr>
+<tr class="row-odd"><td>neg_lo:[{0..1},{0..1}]</td>
+<td>Select affected operands for instructions with 2 source operands.</td>
+</tr>
+<tr class="row-even"><td>neg_lo:[{0..1},{0..1},{0..1}]</td>
+<td>Select affected operands for instructions with 3 source operands.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">neg_lo</span><span class="p">:[</span><span class="mi">0</span><span class="p">]</span>
+<span class="n">neg_lo</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span><span class="mi">1</span><span class="p">]</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="neg-hi">
+<span id="amdgpu-synid-neg-hi"></span><h4><a class="toc-backref" href="#id122">neg_hi</a><a class="headerlink" href="#neg-hi" title="Permalink to this headline">¶</a></h4>
+<p>Specifies whether to change sign of operand values selected by
+<a class="reference internal" href="#amdgpu-synid-op-sel-hi"><span class="std std-ref">op_sel_hi</span></a>. These values are then used
+as input to the operation which results in the upper-half of the destination.</p>
+<p>The number of values specified by this modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.</p>
+<p>The value 0 indicates that the corresponding operand value is used unmodified,
+the value 1 indicates that negative value of the operand must be used.</p>
+<p>By default, operand values are used unmodified.</p>
+<p>This modifier is valid for floating point operands only.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="32%" />
+<col width="68%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>neg_hi:[{0..1}]</td>
+<td>Select affected operands for instructions with 1 source operand.</td>
+</tr>
+<tr class="row-odd"><td>neg_hi:[{0..1},{0..1}]</td>
+<td>Select affected operands for instructions with 2 source operands.</td>
+</tr>
+<tr class="row-even"><td>neg_hi:[{0..1},{0..1},{0..1}]</td>
+<td>Select affected operands for instructions with 3 source operands.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">neg_hi</span><span class="p">:[</span><span class="mi">1</span><span class="p">,</span><span class="mi">0</span><span class="p">]</span>
+<span class="n">neg_hi</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span><span class="mi">1</span><span class="p">,</span><span class="mi">1</span><span class="p">]</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="id26">
+<h4><a class="toc-backref" href="#id123">clamp</a><a class="headerlink" href="#id26" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-clamp"><span class="std std-ref">here</span></a>.</p>
+</div>
+</div>
+<div class="section" id="vop3p-v-mad-mix-modifiers">
+<span id="amdgpu-synid-mad-mix"></span><h3><a class="toc-backref" href="#id124">VOP3P V_MAD_MIX Modifiers</a><a class="headerlink" href="#vop3p-v-mad-mix-modifiers" title="Permalink to this headline">¶</a></h3>
+<p><em>v_mad_mix_f32</em>, <em>v_mad_mixhi_f16</em> and <em>v_mad_mixlo_f16</em> instructions
+use <em>op_sel</em> and <em>op_sel_hi</em> modifiers
+in a manner different from <em>regular</em> VOP3P instructions.</p>
+<p>See a description below.</p>
+<p>GFX9 and GFX10 only.</p>
+<div class="section" id="m-op-sel">
+<span id="amdgpu-synid-mad-mix-op-sel"></span><h4><a class="toc-backref" href="#id125">m_op_sel</a><a class="headerlink" href="#m-op-sel" title="Permalink to this headline">¶</a></h4>
+<p>This operand has meaning only for 16-bit source operands as indicated by
+<a class="reference internal" href="#amdgpu-synid-mad-mix-op-sel-hi"><span class="std std-ref">m_op_sel_hi</span></a>.
+It specifies to select either the low [15:0] or high [31:16] operand bits
+as input to the operation.</p>
+<p>The number of values specified by the <em>op_sel</em> modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.</p>
+<p>The value 0 indicates the low bits, the value 1 indicates the high 16 bits.</p>
+<p>By default, low bits are used for all operands.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="39%" />
+<col width="61%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>op_sel:[{0..1},{0..1},{0..1}]</td>
+<td>Select location of each 16-bit source operand.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">op_sel</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span><span class="mi">1</span><span class="p">]</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="m-op-sel-hi">
+<span id="amdgpu-synid-mad-mix-op-sel-hi"></span><h4><a class="toc-backref" href="#id126">m_op_sel_hi</a><a class="headerlink" href="#m-op-sel-hi" title="Permalink to this headline">¶</a></h4>
+<p>Selects the size of source operands: either 32 bits or 16 bits.
+By default, 32 bits are used for all source operands.</p>
+<p>The number of values specified by the <em>op_sel_hi</em> modifier must match the number of source
+operands. First value controls src0, second value controls src1 and so on.</p>
+<p>The value 0 indicates 32 bits, the value 1 indicates 16 bits.</p>
+<p>The location of 16 bits in the operand may be specified by
+<a class="reference internal" href="#amdgpu-synid-mad-mix-op-sel"><span class="std std-ref">m_op_sel</span></a>.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="53%" />
+<col width="47%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>op_sel_hi:[{0..1},{0..1},{0..1}]</td>
+<td>Select size of each source operand.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">op_sel_hi</span><span class="p">:[</span><span class="mi">1</span><span class="p">,</span><span class="mi">1</span><span class="p">,</span><span class="mi">1</span><span class="p">]</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="id27">
+<h4><a class="toc-backref" href="#id127">abs</a><a class="headerlink" href="#id27" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-abs"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="id28">
+<h4><a class="toc-backref" href="#id128">neg</a><a class="headerlink" href="#id28" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-neg"><span class="std std-ref">here</span></a>.</p>
+</div>
+<div class="section" id="id29">
+<h4><a class="toc-backref" href="#id129">clamp</a><a class="headerlink" href="#id29" title="Permalink to this headline">¶</a></h4>
+<p>See a description <a class="reference internal" href="#amdgpu-synid-clamp"><span class="std std-ref">here</span></a>.</p>
+</div>
+</div>
+</div>
+</div>
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+
+ <div class="section" id="syntax-of-amdgpu-instruction-operands">
+<h1>Syntax of AMDGPU Instruction Operands<a class="headerlink" href="#syntax-of-amdgpu-instruction-operands" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#conventions" id="id2">Conventions</a></li>
+<li><a class="reference internal" href="#operands" id="id3">Operands</a><ul>
+<li><a class="reference internal" href="#v" id="id4">v</a></li>
+<li><a class="reference internal" href="#s" id="id5">s</a></li>
+<li><a class="reference internal" href="#trap" id="id6">trap</a></li>
+<li><a class="reference internal" href="#ttmp" id="id7">ttmp</a></li>
+<li><a class="reference internal" href="#tba" id="id8">tba</a></li>
+<li><a class="reference internal" href="#tma" id="id9">tma</a></li>
+<li><a class="reference internal" href="#flat-scratch" id="id10">flat_scratch</a></li>
+<li><a class="reference internal" href="#xnack" id="id11">xnack</a></li>
+<li><a class="reference internal" href="#vcc" id="id12">vcc</a></li>
+<li><a class="reference internal" href="#m0" id="id13">m0</a></li>
+<li><a class="reference internal" href="#exec" id="id14">exec</a></li>
+<li><a class="reference internal" href="#vccz" id="id15">vccz</a></li>
+<li><a class="reference internal" href="#execz" id="id16">execz</a></li>
+<li><a class="reference internal" href="#scc" id="id17">scc</a></li>
+<li><a class="reference internal" href="#lds-direct" id="id18">lds_direct</a></li>
+<li><a class="reference internal" href="#null" id="id19">null</a></li>
+<li><a class="reference internal" href="#constant" id="id20">constant</a><ul>
+<li><a class="reference internal" href="#iconst" id="id21">iconst</a></li>
+<li><a class="reference internal" href="#fconst" id="id22">fconst</a></li>
+<li><a class="reference internal" href="#ival" id="id23">ival</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#literal" id="id24">literal</a></li>
+<li><a class="reference internal" href="#uimm8" id="id25">uimm8</a></li>
+<li><a class="reference internal" href="#uimm32" id="id26">uimm32</a></li>
+<li><a class="reference internal" href="#uimm20" id="id27">uimm20</a></li>
+<li><a class="reference internal" href="#uimm21" id="id28">uimm21</a></li>
+<li><a class="reference internal" href="#simm21" id="id29">simm21</a></li>
+<li><a class="reference internal" href="#off" id="id30">off</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#numbers" id="id31">Numbers</a><ul>
+<li><a class="reference internal" href="#integer-numbers" id="id32">Integer Numbers</a></li>
+<li><a class="reference internal" href="#floating-point-numbers" id="id33">Floating-Point Numbers</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#expressions" id="id34">Expressions</a><ul>
+<li><a class="reference internal" href="#absolute-expressions" id="id35">Absolute Expressions</a></li>
+<li><a class="reference internal" href="#relocatable-expressions" id="id36">Relocatable Expressions</a></li>
+<li><a class="reference internal" href="#expression-data-type" id="id37">Expression Data Type</a></li>
+<li><a class="reference internal" href="#syntax" id="id38">Syntax</a></li>
+<li><a class="reference internal" href="#binary-operators" id="id39">Binary Operators</a></li>
+<li><a class="reference internal" href="#unary-operators" id="id40">Unary Operators</a></li>
+<li><a class="reference internal" href="#symbols" id="id41">Symbols</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#conversions" id="id42">Conversions</a><ul>
+<li><a class="reference internal" href="#inline-constants" id="id43">Inline Constants</a><ul>
+<li><a class="reference internal" href="#integer-inline-constants" id="id44">Integer Inline Constants</a></li>
+<li><a class="reference internal" href="#floating-point-inline-constants" id="id45">Floating-Point Inline Constants</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#literals" id="id46">Literals</a><ul>
+<li><a class="reference internal" href="#integer-literals" id="id47">Integer Literals</a></li>
+<li><a class="reference internal" href="#floating-point-literals" id="id48">Floating-Point Literals</a></li>
+<li><a class="reference internal" href="#amdgpu-synid-exp-conv" id="id49">Expressions</a></li>
+</ul>
+</li>
+</ul>
+</li>
+</ul>
+</div>
+<div class="section" id="conventions">
+<h2><a class="toc-backref" href="#id2">Conventions</a><a class="headerlink" href="#conventions" title="Permalink to this headline">¶</a></h2>
+<p>The following notation is used throughout this document:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="20%" />
+<col width="80%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Notation</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>{0..N}</td>
+<td>Any integer value in the range from 0 to N (inclusive).</td>
+</tr>
+<tr class="row-odd"><td><x></td>
+<td>Syntax and meaning of <em>x</em> is explained elsewhere.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="operands">
+<span id="amdgpu-syn-operands"></span><h2><a class="toc-backref" href="#id3">Operands</a><a class="headerlink" href="#operands" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="v">
+<span id="amdgpu-synid-v"></span><h3><a class="toc-backref" href="#id4">v</a><a class="headerlink" href="#v" title="Permalink to this headline">¶</a></h3>
+<p>Vector registers. There are 256 32-bit vector registers.</p>
+<p>A sequence of <em>vector</em> registers may be used to operate with more than 32 bits of data.</p>
+<p>Assembler currently supports sequences of 1, 2, 3, 4, 8 and 16 <em>vector</em> registers.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="43%" />
+<col width="57%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><strong>v</strong><N></td>
+<td><p class="first">A single 32-bit <em>vector</em> register.</p>
+<p class="last"><em>N</em> must be a decimal integer number.</p>
+</td>
+</tr>
+<tr class="row-odd"><td><strong>v[</strong><N><strong>]</strong></td>
+<td><p class="first">A single 32-bit <em>vector</em> register.</p>
+<p class="last"><em>N</em> may be specified as an
+<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>
+or an <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expression</span></a>.</p>
+</td>
+</tr>
+<tr class="row-even"><td><strong>v[</strong><N>:<K><strong>]</strong></td>
+<td><p class="first">A sequence of (<em>K-N+1</em>) <em>vector</em> registers.</p>
+<p class="last"><em>N</em> and <em>K</em> may be specified as
+<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>
+or <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expressions</span></a>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td><strong>[v</strong><N>, <strong>v</strong><N+1>, ⦠<strong>v</strong><K><strong>]</strong></td>
+<td><p class="first">A sequence of (<em>K-N+1</em>) <em>vector</em> registers.</p>
+<p class="last">Register indices must be specified as decimal integer numbers.</p>
+</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Note. <em>N</em> and <em>K</em> must satisfy the following conditions:</p>
+<ul class="simple">
+<li><em>N</em> <= <em>K</em>.</li>
+<li>0 <= <em>N</em> <= 255.</li>
+<li>0 <= <em>K</em> <= 255.</li>
+<li><em>K-N+1</em> must be equal to 1, 2, 3, 4, 8 or 16.</li>
+</ul>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">v255</span>
+<span class="n">v</span><span class="p">[</span><span class="mi">0</span><span class="p">]</span>
+<span class="n">v</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">]</span>
+<span class="n">v</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">1</span><span class="p">]</span>
+<span class="n">v</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">3</span><span class="p">]</span>
+<span class="n">v</span><span class="p">[</span><span class="mi">2</span><span class="o">*</span><span class="mi">2</span><span class="p">]</span>
+<span class="n">v</span><span class="p">[</span><span class="mi">1</span><span class="o">-</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="o">-</span><span class="mi">1</span><span class="p">]</span>
+<span class="p">[</span><span class="n">v252</span><span class="p">]</span>
+<span class="p">[</span><span class="n">v252</span><span class="p">,</span><span class="n">v253</span><span class="p">,</span><span class="n">v254</span><span class="p">,</span><span class="n">v255</span><span class="p">]</span>
+</pre></div>
+</div>
+<p id="amdgpu-synid-nsa"><em>Image</em> instructions may use special <em>NSA</em> (Non-Sequential Address) syntax for <em>image addresses</em>:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="43%" />
+<col width="57%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><strong>[v</strong><A>, <strong>v</strong><B>, ⦠<strong>v</strong><X><strong>]</strong></td>
+<td><p class="first">A sequence of <em>vector</em> registers. At least one register
+must be specified.</p>
+<p class="last">In contrast with standard syntax described above, registers in
+this sequence are not required to have consecutive indices.
+Moreover, the same register may appear in the list more than once.</p>
+</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Note. Reqister indices must be in the range 0..255. They must be specified as decimal integer numbers.</p>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="p">[</span><span class="n">v32</span><span class="p">,</span><span class="n">v1</span><span class="p">,</span><span class="n">v2</span><span class="p">]</span>
+<span class="p">[</span><span class="n">v4</span><span class="p">,</span><span class="n">v4</span><span class="p">,</span><span class="n">v4</span><span class="p">,</span><span class="n">v4</span><span class="p">]</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="s">
+<span id="amdgpu-synid-s"></span><h3><a class="toc-backref" href="#id5">s</a><a class="headerlink" href="#s" title="Permalink to this headline">¶</a></h3>
+<p>Scalar 32-bit registers. The number of available <em>scalar</em> registers depends on GPU:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="20%" />
+<col width="80%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">GPU</th>
+<th class="head">Number of <em>scalar</em> registers</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>GFX7</td>
+<td>104</td>
+</tr>
+<tr class="row-odd"><td>GFX8</td>
+<td>102</td>
+</tr>
+<tr class="row-even"><td>GFX9</td>
+<td>102</td>
+</tr>
+<tr class="row-odd"><td>GFX10</td>
+<td>106</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>A sequence of <em>scalar</em> registers may be used to operate with more than 32 bits of data.
+Assembler currently supports sequences of 1, 2, 4, 8 and 16 <em>scalar</em> registers.</p>
+<p>Pairs of <em>scalar</em> registers must be even-aligned (the first register must be even).
+Sequences of 4 and more <em>scalar</em> registers must be quad-aligned.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="45%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><strong>s</strong><N></td>
+<td><p class="first">A single 32-bit <em>scalar</em> register.</p>
+<p class="last"><em>N</em> must be a decimal integer number.</p>
+</td>
+</tr>
+<tr class="row-odd"><td><strong>s[</strong><N><strong>]</strong></td>
+<td><p class="first">A single 32-bit <em>scalar</em> register.</p>
+<p class="last"><em>N</em> may be specified as an
+<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>
+or an <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expression</span></a>.</p>
+</td>
+</tr>
+<tr class="row-even"><td><strong>s[</strong><N>:<K><strong>]</strong></td>
+<td><p class="first">A sequence of (<em>K-N+1</em>) <em>scalar</em> registers.</p>
+<p class="last"><em>N</em> and <em>K</em> may be specified as
+<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>
+or <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expressions</span></a>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td><strong>[s</strong><N>, <strong>s</strong><N+1>, ⦠<strong>s</strong><K><strong>]</strong></td>
+<td><p class="first">A sequence of (<em>K-N+1</em>) <em>scalar</em> registers.</p>
+<p class="last">Register indices must be specified as decimal integer numbers.</p>
+</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Note. <em>N</em> and <em>K</em> must satisfy the following conditions:</p>
+<ul class="simple">
+<li><em>N</em> must be properly aligned based on sequence size.</li>
+<li><em>N</em> <= <em>K</em>.</li>
+<li>0 <= <em>N</em> < <em>SMAX</em>, where <em>SMAX</em> is the number of available <em>scalar</em> registers.</li>
+<li>0 <= <em>K</em> < <em>SMAX</em>, where <em>SMAX</em> is the number of available <em>scalar</em> registers.</li>
+<li><em>K-N+1</em> must be equal to 1, 2, 4, 8 or 16.</li>
+</ul>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">s0</span>
+<span class="n">s</span><span class="p">[</span><span class="mi">0</span><span class="p">]</span>
+<span class="n">s</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">]</span>
+<span class="n">s</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">1</span><span class="p">]</span>
+<span class="n">s</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">3</span><span class="p">]</span>
+<span class="n">s</span><span class="p">[</span><span class="mi">2</span><span class="o">*</span><span class="mi">2</span><span class="p">]</span>
+<span class="n">s</span><span class="p">[</span><span class="mi">1</span><span class="o">-</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="o">-</span><span class="mi">1</span><span class="p">]</span>
+<span class="p">[</span><span class="n">s4</span><span class="p">]</span>
+<span class="p">[</span><span class="n">s4</span><span class="p">,</span><span class="n">s5</span><span class="p">,</span><span class="n">s6</span><span class="p">,</span><span class="n">s7</span><span class="p">]</span>
+</pre></div>
+</div>
+<p>Examples of <em>scalar</em> registers with an invalid alignment:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">s</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="p">]</span>
+<span class="n">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="trap">
+<span id="amdgpu-synid-trap"></span><h3><a class="toc-backref" href="#id6">trap</a><a class="headerlink" href="#trap" title="Permalink to this headline">¶</a></h3>
+<p>A set of trap handler registers:</p>
+<ul class="simple">
+<li><a class="reference internal" href="#amdgpu-synid-ttmp"><span class="std std-ref">ttmp</span></a></li>
+<li><a class="reference internal" href="#amdgpu-synid-tba"><span class="std std-ref">tba</span></a></li>
+<li><a class="reference internal" href="#amdgpu-synid-tma"><span class="std std-ref">tma</span></a></li>
+</ul>
+</div>
+<div class="section" id="ttmp">
+<span id="amdgpu-synid-ttmp"></span><h3><a class="toc-backref" href="#id7">ttmp</a><a class="headerlink" href="#ttmp" title="Permalink to this headline">¶</a></h3>
+<p>Trap handler temporary scalar registers, 32-bits wide.
+The number of available <em>ttmp</em> registers depends on GPU:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="21%" />
+<col width="79%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">GPU</th>
+<th class="head">Number of <em>ttmp</em> registers</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>GFX7</td>
+<td>12</td>
+</tr>
+<tr class="row-odd"><td>GFX8</td>
+<td>12</td>
+</tr>
+<tr class="row-even"><td>GFX9</td>
+<td>16</td>
+</tr>
+<tr class="row-odd"><td>GFX10</td>
+<td>16</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>A sequence of <em>ttmp</em> registers may be used to operate with more than 32 bits of data.
+Assembler currently supports sequences of 1, 2, 4, 8 and 16 <em>ttmp</em> registers.</p>
+<p>Pairs of <em>ttmp</em> registers must be even-aligned (the first register must be even).
+Sequences of 4 and more <em>ttmp</em> registers must be quad-aligned.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="47%" />
+<col width="53%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><strong>ttmp</strong><N></td>
+<td><p class="first">A single 32-bit <em>ttmp</em> register.</p>
+<p class="last"><em>N</em> must be a decimal integer number.</p>
+</td>
+</tr>
+<tr class="row-odd"><td><strong>ttmp[</strong><N><strong>]</strong></td>
+<td><p class="first">A single 32-bit <em>ttmp</em> register.</p>
+<p class="last"><em>N</em> may be specified as an
+<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>
+or an <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expression</span></a>.</p>
+</td>
+</tr>
+<tr class="row-even"><td><strong>ttmp[</strong><N>:<K><strong>]</strong></td>
+<td><p class="first">A sequence of (<em>K-N+1</em>) <em>ttmp</em> registers.</p>
+<p class="last"><em>N</em> and <em>K</em> may be specified as
+<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>
+or <a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">absolute expressions</span></a>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td><strong>[ttmp</strong><N>, <strong>ttmp</strong><N+1>, ⦠<strong>ttmp</strong><K><strong>]</strong></td>
+<td><p class="first">A sequence of (<em>K-N+1</em>) <em>ttmp</em> registers.</p>
+<p class="last">Register indices must be specified as decimal integer numbers.</p>
+</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Note. <em>N</em> and <em>K</em> must satisfy the following conditions:</p>
+<ul class="simple">
+<li><em>N</em> must be properly aligned based on sequence size.</li>
+<li><em>N</em> <= <em>K</em>.</li>
+<li>0 <= <em>N</em> < <em>TMAX</em>, where <em>TMAX</em> is the number of available <em>ttmp</em> registers.</li>
+<li>0 <= <em>K</em> < <em>TMAX</em>, where <em>TMAX</em> is the number of available <em>ttmp</em> registers.</li>
+<li><em>K-N+1</em> must be equal to 1, 2, 4, 8 or 16.</li>
+</ul>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">ttmp0</span>
+<span class="n">ttmp</span><span class="p">[</span><span class="mi">0</span><span class="p">]</span>
+<span class="n">ttmp</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">]</span>
+<span class="n">ttmp</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">1</span><span class="p">]</span>
+<span class="n">ttmp</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">3</span><span class="p">]</span>
+<span class="n">ttmp</span><span class="p">[</span><span class="mi">2</span><span class="o">*</span><span class="mi">2</span><span class="p">]</span>
+<span class="n">ttmp</span><span class="p">[</span><span class="mi">1</span><span class="o">-</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="o">-</span><span class="mi">1</span><span class="p">]</span>
+<span class="p">[</span><span class="n">ttmp4</span><span class="p">]</span>
+<span class="p">[</span><span class="n">ttmp4</span><span class="p">,</span><span class="n">ttmp5</span><span class="p">,</span><span class="n">ttmp6</span><span class="p">,</span><span class="n">ttmp7</span><span class="p">]</span>
+</pre></div>
+</div>
+<p>Examples of <em>ttmp</em> registers with an invalid alignment:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">ttmp</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="p">]</span>
+<span class="n">ttmp</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="tba">
+<span id="amdgpu-synid-tba"></span><h3><a class="toc-backref" href="#id8">tba</a><a class="headerlink" href="#tba" title="Permalink to this headline">¶</a></h3>
+<p>Trap base address, 64-bits wide. Holds the pointer to the current trap handler program.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="18%" />
+<col width="70%" />
+<col width="13%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+<th class="head">Availability</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>tba</td>
+<td>64-bit <em>trap base address</em> register.</td>
+<td>GFX7, GFX8</td>
+</tr>
+<tr class="row-odd"><td>[tba]</td>
+<td>64-bit <em>trap base address</em> register (an alternative syntax).</td>
+<td>GFX7, GFX8</td>
+</tr>
+<tr class="row-even"><td>[tba_lo,tba_hi]</td>
+<td>64-bit <em>trap base address</em> register (an alternative syntax).</td>
+<td>GFX7, GFX8</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>High and low 32 bits of <em>trap base address</em> may be accessed as separate registers:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="18%" />
+<col width="70%" />
+<col width="13%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+<th class="head">Availability</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>tba_lo</td>
+<td>Low 32 bits of <em>trap base address</em> register.</td>
+<td>GFX7, GFX8</td>
+</tr>
+<tr class="row-odd"><td>tba_hi</td>
+<td>High 32 bits of <em>trap base address</em> register.</td>
+<td>GFX7, GFX8</td>
+</tr>
+<tr class="row-even"><td>[tba_lo]</td>
+<td>Low 32 bits of <em>trap base address</em> register (an alternative syntax).</td>
+<td>GFX7, GFX8</td>
+</tr>
+<tr class="row-odd"><td>[tba_hi]</td>
+<td>High 32 bits of <em>trap base address</em> register (an alternative syntax).</td>
+<td>GFX7, GFX8</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Note that <em>tba</em>, <em>tba_lo</em> and <em>tba_hi</em> are not accessible as assembler registers in GFX9 and GFX10,
+but <em>tba</em> is readable/writable with the help of <em>s_get_reg</em> and <em>s_set_reg</em> instructions.</p>
+</div>
+<div class="section" id="tma">
+<span id="amdgpu-synid-tma"></span><h3><a class="toc-backref" href="#id9">tma</a><a class="headerlink" href="#tma" title="Permalink to this headline">¶</a></h3>
+<p>Trap memory address, 64-bits wide.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="16%" />
+<col width="67%" />
+<col width="17%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+<th class="head">Availability</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>tma</td>
+<td>64-bit <em>trap memory address</em> register.</td>
+<td>GFX7, GFX8</td>
+</tr>
+<tr class="row-odd"><td>[tma]</td>
+<td>64-bit <em>trap memory address</em> register (an alternative syntax).</td>
+<td>GFX7, GFX8</td>
+</tr>
+<tr class="row-even"><td>[tma_lo,tma_hi]</td>
+<td>64-bit <em>trap memory address</em> register (an alternative syntax).</td>
+<td>GFX7, GFX8</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>High and low 32 bits of <em>trap memory address</em> may be accessed as separate registers:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="16%" />
+<col width="67%" />
+<col width="17%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+<th class="head">Availability</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>tma_lo</td>
+<td>Low 32 bits of <em>trap memory address</em> register.</td>
+<td>GFX7, GFX8</td>
+</tr>
+<tr class="row-odd"><td>tma_hi</td>
+<td>High 32 bits of <em>trap memory address</em> register.</td>
+<td>GFX7, GFX8</td>
+</tr>
+<tr class="row-even"><td>[tma_lo]</td>
+<td>Low 32 bits of <em>trap memory address</em> register (an alternative syntax).</td>
+<td>GFX7, GFX8</td>
+</tr>
+<tr class="row-odd"><td>[tma_hi]</td>
+<td>High 32 bits of <em>trap memory address</em> register (an alternative syntax).</td>
+<td>GFX7, GFX8</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Note that <em>tma</em>, <em>tma_lo</em> and <em>tma_hi</em> are not accessible as assembler registers in GFX9 and GFX10,
+but <em>tma</em> is readable/writable with the help of <em>s_get_reg</em> and <em>s_set_reg</em> instructions.</p>
+</div>
+<div class="section" id="flat-scratch">
+<span id="amdgpu-synid-flat-scratch"></span><h3><a class="toc-backref" href="#id10">flat_scratch</a><a class="headerlink" href="#flat-scratch" title="Permalink to this headline">¶</a></h3>
+<p>Flat scratch address, 64-bits wide. Holds the base address of scratch memory.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="35%" />
+<col width="65%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>flat_scratch</td>
+<td>64-bit <em>flat scratch</em> address register.</td>
+</tr>
+<tr class="row-odd"><td>[flat_scratch]</td>
+<td>64-bit <em>flat scratch</em> address register (an alternative syntax).</td>
+</tr>
+<tr class="row-even"><td>[flat_scratch_lo,flat_scratch_hi]</td>
+<td>64-bit <em>flat scratch</em> address register (an alternative syntax).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>High and low 32 bits of <em>flat scratch</em> address may be accessed as separate registers:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="26%" />
+<col width="74%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>flat_scratch_lo</td>
+<td>Low 32 bits of <em>flat scratch</em> address register.</td>
+</tr>
+<tr class="row-odd"><td>flat_scratch_hi</td>
+<td>High 32 bits of <em>flat scratch</em> address register.</td>
+</tr>
+<tr class="row-even"><td>[flat_scratch_lo]</td>
+<td>Low 32 bits of <em>flat scratch</em> address register (an alternative syntax).</td>
+</tr>
+<tr class="row-odd"><td>[flat_scratch_hi]</td>
+<td>High 32 bits of <em>flat scratch</em> address register (an alternative syntax).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="xnack">
+<span id="amdgpu-synid-xnack"></span><h3><a class="toc-backref" href="#id11">xnack</a><a class="headerlink" href="#xnack" title="Permalink to this headline">¶</a></h3>
+<p>Xnack mask, 64-bits wide. Holds a 64-bit mask of which threads
+received an <em>XNACK</em> due to a vector memory operation.</p>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">GFX7 does not support <em>xnack</em> feature. For availability of this feature in other GPUs, refer <a class="reference internal" href="AMDGPUUsage.html#amdgpu-processors"><span class="std std-ref">this table</span></a>.</p>
+</div>
+<p></p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="36%" />
+<col width="64%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>xnack_mask</td>
+<td>64-bit <em>xnack mask</em> register.</td>
+</tr>
+<tr class="row-odd"><td>[xnack_mask]</td>
+<td>64-bit <em>xnack mask</em> register (an alternative syntax).</td>
+</tr>
+<tr class="row-even"><td>[xnack_mask_lo,xnack_mask_hi]</td>
+<td>64-bit <em>xnack mask</em> register (an alternative syntax).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>High and low 32 bits of <em>xnack mask</em> may be accessed as separate registers:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="25%" />
+<col width="75%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>xnack_mask_lo</td>
+<td>Low 32 bits of <em>xnack mask</em> register.</td>
+</tr>
+<tr class="row-odd"><td>xnack_mask_hi</td>
+<td>High 32 bits of <em>xnack mask</em> register.</td>
+</tr>
+<tr class="row-even"><td>[xnack_mask_lo]</td>
+<td>Low 32 bits of <em>xnack mask</em> register (an alternative syntax).</td>
+</tr>
+<tr class="row-odd"><td>[xnack_mask_hi]</td>
+<td>High 32 bits of <em>xnack mask</em> register (an alternative syntax).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="vcc">
+<span id="amdgpu-synid-vcc-lo"></span><span id="amdgpu-synid-vcc"></span><h3><a class="toc-backref" href="#id12">vcc</a><a class="headerlink" href="#vcc" title="Permalink to this headline">¶</a></h3>
+<p>Vector condition code, 64-bits wide. A bit mask with one bit per thread;
+it holds the result of a vector compare operation.</p>
+<p>Note that GFX10 H/W does not use high 32 bits of <em>vcc</em> in <em>wave32</em> mode.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="18%" />
+<col width="82%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>vcc</td>
+<td>64-bit <em>vector condition code</em> register.</td>
+</tr>
+<tr class="row-odd"><td>[vcc]</td>
+<td>64-bit <em>vector condition code</em> register (an alternative syntax).</td>
+</tr>
+<tr class="row-even"><td>[vcc_lo,vcc_hi]</td>
+<td>64-bit <em>vector condition code</em> register (an alternative syntax).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>High and low 32 bits of <em>vector condition code</em> may be accessed as separate registers:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="18%" />
+<col width="82%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>vcc_lo</td>
+<td>Low 32 bits of <em>vector condition code</em> register.</td>
+</tr>
+<tr class="row-odd"><td>vcc_hi</td>
+<td>High 32 bits of <em>vector condition code</em> register.</td>
+</tr>
+<tr class="row-even"><td>[vcc_lo]</td>
+<td>Low 32 bits of <em>vector condition code</em> register (an alternative syntax).</td>
+</tr>
+<tr class="row-odd"><td>[vcc_hi]</td>
+<td>High 32 bits of <em>vector condition code</em> register (an alternative syntax).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="m0">
+<span id="amdgpu-synid-m0"></span><h3><a class="toc-backref" href="#id13">m0</a><a class="headerlink" href="#m0" title="Permalink to this headline">¶</a></h3>
+<p>A 32-bit memory register. It has various uses,
+including register indexing and bounds checking.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="18%" />
+<col width="82%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>m0</td>
+<td>A 32-bit <em>memory</em> register.</td>
+</tr>
+<tr class="row-odd"><td>[m0]</td>
+<td>A 32-bit <em>memory</em> register (an alternative syntax).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="exec">
+<span id="amdgpu-synid-exec"></span><h3><a class="toc-backref" href="#id14">exec</a><a class="headerlink" href="#exec" title="Permalink to this headline">¶</a></h3>
+<p>Execute mask, 64-bits wide. A bit mask with one bit per thread,
+which is applied to vector instructions and controls which threads execute
+and which ignore the instruction.</p>
+<p>Note that GFX10 H/W does not use high 32 bits of <em>exec</em> in <em>wave32</em> mode.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="24%" />
+<col width="76%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>exec</td>
+<td>64-bit <em>execute mask</em> register.</td>
+</tr>
+<tr class="row-odd"><td>[exec]</td>
+<td>64-bit <em>execute mask</em> register (an alternative syntax).</td>
+</tr>
+<tr class="row-even"><td>[exec_lo,exec_hi]</td>
+<td>64-bit <em>execute mask</em> register (an alternative syntax).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>High and low 32 bits of <em>execute mask</em> may be accessed as separate registers:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="24%" />
+<col width="76%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>exec_lo</td>
+<td>Low 32 bits of <em>execute mask</em> register.</td>
+</tr>
+<tr class="row-odd"><td>exec_hi</td>
+<td>High 32 bits of <em>execute mask</em> register.</td>
+</tr>
+<tr class="row-even"><td>[exec_lo]</td>
+<td>Low 32 bits of <em>execute mask</em> register (an alternative syntax).</td>
+</tr>
+<tr class="row-odd"><td>[exec_hi]</td>
+<td>High 32 bits of <em>execute mask</em> register (an alternative syntax).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="vccz">
+<span id="amdgpu-synid-vccz"></span><h3><a class="toc-backref" href="#id15">vccz</a><a class="headerlink" href="#vccz" title="Permalink to this headline">¶</a></h3>
+<p>A single bit flag indicating that the <a class="reference internal" href="#amdgpu-synid-vcc"><span class="std std-ref">vcc</span></a> is all zeros.</p>
+<p>Note. When GFX10 operates in <em>wave32</em> mode, this register reflects state of <a class="reference internal" href="#amdgpu-synid-vcc-lo"><span class="std std-ref">vcc_lo</span></a>.</p>
+</div>
+<div class="section" id="execz">
+<span id="amdgpu-synid-execz"></span><h3><a class="toc-backref" href="#id16">execz</a><a class="headerlink" href="#execz" title="Permalink to this headline">¶</a></h3>
+<p>A single bit flag indicating that the <a class="reference internal" href="#amdgpu-synid-exec"><span class="std std-ref">exec</span></a> is all zeros.</p>
+<p>Note. When GFX10 operates in <em>wave32</em> mode, this register reflects state of <a class="reference internal" href="#amdgpu-synid-exec"><span class="std std-ref">exec_lo</span></a>.</p>
+</div>
+<div class="section" id="scc">
+<span id="amdgpu-synid-scc"></span><h3><a class="toc-backref" href="#id17">scc</a><a class="headerlink" href="#scc" title="Permalink to this headline">¶</a></h3>
+<p>A single bit flag indicating the result of a scalar compare operation.</p>
+</div>
+<div class="section" id="lds-direct">
+<span id="amdgpu-synid-lds-direct"></span><h3><a class="toc-backref" href="#id18">lds_direct</a><a class="headerlink" href="#lds-direct" title="Permalink to this headline">¶</a></h3>
+<p>A special operand which supplies a 32-bit value
+fetched from <em>LDS</em> memory using <a class="reference internal" href="#amdgpu-synid-m0"><span class="std std-ref">m0</span></a> as an address.</p>
+</div>
+<div class="section" id="null">
+<span id="amdgpu-synid-null"></span><h3><a class="toc-backref" href="#id19">null</a><a class="headerlink" href="#null" title="Permalink to this headline">¶</a></h3>
+<p>This is a special operand which may be used as a source or a destination.</p>
+<p>When used as a destination, the result of the operation is discarded.</p>
+<p>When used as a source, it supplies zero value.</p>
+<p>GFX10 only.</p>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">Due to a H/W bug, this operand cannot be used with VALU instructions in first generation of GFX10.</p>
+</div>
+</div>
+<div class="section" id="constant">
+<span id="amdgpu-synid-constant"></span><h3><a class="toc-backref" href="#id20">constant</a><a class="headerlink" href="#constant" title="Permalink to this headline">¶</a></h3>
+<p>A set of integer and floating-point <em>inline</em> constants and values:</p>
+<ul class="simple">
+<li><a class="reference internal" href="#amdgpu-synid-iconst"><span class="std std-ref">iconst</span></a></li>
+<li><a class="reference internal" href="#amdgpu-synid-fconst"><span class="std std-ref">fconst</span></a></li>
+<li><a class="reference internal" href="#amdgpu-synid-ival"><span class="std std-ref">ival</span></a></li>
+</ul>
+<p>In contrast with <a class="reference internal" href="#amdgpu-synid-literal"><span class="std std-ref">literals</span></a>, these operands are encoded as a part of instruction.</p>
+<p>If a number may be encoded as either
+a <a class="reference internal" href="#amdgpu-synid-literal"><span class="std std-ref">literal</span></a> or
+a <a class="reference internal" href="#amdgpu-synid-constant"><span class="std std-ref">constant</span></a>,
+assembler selects the latter encoding as more efficient.</p>
+<div class="section" id="iconst">
+<span id="amdgpu-synid-iconst"></span><h4><a class="toc-backref" href="#id21">iconst</a><a class="headerlink" href="#iconst" title="Permalink to this headline">¶</a></h4>
+<p>An <a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>
+encoded as an <em>inline constant</em>.</p>
+<p>Only a small fraction of integer numbers may be encoded as <em>inline constants</em>.
+They are enumerated in the table below.
+Other integer numbers have to be encoded as <a class="reference internal" href="#amdgpu-synid-literal"><span class="std std-ref">literals</span></a>.</p>
+<p>Integer <em>inline constants</em> are converted to
+<a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">expected operand type</span></a>
+as described <a class="reference internal" href="#amdgpu-synid-int-const-conv"><span class="std std-ref">here</span></a>.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="49%" />
+<col width="51%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Value</th>
+<th class="head">Note</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>{0..64}</td>
+<td>Positive integer inline constants.</td>
+</tr>
+<tr class="row-odd"><td>{-16..-1}</td>
+<td>Negative integer inline constants.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">GFX7 does not support inline constants for <em>f16</em> operands.</p>
+</div>
+</div>
+<div class="section" id="fconst">
+<span id="amdgpu-synid-fconst"></span><h4><a class="toc-backref" href="#id22">fconst</a><a class="headerlink" href="#fconst" title="Permalink to this headline">¶</a></h4>
+<p>A <a class="reference internal" href="#amdgpu-synid-floating-point-number"><span class="std std-ref">floating-point number</span></a>
+encoded as an <em>inline constant</em>.</p>
+<p>Only a small fraction of floating-point numbers may be encoded as <em>inline constants</em>.
+They are enumerated in the table below.
+Other floating-point numbers have to be encoded as <a class="reference internal" href="#amdgpu-synid-literal"><span class="std std-ref">literals</span></a>.</p>
+<p>Floating-point <em>inline constants</em> are converted to
+<a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">expected operand type</span></a>
+as described <a class="reference internal" href="#amdgpu-synid-fp-const-conv"><span class="std std-ref">here</span></a>.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="23%" />
+<col width="58%" />
+<col width="20%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Value</th>
+<th class="head">Note</th>
+<th class="head">Availability</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>0.0</td>
+<td>The same as integer constant 0.</td>
+<td>All GPUs</td>
+</tr>
+<tr class="row-odd"><td>0.5</td>
+<td>Floating-point constant 0.5</td>
+<td>All GPUs</td>
+</tr>
+<tr class="row-even"><td>1.0</td>
+<td>Floating-point constant 1.0</td>
+<td>All GPUs</td>
+</tr>
+<tr class="row-odd"><td>2.0</td>
+<td>Floating-point constant 2.0</td>
+<td>All GPUs</td>
+</tr>
+<tr class="row-even"><td>4.0</td>
+<td>Floating-point constant 4.0</td>
+<td>All GPUs</td>
+</tr>
+<tr class="row-odd"><td>-0.5</td>
+<td>Floating-point constant -0.5</td>
+<td>All GPUs</td>
+</tr>
+<tr class="row-even"><td>-1.0</td>
+<td>Floating-point constant -1.0</td>
+<td>All GPUs</td>
+</tr>
+<tr class="row-odd"><td>-2.0</td>
+<td>Floating-point constant -2.0</td>
+<td>All GPUs</td>
+</tr>
+<tr class="row-even"><td>-4.0</td>
+<td>Floating-point constant -4.0</td>
+<td>All GPUs</td>
+</tr>
+<tr class="row-odd"><td>0.1592</td>
+<td>1.0/(2.0*pi). Use only for 16-bit operands.</td>
+<td>GFX8, GFX9, GFX10</td>
+</tr>
+<tr class="row-even"><td>0.15915494</td>
+<td>1.0/(2.0*pi). Use only for 16- and 32-bit operands.</td>
+<td>GFX8, GFX9, GFX10</td>
+</tr>
+<tr class="row-odd"><td>0.15915494309189532</td>
+<td>1.0/(2.0*pi).</td>
+<td>GFX8, GFX9, GFX10</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">GFX7 does not support inline constants for <em>f16</em> operands.</p>
+</div>
+</div>
+<div class="section" id="ival">
+<span id="amdgpu-synid-ival"></span><h4><a class="toc-backref" href="#id23">ival</a><a class="headerlink" href="#ival" title="Permalink to this headline">¶</a></h4>
+<p>A symbolic operand encoded as an <em>inline constant</em>.
+These operands provide read-only access to H/W registers.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="28%" />
+<col width="56%" />
+<col width="15%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Note</th>
+<th class="head">Availability</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>shared_base</td>
+<td>Base address of shared memory region.</td>
+<td>GFX9, GFX10</td>
+</tr>
+<tr class="row-odd"><td>shared_limit</td>
+<td>Address of the end of shared memory region.</td>
+<td>GFX9, GFX10</td>
+</tr>
+<tr class="row-even"><td>private_base</td>
+<td>Base address of private memory region.</td>
+<td>GFX9, GFX10</td>
+</tr>
+<tr class="row-odd"><td>private_limit</td>
+<td>Address of the end of private memory region.</td>
+<td>GFX9, GFX10</td>
+</tr>
+<tr class="row-even"><td>pops_exiting_wave_id</td>
+<td>A dedicated counter for POPS.</td>
+<td>GFX9, GFX10</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="literal">
+<span id="amdgpu-synid-literal"></span><h3><a class="toc-backref" href="#id24">literal</a><a class="headerlink" href="#literal" title="Permalink to this headline">¶</a></h3>
+<p>A literal is a 64-bit value which is encoded as a separate 32-bit dword in the instruction stream.</p>
+<p>If a number may be encoded as either
+a <a class="reference internal" href="#amdgpu-synid-literal"><span class="std std-ref">literal</span></a> or
+an <a class="reference internal" href="#amdgpu-synid-constant"><span class="std std-ref">inline constant</span></a>,
+assembler selects the latter encoding as more efficient.</p>
+<p>Literals may be specified as <a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>,
+<a class="reference internal" href="#amdgpu-synid-floating-point-number"><span class="std std-ref">floating-point numbers</span></a> or
+<a class="reference internal" href="#amdgpu-synid-expression"><span class="std std-ref">expressions</span></a>
+(expressions are currently supported for 32-bit operands only).</p>
+<p>A 64-bit literal value is converted by assembler
+to an <a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">expected operand type</span></a>
+as described <a class="reference internal" href="#amdgpu-synid-lit-conv"><span class="std std-ref">here</span></a>.</p>
+<p>An instruction may use only one literal but several operands may refer the same literal.</p>
+</div>
+<div class="section" id="uimm8">
+<span id="amdgpu-synid-uimm8"></span><h3><a class="toc-backref" href="#id25">uimm8</a><a class="headerlink" href="#uimm8" title="Permalink to this headline">¶</a></h3>
+<p>A 8-bit positive <a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.
+The value is encoded as part of the opcode so it is free to use.</p>
+</div>
+<div class="section" id="uimm32">
+<span id="amdgpu-synid-uimm32"></span><h3><a class="toc-backref" href="#id26">uimm32</a><a class="headerlink" href="#uimm32" title="Permalink to this headline">¶</a></h3>
+<p>A 32-bit positive <a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.
+The value is stored as a separate 32-bit dword in the instruction stream.</p>
+</div>
+<div class="section" id="uimm20">
+<span id="amdgpu-synid-uimm20"></span><h3><a class="toc-backref" href="#id27">uimm20</a><a class="headerlink" href="#uimm20" title="Permalink to this headline">¶</a></h3>
+<p>A 20-bit positive <a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</p>
+</div>
+<div class="section" id="uimm21">
+<span id="amdgpu-synid-uimm21"></span><h3><a class="toc-backref" href="#id28">uimm21</a><a class="headerlink" href="#uimm21" title="Permalink to this headline">¶</a></h3>
+<p>A 21-bit positive <a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</p>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">Assembler currently supports 20-bit offsets only. Use <a class="reference internal" href="#amdgpu-synid-uimm20"><span class="std std-ref">uimm20</span></a> as a replacement.</p>
+</div>
+</div>
+<div class="section" id="simm21">
+<span id="amdgpu-synid-simm21"></span><h3><a class="toc-backref" href="#id29">simm21</a><a class="headerlink" href="#simm21" title="Permalink to this headline">¶</a></h3>
+<p>A 21-bit <a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>.</p>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">Assembler currently supports 20-bit unsigned offsets only. Use <a class="reference internal" href="#amdgpu-synid-uimm20"><span class="std std-ref">uimm20</span></a> as a replacement.</p>
+</div>
+</div>
+<div class="section" id="off">
+<span id="amdgpu-synid-off"></span><h3><a class="toc-backref" href="#id30">off</a><a class="headerlink" href="#off" title="Permalink to this headline">¶</a></h3>
+<p>A special entity which indicates that the value of this operand is not used.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="40%" />
+<col width="60%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>off</td>
+<td>Indicates an unused operand.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="numbers">
+<span id="amdgpu-synid-number"></span><h2><a class="toc-backref" href="#id31">Numbers</a><a class="headerlink" href="#numbers" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="integer-numbers">
+<span id="amdgpu-synid-integer-number"></span><h3><a class="toc-backref" href="#id32">Integer Numbers</a><a class="headerlink" href="#integer-numbers" title="Permalink to this headline">¶</a></h3>
+<p>Integer numbers are 64 bits wide.
+They may be specified in binary, octal, hexadecimal and decimal formats:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="28%" />
+<col width="72%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Format</th>
+<th class="head">Syntax</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>Decimal</td>
+<td>[-]?[1-9][0-9]*</td>
+</tr>
+<tr class="row-odd"><td>Binary</td>
+<td>[-]?0b[01]+</td>
+</tr>
+<tr class="row-even"><td>Octal</td>
+<td>[-]?0[0-7]+</td>
+</tr>
+<tr class="row-odd"><td>Hexadecimal</td>
+<td>[-]?0x[0-9a-fA-F]+</td>
+</tr>
+<tr class="row-even"><td></td>
+<td>[-]?[0x]?[0-9][0-9a-fA-F]*[hH]</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">-</span><span class="mi">1234</span>
+<span class="mb">0b1010</span>
+<span class="mi">010</span>
+<span class="mh">0xff</span>
+<span class="mi">0</span><span class="n">ffh</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="floating-point-numbers">
+<span id="amdgpu-synid-floating-point-number"></span><h3><a class="toc-backref" href="#id33">Floating-Point Numbers</a><a class="headerlink" href="#floating-point-numbers" title="Permalink to this headline">¶</a></h3>
+<p>All floating-point numbers are handled as double (64 bits wide).</p>
+<p>Floating-point numbers may be specified in hexadecimal and decimal formats:</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="11%" />
+<col width="44%" />
+<col width="44%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Format</th>
+<th class="head">Syntax</th>
+<th class="head">Note</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>Decimal</td>
+<td>[-]?[0-9]*[.][0-9]*([eE][+-]?[0-9]*)?</td>
+<td>Must include either a decimal separator or an exponent.</td>
+</tr>
+<tr class="row-odd"><td>Hexadecimal</td>
+<td>[-]0x[0-9a-fA-F]*(.[0-9a-fA-F]*)?[pP][+-]?[0-9a-fA-F]+</td>
+<td> </td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">-</span><span class="mf">1.234</span>
+<span class="mf">234e2</span>
+<span class="o">-</span><span class="mh">0x1af</span><span class="n">p</span><span class="o">-</span><span class="mi">10</span>
+<span class="mi">0</span><span class="n">x</span><span class="o">.</span><span class="mi">1</span><span class="n">afp10</span>
+</pre></div>
+</div>
+</div>
+</div>
+<div class="section" id="expressions">
+<span id="amdgpu-synid-expression"></span><h2><a class="toc-backref" href="#id34">Expressions</a><a class="headerlink" href="#expressions" title="Permalink to this headline">¶</a></h2>
+<p>An expression specifies an address or a numeric value.
+There are two kinds of expressions:</p>
+<ul class="simple">
+<li><a class="reference internal" href="#amdgpu-synid-absolute-expression"><span class="std std-ref">Absolute</span></a>.</li>
+<li><a class="reference internal" href="#amdgpu-synid-relocatable-expression"><span class="std std-ref">Relocatable</span></a>.</li>
+</ul>
+<div class="section" id="absolute-expressions">
+<span id="amdgpu-synid-absolute-expression"></span><h3><a class="toc-backref" href="#id35">Absolute Expressions</a><a class="headerlink" href="#absolute-expressions" title="Permalink to this headline">¶</a></h3>
+<p>The value of an absolute expression remains the same after program relocation.
+Absolute expressions must not include unassigned and relocatable values
+such as labels.</p>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">x</span> <span class="o">=</span> <span class="o">-</span><span class="mi">1</span>
+<span class="n">y</span> <span class="o">=</span> <span class="n">x</span> <span class="o">+</span> <span class="mi">10</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="relocatable-expressions">
+<span id="amdgpu-synid-relocatable-expression"></span><h3><a class="toc-backref" href="#id36">Relocatable Expressions</a><a class="headerlink" href="#relocatable-expressions" title="Permalink to this headline">¶</a></h3>
+<p>The value of a relocatable expression depends on program relocation.</p>
+<p>Note that use of relocatable expressions is limited with branch targets
+and 32-bit <a class="reference internal" href="#amdgpu-synid-literal"><span class="std std-ref">literals</span></a>.</p>
+<p>Addition information about relocation may be found <a class="reference internal" href="AMDGPUUsage.html#amdgpu-relocation-records"><span class="std std-ref">here</span></a>.</p>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">y</span> <span class="o">=</span> <span class="n">x</span> <span class="o">+</span> <span class="mi">10</span> <span class="o">//</span> <span class="n">x</span> <span class="ow">is</span> <span class="ow">not</span> <span class="n">yet</span> <span class="n">defined</span><span class="o">.</span> <span class="n">Undefined</span> <span class="n">symbols</span> <span class="n">are</span> <span class="n">assumed</span> <span class="n">to</span> <span class="n">be</span> <span class="n">PC</span><span class="o">-</span><span class="n">relative</span><span class="o">.</span>
+<span class="n">z</span> <span class="o">=</span> <span class="o">.</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="expression-data-type">
+<h3><a class="toc-backref" href="#id37">Expression Data Type</a><a class="headerlink" href="#expression-data-type" title="Permalink to this headline">¶</a></h3>
+<p>Expressions and operands of expressions are interpreted as 64-bit integers.</p>
+<p>Expressions may include 64-bit <a class="reference internal" href="#amdgpu-synid-floating-point-number"><span class="std std-ref">floating-point numbers</span></a> (double).
+However these operands are also handled as 64-bit integers
+using binary representation of specified floating-point numbers.
+No conversion from floating-point to integer is performed.</p>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span>x = 0.1 // x is assigned an integer 4591870180066957722 which is a binary representation of 0.1.
+y = x + x // y is a sum of two integer values; it is not equal to 0.2!
+</pre></div>
+</div>
+</div>
+<div class="section" id="syntax">
+<h3><a class="toc-backref" href="#id38">Syntax</a><a class="headerlink" href="#syntax" title="Permalink to this headline">¶</a></h3>
+<p>Expressions are composed of
+<a class="reference internal" href="#amdgpu-synid-symbol"><span class="std std-ref">symbols</span></a>,
+<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>,
+<a class="reference internal" href="#amdgpu-synid-floating-point-number"><span class="std std-ref">floating-point numbers</span></a>,
+<a class="reference internal" href="#amdgpu-synid-expression-bin-op"><span class="std std-ref">binary operators</span></a>,
+<a class="reference internal" href="#amdgpu-synid-expression-un-op"><span class="std std-ref">unary operators</span></a> and subexpressions.</p>
+<p>Expressions may also use â.â which is a reference to the current PC (program counter).</p>
+<p>The syntax of expressions is shown below:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">expr</span> <span class="p">::</span><span class="o">=</span> <span class="n">expr</span> <span class="n">binop</span> <span class="n">expr</span> <span class="o">|</span> <span class="n">primaryexpr</span> <span class="p">;</span>
+
+<span class="n">primaryexpr</span> <span class="p">::</span><span class="o">=</span> <span class="s1">'('</span> <span class="n">expr</span> <span class="s1">')'</span> <span class="o">|</span> <span class="n">symbol</span> <span class="o">|</span> <span class="n">number</span> <span class="o">|</span> <span class="s1">'.'</span> <span class="o">|</span> <span class="n">unop</span> <span class="n">primaryexpr</span> <span class="p">;</span>
+
+<span class="n">binop</span> <span class="p">::</span><span class="o">=</span> <span class="s1">'&&'</span>
+ <span class="o">|</span> <span class="s1">'||'</span>
+ <span class="o">|</span> <span class="s1">'|'</span>
+ <span class="o">|</span> <span class="s1">'^'</span>
+ <span class="o">|</span> <span class="s1">'&'</span>
+ <span class="o">|</span> <span class="s1">'!'</span>
+ <span class="o">|</span> <span class="s1">'=='</span>
+ <span class="o">|</span> <span class="s1">'!='</span>
+ <span class="o">|</span> <span class="s1">'<>'</span>
+ <span class="o">|</span> <span class="s1">'<'</span>
+ <span class="o">|</span> <span class="s1">'<='</span>
+ <span class="o">|</span> <span class="s1">'>'</span>
+ <span class="o">|</span> <span class="s1">'>='</span>
+ <span class="o">|</span> <span class="s1">'<<'</span>
+ <span class="o">|</span> <span class="s1">'>>'</span>
+ <span class="o">|</span> <span class="s1">'+'</span>
+ <span class="o">|</span> <span class="s1">'-'</span>
+ <span class="o">|</span> <span class="s1">'*'</span>
+ <span class="o">|</span> <span class="s1">'/'</span>
+ <span class="o">|</span> <span class="s1">'%'</span> <span class="p">;</span>
+
+<span class="n">unop</span> <span class="p">::</span><span class="o">=</span> <span class="s1">'~'</span>
+ <span class="o">|</span> <span class="s1">'+'</span>
+ <span class="o">|</span> <span class="s1">'-'</span>
+ <span class="o">|</span> <span class="s1">'!'</span> <span class="p">;</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="binary-operators">
+<span id="amdgpu-synid-expression-bin-op"></span><h3><a class="toc-backref" href="#id39">Binary Operators</a><a class="headerlink" href="#binary-operators" title="Permalink to this headline">¶</a></h3>
+<p>Binary operators are described in the following table.
+They operate on and produce 64-bit integers.
+Operators with higher priority are performed first.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="15%" />
+<col width="14%" />
+<col width="71%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Operator</th>
+<th class="head">Priority</th>
+<th class="head">Meaning</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>*</td>
+<td>5</td>
+<td>Integer multiplication.</td>
+</tr>
+<tr class="row-odd"><td>/</td>
+<td>5</td>
+<td>Integer division.</td>
+</tr>
+<tr class="row-even"><td>%</td>
+<td>5</td>
+<td>Integer signed remainder.</td>
+</tr>
+<tr class="row-odd"><td>+</td>
+<td>4</td>
+<td>Integer addition.</td>
+</tr>
+<tr class="row-even"><td>-</td>
+<td>4</td>
+<td>Integer subtraction.</td>
+</tr>
+<tr class="row-odd"><td><<</td>
+<td>3</td>
+<td>Integer shift left.</td>
+</tr>
+<tr class="row-even"><td>>></td>
+<td>3</td>
+<td>Logical shift right.</td>
+</tr>
+<tr class="row-odd"><td>==</td>
+<td>2</td>
+<td>Equality comparison.</td>
+</tr>
+<tr class="row-even"><td>!=</td>
+<td>2</td>
+<td>Inequality comparison.</td>
+</tr>
+<tr class="row-odd"><td><></td>
+<td>2</td>
+<td>Inequality comparison.</td>
+</tr>
+<tr class="row-even"><td><</td>
+<td>2</td>
+<td>Signed less than comparison.</td>
+</tr>
+<tr class="row-odd"><td><=</td>
+<td>2</td>
+<td>Signed less than or equal comparison.</td>
+</tr>
+<tr class="row-even"><td>></td>
+<td>2</td>
+<td>Signed greater than comparison.</td>
+</tr>
+<tr class="row-odd"><td>>=</td>
+<td>2</td>
+<td>Signed greater than or equal comparison.</td>
+</tr>
+<tr class="row-even"><td>|</td>
+<td>1</td>
+<td>Bitwise or.</td>
+</tr>
+<tr class="row-odd"><td>^</td>
+<td>1</td>
+<td>Bitwise xor.</td>
+</tr>
+<tr class="row-even"><td>&</td>
+<td>1</td>
+<td>Bitwise and.</td>
+</tr>
+<tr class="row-odd"><td>&&</td>
+<td>0</td>
+<td>Logical and.</td>
+</tr>
+<tr class="row-even"><td>||</td>
+<td>0</td>
+<td>Logical or.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="unary-operators">
+<span id="amdgpu-synid-expression-un-op"></span><h3><a class="toc-backref" href="#id40">Unary Operators</a><a class="headerlink" href="#unary-operators" title="Permalink to this headline">¶</a></h3>
+<p>Unary operators are described in the following table.
+They operate on and produce 64-bit integers.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="18%" />
+<col width="82%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Operator</th>
+<th class="head">Meaning</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>!</td>
+<td>Logical negation.</td>
+</tr>
+<tr class="row-odd"><td>~</td>
+<td>Bitwise negation.</td>
+</tr>
+<tr class="row-even"><td>+</td>
+<td>Integer unary plus.</td>
+</tr>
+<tr class="row-odd"><td>-</td>
+<td>Integer unary minus.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="symbols">
+<span id="amdgpu-synid-symbol"></span><h3><a class="toc-backref" href="#id41">Symbols</a><a class="headerlink" href="#symbols" title="Permalink to this headline">¶</a></h3>
+<p>A symbol is a named 64-bit value, representing a relocatable
+address or an absolute (non-relocatable) number.</p>
+<dl class="docutils">
+<dt>Symbol names have the following syntax:</dt>
+<dd><code class="docutils literal notranslate"><span class="pre">[a-zA-Z_.][a-zA-Z0-9_$.@]*</span></code></dd>
+</dl>
+<p>The table below provides several examples of syntax used for symbol definition.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="22%" />
+<col width="78%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Syntax</th>
+<th class="head">Meaning</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>.globl <S></td>
+<td>Declares a global symbol S without assigning it a value.</td>
+</tr>
+<tr class="row-odd"><td>.set <S>, <E></td>
+<td>Assigns the value of an expression E to a symbol S.</td>
+</tr>
+<tr class="row-even"><td><S> = <E></td>
+<td>Assigns the value of an expression E to a symbol S.</td>
+</tr>
+<tr class="row-odd"><td><S>:</td>
+<td>Declares a label S and assigns it the current PC value.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>A symbol may be used before it is declared or assigned;
+unassigned symbols are assumed to be PC-relative.</p>
+<p>Addition information about symbols may be found <a class="reference internal" href="AMDGPUUsage.html#amdgpu-symbols"><span class="std std-ref">here</span></a>.</p>
+</div>
+</div>
+<div class="section" id="conversions">
+<span id="amdgpu-synid-conv"></span><h2><a class="toc-backref" href="#id42">Conversions</a><a class="headerlink" href="#conversions" title="Permalink to this headline">¶</a></h2>
+<p>This section describes what happens when a 64-bit
+<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer number</span></a>, a
+<a class="reference internal" href="#amdgpu-synid-floating-point-number"><span class="std std-ref">floating-point numbers</span></a> or a
+<a class="reference internal" href="#amdgpu-synid-symbol"><span class="std std-ref">symbol</span></a>
+is used for an operand which has a different type or size.</p>
+<p>Depending on operand kind, this conversion is performed by either assembler or AMDGPU H/W:</p>
+<ul class="simple">
+<li>Values encoded as <a class="reference internal" href="#amdgpu-synid-constant"><span class="std std-ref">inline constants</span></a> are handled by H/W.</li>
+<li>Values encoded as <a class="reference internal" href="#amdgpu-synid-literal"><span class="std std-ref">literals</span></a> are converted by assembler.</li>
+</ul>
+<div class="section" id="inline-constants">
+<span id="amdgpu-synid-const-conv"></span><h3><a class="toc-backref" href="#id43">Inline Constants</a><a class="headerlink" href="#inline-constants" title="Permalink to this headline">¶</a></h3>
+<div class="section" id="integer-inline-constants">
+<span id="amdgpu-synid-int-const-conv"></span><h4><a class="toc-backref" href="#id44">Integer Inline Constants</a><a class="headerlink" href="#integer-inline-constants" title="Permalink to this headline">¶</a></h4>
+<p>Integer <a class="reference internal" href="#amdgpu-synid-constant"><span class="std std-ref">inline constants</span></a>
+may be thought of as 64-bit
+<a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>;
+when used as operands they are truncated to the size of
+<a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">expected operand type</span></a>.
+No data type conversions are performed.</p>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">//</span> <span class="n">GFX9</span>
+
+<span class="n">v_add_u16</span> <span class="n">v0</span><span class="p">,</span> <span class="o">-</span><span class="mi">1</span><span class="p">,</span> <span class="mi">0</span> <span class="o">//</span> <span class="n">v0</span> <span class="o">=</span> <span class="mh">0xFFFF</span>
+<span class="n">v_add_f16</span> <span class="n">v0</span><span class="p">,</span> <span class="o">-</span><span class="mi">1</span><span class="p">,</span> <span class="mi">0</span> <span class="o">//</span> <span class="n">v0</span> <span class="o">=</span> <span class="mh">0xFFFF</span> <span class="p">(</span><span class="n">NaN</span><span class="p">)</span>
+
+<span class="n">v_add_u32</span> <span class="n">v0</span><span class="p">,</span> <span class="o">-</span><span class="mi">1</span><span class="p">,</span> <span class="mi">0</span> <span class="o">//</span> <span class="n">v0</span> <span class="o">=</span> <span class="mh">0xFFFFFFFF</span>
+<span class="n">v_add_f32</span> <span class="n">v0</span><span class="p">,</span> <span class="o">-</span><span class="mi">1</span><span class="p">,</span> <span class="mi">0</span> <span class="o">//</span> <span class="n">v0</span> <span class="o">=</span> <span class="mh">0xFFFFFFFF</span> <span class="p">(</span><span class="n">NaN</span><span class="p">)</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="floating-point-inline-constants">
+<span id="amdgpu-synid-fp-const-conv"></span><h4><a class="toc-backref" href="#id45">Floating-Point Inline Constants</a><a class="headerlink" href="#floating-point-inline-constants" title="Permalink to this headline">¶</a></h4>
+<p>Floating-point <a class="reference internal" href="#amdgpu-synid-constant"><span class="std std-ref">inline constants</span></a>
+may be thought of as 64-bit
+<a class="reference internal" href="#amdgpu-synid-floating-point-number"><span class="std std-ref">floating-point numbers</span></a>;
+when used as operands they are converted to a floating-point number of
+<a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">expected operand size</span></a>.</p>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">//</span> <span class="n">GFX9</span>
+
+<span class="n">v_add_f16</span> <span class="n">v0</span><span class="p">,</span> <span class="mf">1.0</span><span class="p">,</span> <span class="mi">0</span> <span class="o">//</span> <span class="n">v0</span> <span class="o">=</span> <span class="mh">0x3C00</span> <span class="p">(</span><span class="mf">1.0</span><span class="p">)</span>
+<span class="n">v_add_u16</span> <span class="n">v0</span><span class="p">,</span> <span class="mf">1.0</span><span class="p">,</span> <span class="mi">0</span> <span class="o">//</span> <span class="n">v0</span> <span class="o">=</span> <span class="mh">0x3C00</span>
+
+<span class="n">v_add_f32</span> <span class="n">v0</span><span class="p">,</span> <span class="mf">1.0</span><span class="p">,</span> <span class="mi">0</span> <span class="o">//</span> <span class="n">v0</span> <span class="o">=</span> <span class="mh">0x3F800000</span> <span class="p">(</span><span class="mf">1.0</span><span class="p">)</span>
+<span class="n">v_add_u32</span> <span class="n">v0</span><span class="p">,</span> <span class="mf">1.0</span><span class="p">,</span> <span class="mi">0</span> <span class="o">//</span> <span class="n">v0</span> <span class="o">=</span> <span class="mh">0x3F800000</span>
+</pre></div>
+</div>
+</div>
+</div>
+<div class="section" id="literals">
+<span id="amdgpu-synid-lit-conv"></span><h3><a class="toc-backref" href="#id46">Literals</a><a class="headerlink" href="#literals" title="Permalink to this headline">¶</a></h3>
+<div class="section" id="integer-literals">
+<span id="amdgpu-synid-int-lit-conv"></span><h4><a class="toc-backref" href="#id47">Integer Literals</a><a class="headerlink" href="#integer-literals" title="Permalink to this headline">¶</a></h4>
+<p>Integer <a class="reference internal" href="#amdgpu-synid-literal"><span class="std std-ref">literals</span></a>
+are specified as 64-bit <a class="reference internal" href="#amdgpu-synid-integer-number"><span class="std std-ref">integer numbers</span></a>.</p>
+<p>When used as operands they are converted to
+<a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">expected operand type</span></a> as described below.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="13%" />
+<col width="13%" />
+<col width="14%" />
+<col width="61%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Expected type</th>
+<th class="head">Condition</th>
+<th class="head">Result</th>
+<th class="head">Note</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>i16, u16, b16</td>
+<td>cond(num,16)</td>
+<td>num.u16</td>
+<td>Truncate to 16 bits.</td>
+</tr>
+<tr class="row-odd"><td>i32, u32, b32</td>
+<td>cond(num,32)</td>
+<td>num.u32</td>
+<td>Truncate to 32 bits.</td>
+</tr>
+<tr class="row-even"><td>i64</td>
+<td>cond(num,32)</td>
+<td>{-1,num.i32}</td>
+<td>Truncate to 32 bits and then sign-extend the result to 64 bits.</td>
+</tr>
+<tr class="row-odd"><td>u64, b64</td>
+<td>cond(num,32)</td>
+<td>{ 0,num.u32}</td>
+<td>Truncate to 32 bits and then zero-extend the result to 64 bits.</td>
+</tr>
+<tr class="row-even"><td>f16</td>
+<td>cond(num,16)</td>
+<td>num.u16</td>
+<td>Use low 16 bits as an f16 value.</td>
+</tr>
+<tr class="row-odd"><td>f32</td>
+<td>cond(num,32)</td>
+<td>num.u32</td>
+<td>Use low 32 bits as an f32 value.</td>
+</tr>
+<tr class="row-even"><td>f64</td>
+<td>cond(num,32)</td>
+<td>{num.u32,0}</td>
+<td>Use low 32 bits of the number as high 32 bits
+of the result; low 32 bits of the result are zeroed.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>The condition <em>cond(X,S)</em> indicates if a 64-bit number <em>X</em>
+can be converted to a smaller size <em>S</em> by truncation of upper bits.
+There are two cases when the conversion is possible:</p>
+<ul class="simple">
+<li>The truncated bits are all 0.</li>
+<li>The truncated bits are all 1 and the value after truncation has its MSB bit set.</li>
+</ul>
+<p>Examples of valid literals:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">//</span> <span class="n">GFX9</span>
+ <span class="o">//</span> <span class="n">Literal</span> <span class="n">value</span> <span class="n">after</span> <span class="n">conversion</span><span class="p">:</span>
+<span class="n">v_add_u16</span> <span class="n">v0</span><span class="p">,</span> <span class="mh">0xff00</span><span class="p">,</span> <span class="n">v0</span> <span class="o">//</span> <span class="mh">0xff00</span>
+<span class="n">v_add_u16</span> <span class="n">v0</span><span class="p">,</span> <span class="mh">0xffffffffffffff00</span><span class="p">,</span> <span class="n">v0</span> <span class="o">//</span> <span class="mh">0xff00</span>
+<span class="n">v_add_u16</span> <span class="n">v0</span><span class="p">,</span> <span class="o">-</span><span class="mi">256</span><span class="p">,</span> <span class="n">v0</span> <span class="o">//</span> <span class="mh">0xff00</span>
+ <span class="o">//</span> <span class="n">Literal</span> <span class="n">value</span> <span class="n">after</span> <span class="n">conversion</span><span class="p">:</span>
+<span class="n">s_bfe_i64</span> <span class="n">s</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">],</span> <span class="mh">0xffefffff</span><span class="p">,</span> <span class="n">s3</span> <span class="o">//</span> <span class="mh">0xffffffffffefffff</span>
+<span class="n">s_bfe_u64</span> <span class="n">s</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">],</span> <span class="mh">0xffefffff</span><span class="p">,</span> <span class="n">s3</span> <span class="o">//</span> <span class="mh">0x00000000ffefffff</span>
+<span class="n">v_ceil_f64_e32</span> <span class="n">v</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">],</span> <span class="mh">0xffefffff</span> <span class="o">//</span> <span class="mh">0xffefffff00000000</span> <span class="p">(</span><span class="o">-</span><span class="mf">1.7976922776554302e308</span><span class="p">)</span>
+</pre></div>
+</div>
+<p>Examples of invalid literals:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">//</span> <span class="n">GFX9</span>
+
+<span class="n">v_add_u16</span> <span class="n">v0</span><span class="p">,</span> <span class="mh">0x1ff00</span><span class="p">,</span> <span class="n">v0</span> <span class="o">//</span> <span class="n">truncated</span> <span class="n">bits</span> <span class="n">are</span> <span class="ow">not</span> <span class="nb">all</span> <span class="mi">0</span> <span class="ow">or</span> <span class="mi">1</span>
+<span class="n">v_add_u16</span> <span class="n">v0</span><span class="p">,</span> <span class="mh">0xffffffffffff00ff</span><span class="p">,</span> <span class="n">v0</span> <span class="o">//</span> <span class="n">truncated</span> <span class="n">bits</span> <span class="n">do</span> <span class="ow">not</span> <span class="n">match</span> <span class="n">MSB</span> <span class="n">of</span> <span class="n">the</span> <span class="n">result</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="floating-point-literals">
+<span id="amdgpu-synid-fp-lit-conv"></span><h4><a class="toc-backref" href="#id48">Floating-Point Literals</a><a class="headerlink" href="#floating-point-literals" title="Permalink to this headline">¶</a></h4>
+<p>Floating-point <a class="reference internal" href="#amdgpu-synid-literal"><span class="std std-ref">literals</span></a> are specified as 64-bit
+<a class="reference internal" href="#amdgpu-synid-floating-point-number"><span class="std std-ref">floating-point numbers</span></a>.</p>
+<p>When used as operands they are converted to
+<a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">expected operand type</span></a> as described below.</p>
+<blockquote>
+<div><table border="1" class="docutils">
+<colgroup>
+<col width="13%" />
+<col width="13%" />
+<col width="15%" />
+<col width="59%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Expected type</th>
+<th class="head">Condition</th>
+<th class="head">Result</th>
+<th class="head">Note</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>i16, u16, b16</td>
+<td>cond(num,16)</td>
+<td>f16(num)</td>
+<td>Convert to f16 and use bits of the result as an integer value.</td>
+</tr>
+<tr class="row-odd"><td>i32, u32, b32</td>
+<td>cond(num,32)</td>
+<td>f32(num)</td>
+<td>Convert to f32 and use bits of the result as an integer value.</td>
+</tr>
+<tr class="row-even"><td>i64, u64, b64</td>
+<td>false</td>
+<td>-</td>
+<td>Conversion disabled because of an unclear semantics.</td>
+</tr>
+<tr class="row-odd"><td>f16</td>
+<td>cond(num,16)</td>
+<td>f16(num)</td>
+<td>Convert to f16.</td>
+</tr>
+<tr class="row-even"><td>f32</td>
+<td>cond(num,32)</td>
+<td>f32(num)</td>
+<td>Convert to f32.</td>
+</tr>
+<tr class="row-odd"><td>f64</td>
+<td>true</td>
+<td>{num.u32.hi,0}</td>
+<td><p class="first">Use high 32 bits of the number as high 32 bits of the result;
+zero-fill low 32 bits of the result.</p>
+<p class="last">Note that the result may differ from the original number.</p>
+</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>The condition <em>cond(X,S)</em> indicates if an f64 number <em>X</em> can be converted
+to a smaller <em>S</em>-bit floating-point type without overflow or underflow.
+Precision lost is allowed.</p>
+<p>Examples of valid literals:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">//</span> <span class="n">GFX9</span>
+
+<span class="n">v_add_f16</span> <span class="n">v1</span><span class="p">,</span> <span class="mf">65500.0</span><span class="p">,</span> <span class="n">v2</span>
+<span class="n">v_add_f32</span> <span class="n">v1</span><span class="p">,</span> <span class="mf">65600.0</span><span class="p">,</span> <span class="n">v2</span>
+
+<span class="o">//</span> <span class="n">Literal</span> <span class="n">value</span> <span class="n">before</span> <span class="n">conversion</span><span class="p">:</span> <span class="mf">1.7976931348623157e308</span> <span class="p">(</span><span class="mh">0x7fefffffffffffff</span><span class="p">)</span>
+<span class="o">//</span> <span class="n">Literal</span> <span class="n">value</span> <span class="n">after</span> <span class="n">conversion</span><span class="p">:</span> <span class="mf">1.7976922776554302e308</span> <span class="p">(</span><span class="mh">0x7fefffff00000000</span><span class="p">)</span>
+<span class="n">v_ceil_f64</span> <span class="n">v</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">],</span> <span class="mf">1.7976931348623157e308</span>
+</pre></div>
+</div>
+<p>Examples of invalid literals:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">//</span> <span class="n">GFX9</span>
+
+<span class="n">v_add_f16</span> <span class="n">v1</span><span class="p">,</span> <span class="mf">65600.0</span><span class="p">,</span> <span class="n">v2</span> <span class="o">//</span> <span class="n">overflow</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="amdgpu-synid-exp-conv">
+<span id="id1"></span><h4><a class="toc-backref" href="#id49">Expressions</a><a class="headerlink" href="#amdgpu-synid-exp-conv" title="Permalink to this headline">¶</a></h4>
+<p>Expressions operate with and result in 64-bit integers.</p>
+<p>When used as operands they are truncated to
+<a class="reference internal" href="AMDGPUInstructionSyntax.html#amdgpu-syn-instruction-type"><span class="std std-ref">expected operand size</span></a>.
+No data type conversions are performed.</p>
+<p>Examples:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">//</span> <span class="n">GFX9</span>
+
+<span class="n">x</span> <span class="o">=</span> <span class="mf">0.1</span>
+<span class="n">v_sqrt_f32</span> <span class="n">v0</span><span class="p">,</span> <span class="n">x</span> <span class="o">//</span> <span class="n">v0</span> <span class="o">=</span> <span class="p">[</span><span class="n">low</span> <span class="mi">32</span> <span class="n">bits</span> <span class="n">of</span> <span class="mf">0.1</span> <span class="p">(</span><span class="n">double</span><span class="p">)]</span>
+<span class="n">v_sqrt_f32</span> <span class="n">v0</span><span class="p">,</span> <span class="p">(</span><span class="mf">0.1</span> <span class="o">+</span> <span class="mi">0</span><span class="p">)</span> <span class="o">//</span> <span class="n">the</span> <span class="n">same</span> <span class="k">as</span> <span class="n">above</span>
+<span class="n">v_sqrt_f32</span> <span class="n">v0</span><span class="p">,</span> <span class="mf">0.1</span> <span class="o">//</span> <span class="n">v0</span> <span class="o">=</span> <span class="p">[</span><span class="mf">0.1</span> <span class="p">(</span><span class="n">double</span><span class="p">)</span> <span class="n">converted</span> <span class="n">to</span> <span class="nb">float</span><span class="p">]</span>
+</pre></div>
+</div>
+</div>
+</div>
+</div>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
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+ <a href="genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="AMDGPUInstructionSyntax.html" title="AMDGPU Instruction Syntax"
+ >next</a> |</li>
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+ <div class="documentwrapper">
+ <div class="body" role="main">
+
+ <div class="section" id="user-guide-for-amdgpu-backend">
+<h1>User Guide for AMDGPU Backend<a class="headerlink" href="#user-guide-for-amdgpu-backend" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#introduction" id="id48">Introduction</a></li>
+<li><a class="reference internal" href="#llvm" id="id49">LLVM</a><ul>
+<li><a class="reference internal" href="#target-triples" id="id50">Target Triples</a></li>
+<li><a class="reference internal" href="#processors" id="id51">Processors</a></li>
+<li><a class="reference internal" href="#target-features" id="id52">Target Features</a></li>
+<li><a class="reference internal" href="#address-spaces" id="id53">Address Spaces</a></li>
+<li><a class="reference internal" href="#memory-scopes" id="id54">Memory Scopes</a></li>
+<li><a class="reference internal" href="#amdgpu-intrinsics" id="id55">AMDGPU Intrinsics</a></li>
+<li><a class="reference internal" href="#amdgpu-attributes" id="id56">AMDGPU Attributes</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#code-object" id="id57">Code Object</a><ul>
+<li><a class="reference internal" href="#header" id="id58">Header</a></li>
+<li><a class="reference internal" href="#sections" id="id59">Sections</a></li>
+<li><a class="reference internal" href="#note-records" id="id60">Note Records</a><ul>
+<li><a class="reference internal" href="#code-object-v2-note-records-mattr-code-object-v3" id="id61">Code Object V2 Note Records (-mattr=-code-object-v3)</a></li>
+<li><a class="reference internal" href="#code-object-v3-note-records-mattr-code-object-v3" id="id62">Code Object V3 Note Records (-mattr=+code-object-v3)</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#symbols" id="id63">Symbols</a></li>
+<li><a class="reference internal" href="#relocation-records" id="id64">Relocation Records</a></li>
+<li><a class="reference internal" href="#dwarf" id="id65">DWARF</a><ul>
+<li><a class="reference internal" href="#address-space-mapping" id="id66">Address Space Mapping</a></li>
+<li><a class="reference internal" href="#register-mapping" id="id67">Register Mapping</a></li>
+<li><a class="reference internal" href="#source-text" id="id68">Source Text</a></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><a class="reference internal" href="#code-conventions" id="id69">Code Conventions</a><ul>
+<li><a class="reference internal" href="#amdhsa" id="id70">AMDHSA</a><ul>
+<li><a class="reference internal" href="#code-object-target-identification" id="id71">Code Object Target Identification</a></li>
+<li><a class="reference internal" href="#code-object-metadata" id="id72">Code Object Metadata</a><ul>
+<li><a class="reference internal" href="#code-object-v2-metadata-mattr-code-object-v3" id="id73">Code Object V2 Metadata (-mattr=-code-object-v3)</a></li>
+<li><a class="reference internal" href="#code-object-v3-metadata-mattr-code-object-v3" id="id74">Code Object V3 Metadata (-mattr=+code-object-v3)</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#kernel-dispatch" id="id75">Kernel Dispatch</a></li>
+<li><a class="reference internal" href="#memory-spaces" id="id76">Memory Spaces</a></li>
+<li><a class="reference internal" href="#image-and-samplers" id="id77">Image and Samplers</a></li>
+<li><a class="reference internal" href="#hsa-signals" id="id78">HSA Signals</a></li>
+<li><a class="reference internal" href="#hsa-aql-queue" id="id79">HSA AQL Queue</a></li>
+<li><a class="reference internal" href="#kernel-descriptor" id="id80">Kernel Descriptor</a><ul>
+<li><a class="reference internal" href="#kernel-descriptor-for-gfx6-gfx10" id="id81">Kernel Descriptor for GFX6-GFX10</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#initial-kernel-execution-state" id="id82">Initial Kernel Execution State</a></li>
+<li><a class="reference internal" href="#kernel-prolog" id="id83">Kernel Prolog</a><ul>
+<li><a class="reference internal" href="#m0" id="id84">M0</a></li>
+<li><a class="reference internal" href="#flat-scratch" id="id85">Flat Scratch</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#memory-model" id="id86">Memory Model</a></li>
+<li><a class="reference internal" href="#trap-handler-abi" id="id87">Trap Handler ABI</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#amdpal" id="id88">AMDPAL</a><ul>
+<li><a class="reference internal" href="#user-data" id="id89">User Data</a></li>
+<li><a class="reference internal" href="#compute-user-data" id="id90">Compute User Data</a></li>
+<li><a class="reference internal" href="#graphics-user-data" id="id91">Graphics User Data</a></li>
+<li><a class="reference internal" href="#global-internal-table" id="id92">Global Internal Table</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#unspecified-os" id="id93">Unspecified OS</a><ul>
+<li><a class="reference internal" href="#id39" id="id94">Trap Handler ABI</a></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><a class="reference internal" href="#source-languages" id="id95">Source Languages</a><ul>
+<li><a class="reference internal" href="#opencl" id="id96">OpenCL</a></li>
+<li><a class="reference internal" href="#hcc" id="id97">HCC</a></li>
+<li><a class="reference internal" href="#assembler" id="id98">Assembler</a><ul>
+<li><a class="reference internal" href="#instructions" id="id99">Instructions</a></li>
+<li><a class="reference internal" href="#operands" id="id100">Operands</a></li>
+<li><a class="reference internal" href="#modifiers" id="id101">Modifiers</a></li>
+<li><a class="reference internal" href="#instruction-examples" id="id102">Instruction Examples</a><ul>
+<li><a class="reference internal" href="#ds" id="id103">DS</a></li>
+<li><a class="reference internal" href="#flat" id="id104">FLAT</a></li>
+<li><a class="reference internal" href="#mubuf" id="id105">MUBUF</a></li>
+<li><a class="reference internal" href="#smrd-smem" id="id106">SMRD/SMEM</a></li>
+<li><a class="reference internal" href="#sop1" id="id107">SOP1</a></li>
+<li><a class="reference internal" href="#sop2" id="id108">SOP2</a></li>
+<li><a class="reference internal" href="#sopc" id="id109">SOPC</a></li>
+<li><a class="reference internal" href="#sopp" id="id110">SOPP</a></li>
+<li><a class="reference internal" href="#valu" id="id111">VALU</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#code-object-v2-predefined-symbols-mattr-code-object-v3" id="id112">Code Object V2 Predefined Symbols (-mattr=-code-object-v3)</a><ul>
+<li><a class="reference internal" href="#option-machine-version-major" id="id113">.option.machine_version_major</a></li>
+<li><a class="reference internal" href="#option-machine-version-minor" id="id114">.option.machine_version_minor</a></li>
+<li><a class="reference internal" href="#option-machine-version-stepping" id="id115">.option.machine_version_stepping</a></li>
+<li><a class="reference internal" href="#kernel-vgpr-count" id="id116">.kernel.vgpr_count</a></li>
+<li><a class="reference internal" href="#kernel-sgpr-count" id="id117">.kernel.sgpr_count</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#code-object-v2-directives-mattr-code-object-v3" id="id118">Code Object V2 Directives (-mattr=-code-object-v3)</a><ul>
+<li><a class="reference internal" href="#hsa-code-object-version-major-minor" id="id119">.hsa_code_object_version major, minor</a></li>
+<li><a class="reference internal" href="#hsa-code-object-isa-major-minor-stepping-vendor-arch" id="id120">.hsa_code_object_isa [major, minor, stepping, vendor, arch]</a></li>
+<li><a class="reference internal" href="#amdgpu-hsa-kernel-name" id="id121">.amdgpu_hsa_kernel (name)</a></li>
+<li><a class="reference internal" href="#amd-kernel-code-t" id="id122">.amd_kernel_code_t</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#code-object-v2-example-source-code-mattr-code-object-v3" id="id123">Code Object V2 Example Source Code (-mattr=-code-object-v3)</a></li>
+<li><a class="reference internal" href="#code-object-v3-predefined-symbols-mattr-code-object-v3" id="id124">Code Object V3 Predefined Symbols (-mattr=+code-object-v3)</a><ul>
+<li><a class="reference internal" href="#amdgcn-gfx-generation-number" id="id125">.amdgcn.gfx_generation_number</a></li>
+<li><a class="reference internal" href="#amdgcn-gfx-generation-minor" id="id126">.amdgcn.gfx_generation_minor</a></li>
+<li><a class="reference internal" href="#amdgcn-gfx-generation-stepping" id="id127">.amdgcn.gfx_generation_stepping</a></li>
+<li><a class="reference internal" href="#amdgcn-next-free-vgpr" id="id128">.amdgcn.next_free_vgpr</a></li>
+<li><a class="reference internal" href="#amdgcn-next-free-sgpr" id="id129">.amdgcn.next_free_sgpr</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#code-object-v3-directives-mattr-code-object-v3" id="id130">Code Object V3 Directives (-mattr=+code-object-v3)</a><ul>
+<li><a class="reference internal" href="#amdgcn-target-target" id="id131">.amdgcn_target <target></a></li>
+<li><a class="reference internal" href="#amdhsa-kernel-name" id="id132">.amdhsa_kernel <name></a></li>
+<li><a class="reference internal" href="#amdgpu-metadata" id="id133">.amdgpu_metadata</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#code-object-v3-example-source-code-mattr-code-object-v3" id="id134">Code Object V3 Example Source Code (-mattr=+code-object-v3)</a></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><a class="reference internal" href="#additional-documentation" id="id135">Additional Documentation</a></li>
+</ul>
+</div>
+<div class="section" id="introduction">
+<h2><a class="toc-backref" href="#id48">Introduction</a><a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
+<p>The AMDGPU backend provides ISA code generation for AMD GPUs, starting with the
+R600 family up until the current GCN families. It lives in the
+<code class="docutils literal notranslate"><span class="pre">lib/Target/AMDGPU</span></code> directory.</p>
+</div>
+<div class="section" id="llvm">
+<h2><a class="toc-backref" href="#id49">LLVM</a><a class="headerlink" href="#llvm" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="target-triples">
+<span id="amdgpu-target-triples"></span><h3><a class="toc-backref" href="#id50">Target Triples</a><a class="headerlink" href="#target-triples" title="Permalink to this headline">¶</a></h3>
+<p>Use the <code class="docutils literal notranslate"><span class="pre">clang</span> <span class="pre">-target</span> <span class="pre"><Architecture>-<Vendor>-<OS>-<Environment></span></code> option to
+specify the target triple:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-architecture-table">
+<caption><span class="caption-text">AMDGPU Architectures</span><a class="headerlink" href="#amdgpu-architecture-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="16%" />
+<col width="84%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Architecture</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>AMD GPUs HD2XXX-HD6XXX for graphics and compute shaders.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>AMD GPUs GCN GFX6 onwards for graphics and compute shaders.</td>
+</tr>
+</tbody>
+</table>
+<table border="1" class="docutils" id="amdgpu-vendor-table">
+<caption><span class="caption-text">AMDGPU Vendors</span><a class="headerlink" href="#amdgpu-vendor-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="16%" />
+<col width="84%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Vendor</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">amd</span></code></td>
+<td>Can be used for all AMD GPU usage.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">mesa3d</span></code></td>
+<td>Can be used if the OS is <code class="docutils literal notranslate"><span class="pre">mesa3d</span></code>.</td>
+</tr>
+</tbody>
+</table>
+<table border="1" class="docutils" id="amdgpu-os-table">
+<caption><span class="caption-text">AMDGPU Operating Systems</span><a class="headerlink" href="#amdgpu-os-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="19%" />
+<col width="81%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">OS</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><em><empty></em></td>
+<td>Defaults to the <em>unknown</em> OS.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">amdhsa</span></code></td>
+<td>Compute kernels executed on HSA <a class="reference internal" href="#hsa" id="id1">[HSA]</a> compatible runtimes
+such as AMDâs ROCm <a class="reference internal" href="#amd-rocm" id="id2">[AMD-ROCm]</a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">amdpal</span></code></td>
+<td>Graphic shaders and compute kernels executed on AMD PAL
+runtime.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">mesa3d</span></code></td>
+<td>Graphic shaders and compute kernels executed on Mesa 3D
+runtime.</td>
+</tr>
+</tbody>
+</table>
+<table border="1" class="docutils" id="amdgpu-environment-table">
+<caption><span class="caption-text">AMDGPU Environments</span><a class="headerlink" href="#amdgpu-environment-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="16%" />
+<col width="84%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Environment</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><em><empty></em></td>
+<td>Default.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="processors">
+<span id="amdgpu-processors"></span><h3><a class="toc-backref" href="#id51">Processors</a><a class="headerlink" href="#processors" title="Permalink to this headline">¶</a></h3>
+<p>Use the <code class="docutils literal notranslate"><span class="pre">clang</span> <span class="pre">-mcpu</span> <span class="pre"><Processor></span></code> option to specify the AMD GPU processor. The
+names from both the <em>Processor</em> and <em>Alternative Processor</em> can be used.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-processor-table">
+<caption><span class="caption-text">AMDGPU Processors</span><a class="headerlink" href="#amdgpu-processor-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="12%" />
+<col width="17%" />
+<col width="13%" />
+<col width="6%" />
+<col width="19%" />
+<col width="8%" />
+<col width="25%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Processor</th>
+<th class="head">Alternative
+Processor</th>
+<th class="head">Target
+Triple
+Architecture</th>
+<th class="head">dGPU/
+APU</th>
+<th class="head">Target
+Features
+Supported
+[Default]</th>
+<th class="head">ROCm
+Support</th>
+<th class="head">Example
+Products</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td colspan="7"><strong>Radeon HD 2000/3000 Series (R600)</strong> <a class="reference internal" href="#amd-radeon-hd-2000-3000" id="id3">[AMD-RADEON-HD-2000-3000]</a></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">r630</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">rs880</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">rv670</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td colspan="7"><strong>Radeon HD 4000 Series (R700)</strong> <a class="reference internal" href="#amd-radeon-hd-4000" id="id4">[AMD-RADEON-HD-4000]</a></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">rv710</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">rv730</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">rv770</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td colspan="7"><strong>Radeon HD 5000 Series (Evergreen)</strong> <a class="reference internal" href="#amd-radeon-hd-5000" id="id5">[AMD-RADEON-HD-5000]</a></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">cedar</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">cypress</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">juniper</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">redwood</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">sumo</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td colspan="7"><strong>Radeon HD 6000 Series (Northern Islands)</strong> <a class="reference internal" href="#amd-radeon-hd-6000" id="id6">[AMD-RADEON-HD-6000]</a></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">barts</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">caicos</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">cayman</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">turks</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-even"><td colspan="7"><strong>GCN GFX6 (Southern Islands (SI))</strong> <a class="reference internal" href="#amd-gcn-gfx6" id="id7">[AMD-GCN-GFX6]</a></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">gfx600</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">tahiti</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx601</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">hainan</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">oland</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">pitcairn</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">verde</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td colspan="7"><strong>GCN GFX7 (Sea Islands (CI))</strong> <a class="reference internal" href="#amd-gcn-gfx7" id="id8">[AMD-GCN-GFX7]</a></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx700</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">kaveri</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td> </td>
+<td> </td>
+<td><ul class="first last simple">
+<li>A6-7000</li>
+<li>A6 Pro-7050B</li>
+<li>A8-7100</li>
+<li>A8 Pro-7150B</li>
+<li>A10-7300</li>
+<li>A10 Pro-7350B</li>
+<li>FX-7500</li>
+<li>A8-7200P</li>
+<li>A10-7400P</li>
+<li>FX-7600P</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">gfx701</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">hawaii</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td>ROCm</td>
+<td><ul class="first last simple">
+<li>FirePro W8100</li>
+<li>FirePro W9100</li>
+<li>FirePro S9150</li>
+<li>FirePro S9170</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx702</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td>ROCm</td>
+<td><ul class="first last simple">
+<li>Radeon R9 290</li>
+<li>Radeon R9 290x</li>
+<li>Radeon R390</li>
+<li>Radeon R390x</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">gfx703</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">kabini</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">mullins</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td> </td>
+<td> </td>
+<td><ul class="first last simple">
+<li>E1-2100</li>
+<li>E1-2200</li>
+<li>E1-2500</li>
+<li>E2-3000</li>
+<li>E2-3800</li>
+<li>A4-5000</li>
+<li>A4-5100</li>
+<li>A6-5200</li>
+<li>A4 Pro-3340B</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx704</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">bonaire</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td> </td>
+<td> </td>
+<td><ul class="first last simple">
+<li>Radeon HD 7790</li>
+<li>Radeon HD 8770</li>
+<li>R7 260</li>
+<li>R7 260X</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td colspan="7"><strong>GCN GFX8 (Volcanic Islands (VI))</strong> <a class="reference internal" href="#amd-gcn-gfx8" id="id9">[AMD-GCN-GFX8]</a></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx801</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">carrizo</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td><ul class="first last simple">
+<li>xnack
+[on]</li>
+</ul>
+</td>
+<td> </td>
+<td><ul class="first last simple">
+<li>A6-8500P</li>
+<li>Pro A6-8500B</li>
+<li>A8-8600P</li>
+<li>Pro A8-8600B</li>
+<li>FX-8800P</li>
+<li>Pro A12-8800B</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td><ul class="first last simple">
+<li>xnack
+[on]</li>
+</ul>
+</td>
+<td>ROCm</td>
+<td><ul class="first last simple">
+<li>A10-8700P</li>
+<li>Pro A10-8700B</li>
+<li>A10-8780P</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td><ul class="first last simple">
+<li>xnack
+[on]</li>
+</ul>
+</td>
+<td> </td>
+<td><ul class="first last simple">
+<li>A10-9600P</li>
+<li>A10-9630P</li>
+<li>A12-9700P</li>
+<li>A12-9730P</li>
+<li>FX-9800P</li>
+<li>FX-9830P</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td><ul class="first last simple">
+<li>xnack
+[on]</li>
+</ul>
+</td>
+<td> </td>
+<td><ul class="first last simple">
+<li>E2-9010</li>
+<li>A6-9210</li>
+<li>A9-9410</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx802</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">iceland</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">tonga</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td><ul class="first last simple">
+<li>xnack
+[off]</li>
+</ul>
+</td>
+<td>ROCm</td>
+<td><ul class="first last simple">
+<li>FirePro S7150</li>
+<li>FirePro S7100</li>
+<li>FirePro W7100</li>
+<li>Radeon R285</li>
+<li>Radeon R9 380</li>
+<li>Radeon R9 385</li>
+<li>Mobile FirePro
+M7170</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">gfx803</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">fiji</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td><ul class="first last simple">
+<li>xnack
+[off]</li>
+</ul>
+</td>
+<td>ROCm</td>
+<td><ul class="first last simple">
+<li>Radeon R9 Nano</li>
+<li>Radeon R9 Fury</li>
+<li>Radeon R9 FuryX</li>
+<li>Radeon Pro Duo</li>
+<li>FirePro S9300x2</li>
+<li>Radeon Instinct MI8</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">polaris10</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td><ul class="first last simple">
+<li>xnack
+[off]</li>
+</ul>
+</td>
+<td>ROCm</td>
+<td><ul class="first last simple">
+<li>Radeon RX 470</li>
+<li>Radeon RX 480</li>
+<li>Radeon Instinct MI6</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">polaris11</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td><ul class="first last simple">
+<li>xnack
+[off]</li>
+</ul>
+</td>
+<td>ROCm</td>
+<td><ul class="first last simple">
+<li>Radeon RX 460</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx810</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">stoney</span></code></li>
+</ul>
+</td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td><ul class="first last simple">
+<li>xnack
+[on]</li>
+</ul>
+</td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td colspan="7"><strong>GCN GFX9</strong> <a class="reference internal" href="#amd-gcn-gfx9" id="id10">[AMD-GCN-GFX9]</a></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx900</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td><ul class="first last simple">
+<li>xnack
+[off]</li>
+</ul>
+</td>
+<td>ROCm</td>
+<td><ul class="first last simple">
+<li>Radeon Vega
+Frontier Edition</li>
+<li>Radeon RX Vega 56</li>
+<li>Radeon RX Vega 64</li>
+<li>Radeon RX Vega 64
+Liquid</li>
+<li>Radeon Instinct MI25</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">gfx902</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td><ul class="first last simple">
+<li>xnack
+[on]</li>
+</ul>
+</td>
+<td> </td>
+<td><ul class="first last simple">
+<li>Ryzen 3 2200G</li>
+<li>Ryzen 5 2400G</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx904</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td><ul class="first last simple">
+<li>xnack
+[off]</li>
+</ul>
+</td>
+<td> </td>
+<td><em>TBA</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">gfx906</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td><ul class="first last simple">
+<li>xnack
+[off]</li>
+</ul>
+</td>
+<td> </td>
+<td><ul class="first last simple">
+<li>Radeon Instinct MI50</li>
+<li>Radeon Instinct MI60</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx908</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td><ul class="first last simple">
+<li>xnack
+[off]
+sram-ecc
+[on]</li>
+</ul>
+</td>
+<td> </td>
+<td><em>TBA</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">gfx909</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>APU</td>
+<td><ul class="first last simple">
+<li>xnack
+[on]</li>
+</ul>
+</td>
+<td> </td>
+<td><em>TBA</em> (Raven Ridge 2)</td>
+</tr>
+<tr class="row-even"><td colspan="7"><strong>GCN GFX10</strong> <a class="reference internal" href="#amd-gcn-gfx10" id="id11">[AMD-GCN-GFX10]</a></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">gfx1010</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td><ul class="first last simple">
+<li>xnack
+[off]</li>
+<li>wavefrontsize64
+[off]</li>
+<li>cumode
+[off]</li>
+</ul>
+</td>
+<td> </td>
+<td><em>TBA</em></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">gfx1011</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td><ul class="first last simple">
+<li>xnack
+[off]</li>
+<li>wavefrontsize64
+[off]</li>
+<li>cumode
+[off]</li>
+</ul>
+</td>
+<td> </td>
+<td><em>TBA</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">gfx1012</span></code></td>
+<td> </td>
+<td><code class="docutils literal notranslate"><span class="pre">amdgcn</span></code></td>
+<td>dGPU</td>
+<td><ul class="first last simple">
+<li>xnack
+[off]</li>
+<li>wavefrontsize64
+[off]</li>
+<li>cumode
+[off]</li>
+</ul>
+</td>
+<td> </td>
+<td><em>TBA</em></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="target-features">
+<span id="amdgpu-target-features"></span><h3><a class="toc-backref" href="#id52">Target Features</a><a class="headerlink" href="#target-features" title="Permalink to this headline">¶</a></h3>
+<p>Target features control how code is generated to support certain
+processor specific features. Not all target features are supported by
+all processors. The runtime must ensure that the features supported by
+the device used to execute the code match the features enabled when
+generating the code. A mismatch of features may result in incorrect
+execution, or a reduction in performance.</p>
+<p>The target features supported by each processor, and the default value
+used if not specified explicitly, is listed in
+<a class="reference internal" href="#amdgpu-processor-table"><span class="std std-ref">AMDGPU Processors</span></a>.</p>
+<p>Use the <code class="docutils literal notranslate"><span class="pre">clang</span> <span class="pre">-m[no-]<TargetFeature></span></code> option to specify the AMD GPU
+target features.</p>
+<p>For example:</p>
+<dl class="docutils">
+<dt><code class="docutils literal notranslate"><span class="pre">-mxnack</span></code></dt>
+<dd>Enable the <code class="docutils literal notranslate"><span class="pre">xnack</span></code> feature.</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">-mno-xnack</span></code></dt>
+<dd><p class="first">Disable the <code class="docutils literal notranslate"><span class="pre">xnack</span></code> feature.</p>
+<table border="1" class="last docutils" id="amdgpu-target-feature-table">
+<caption><span class="caption-text">AMDGPU Target Features</span><a class="headerlink" href="#amdgpu-target-feature-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="31%" />
+<col width="69%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Target Feature</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>-m[no-]xnack</td>
+<td><p class="first">Enable/disable generating code that has
+memory clauses that are compatible with
+having XNACK replay enabled.</p>
+<p class="last">This is used for demand paging and page
+migration. If XNACK replay is enabled in
+the device, then if a page fault occurs
+the code may execute incorrectly if the
+<code class="docutils literal notranslate"><span class="pre">xnack</span></code> feature is not enabled. Executing
+code that has the feature enabled on a
+device that does not have XNACK replay
+enabled will execute correctly, but may
+be less performant than code with the
+feature disabled.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>-m[no-]sram-ecc</td>
+<td>Enable/disable generating code that assumes SRAM
+ECC is enabled/disabled.</td>
+</tr>
+<tr class="row-even"><td>-m[no-]wavefrontsize64</td>
+<td>Control the default wavefront size used when
+generating code for kernels. When disabled
+native wavefront size 32 is used, when enabled
+wavefront size 64 is used.</td>
+</tr>
+<tr class="row-odd"><td>-m[no-]cumode</td>
+<td>Control the default wavefront execution mode used
+when generating code for kernels. When disabled
+native WGP wavefront execution mode is used,
+when enabled CU wavefront execution mode is used
+(see <a class="reference internal" href="#amdgpu-amdhsa-memory-model"><span class="std std-ref">Memory Model</span></a>).</td>
+</tr>
+</tbody>
+</table>
+</dd>
+</dl>
+</div>
+<div class="section" id="address-spaces">
+<span id="amdgpu-address-spaces"></span><h3><a class="toc-backref" href="#id53">Address Spaces</a><a class="headerlink" href="#address-spaces" title="Permalink to this headline">¶</a></h3>
+<p>The AMDGPU backend uses the following address space mappings.</p>
+<p>The memory space names used in the table, aside from the region memory space, is
+from the OpenCL standard.</p>
+<p>LLVM Address Space number is used throughout LLVM (for example, in LLVM IR).</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-address-space-mapping-table">
+<caption><span class="caption-text">Address Space Mapping</span><a class="headerlink" href="#amdgpu-address-space-mapping-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="35%" />
+<col width="65%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">LLVM Address Space</th>
+<th class="head">Memory Space</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>0</td>
+<td>Generic (Flat)</td>
+</tr>
+<tr class="row-odd"><td>1</td>
+<td>Global</td>
+</tr>
+<tr class="row-even"><td>2</td>
+<td>Region (GDS)</td>
+</tr>
+<tr class="row-odd"><td>3</td>
+<td>Local (group/LDS)</td>
+</tr>
+<tr class="row-even"><td>4</td>
+<td>Constant</td>
+</tr>
+<tr class="row-odd"><td>5</td>
+<td>Private (Scratch)</td>
+</tr>
+<tr class="row-even"><td>6</td>
+<td>Constant 32-bit</td>
+</tr>
+<tr class="row-odd"><td>7</td>
+<td>Buffer Fat Pointer (experimental)</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>The buffer fat pointer is an experimental address space that is currently
+unsupported in the backend. It exposes a non-integral pointer that is in future
+intended to support the modelling of 128-bit buffer descriptors + a 32-bit
+offset into the buffer descriptor (in total encapsulating a 160-bit âpointerâ),
+allowing us to use normal LLVM load/store/atomic operations to model the buffer
+descriptors used heavily in graphics workloads targeting the backend.</p>
+</div>
+<div class="section" id="memory-scopes">
+<span id="amdgpu-memory-scopes"></span><h3><a class="toc-backref" href="#id54">Memory Scopes</a><a class="headerlink" href="#memory-scopes" title="Permalink to this headline">¶</a></h3>
+<p>This section provides LLVM memory synchronization scopes supported by the AMDGPU
+backend memory model when the target triple OS is <code class="docutils literal notranslate"><span class="pre">amdhsa</span></code> (see
+<a class="reference internal" href="#amdgpu-amdhsa-memory-model"><span class="std std-ref">Memory Model</span></a> and <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>).</p>
+<p>The memory model supported is based on the HSA memory model <a class="reference internal" href="#hsa" id="id12">[HSA]</a> which is
+based in turn on HRF-indirect with scope inclusion <a class="reference internal" href="#hrf" id="id13">[HRF]</a>. The happens-before
+relation is transitive over the synchonizes-with relation independent of scope,
+and synchonizes-with allows the memory scope instances to be inclusive (see
+table <a class="reference internal" href="#amdgpu-amdhsa-llvm-sync-scopes-table"><span class="std std-ref">AMDHSA LLVM Sync Scopes</span></a>).</p>
+<p>This is different to the OpenCL <a class="reference internal" href="#id47" id="id14">[OpenCL]</a> memory model which does not have scope
+inclusion and requires the memory scopes to exactly match. However, this
+is conservatively correct for OpenCL.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-llvm-sync-scopes-table">
+<caption><span class="caption-text">AMDHSA LLVM Sync Scopes</span><a class="headerlink" href="#amdgpu-amdhsa-llvm-sync-scopes-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="31%" />
+<col width="69%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">LLVM Sync Scope</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><em>none</em></td>
+<td><p class="first">The default: <code class="docutils literal notranslate"><span class="pre">system</span></code>.</p>
+<p>Synchronizes with, and participates in modification
+and seq_cst total orderings with, other operations
+(except image operations) for all address spaces
+(except private, or generic that accesses private)
+provided the other operationâs sync scope is:</p>
+<ul class="last simple">
+<li><code class="docutils literal notranslate"><span class="pre">system</span></code>.</li>
+<li><code class="docutils literal notranslate"><span class="pre">agent</span></code> and executed by a thread on the same
+agent.</li>
+<li><code class="docutils literal notranslate"><span class="pre">workgroup</span></code> and executed by a thread in the
+same workgroup.</li>
+<li><code class="docutils literal notranslate"><span class="pre">wavefront</span></code> and executed by a thread in the
+same wavefront.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">agent</span></code></td>
+<td><p class="first">Synchronizes with, and participates in modification
+and seq_cst total orderings with, other operations
+(except image operations) for all address spaces
+(except private, or generic that accesses private)
+provided the other operationâs sync scope is:</p>
+<ul class="last simple">
+<li><code class="docutils literal notranslate"><span class="pre">system</span></code> or <code class="docutils literal notranslate"><span class="pre">agent</span></code> and executed by a thread
+on the same agent.</li>
+<li><code class="docutils literal notranslate"><span class="pre">workgroup</span></code> and executed by a thread in the
+same workgroup.</li>
+<li><code class="docutils literal notranslate"><span class="pre">wavefront</span></code> and executed by a thread in the
+same wavefront.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">workgroup</span></code></td>
+<td><p class="first">Synchronizes with, and participates in modification
+and seq_cst total orderings with, other operations
+(except image operations) for all address spaces
+(except private, or generic that accesses private)
+provided the other operationâs sync scope is:</p>
+<ul class="last simple">
+<li><code class="docutils literal notranslate"><span class="pre">system</span></code>, <code class="docutils literal notranslate"><span class="pre">agent</span></code> or <code class="docutils literal notranslate"><span class="pre">workgroup</span></code> and
+executed by a thread in the same workgroup.</li>
+<li><code class="docutils literal notranslate"><span class="pre">wavefront</span></code> and executed by a thread in the
+same wavefront.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">wavefront</span></code></td>
+<td><p class="first">Synchronizes with, and participates in modification
+and seq_cst total orderings with, other operations
+(except image operations) for all address spaces
+(except private, or generic that accesses private)
+provided the other operationâs sync scope is:</p>
+<ul class="last simple">
+<li><code class="docutils literal notranslate"><span class="pre">system</span></code>, <code class="docutils literal notranslate"><span class="pre">agent</span></code>, <code class="docutils literal notranslate"><span class="pre">workgroup</span></code> or
+<code class="docutils literal notranslate"><span class="pre">wavefront</span></code> and executed by a thread in the
+same wavefront.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">singlethread</span></code></td>
+<td>Only synchronizes with, and participates in
+modification and seq_cst total orderings with,
+other operations (except image operations) running
+in the same thread for all address spaces (for
+example, in signal handlers).</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">one-as</span></code></td>
+<td>Same as <code class="docutils literal notranslate"><span class="pre">system</span></code> but only synchronizes with other
+operations within the same address space.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">agent-one-as</span></code></td>
+<td>Same as <code class="docutils literal notranslate"><span class="pre">agent</span></code> but only synchronizes with other
+operations within the same address space.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">workgroup-one-as</span></code></td>
+<td>Same as <code class="docutils literal notranslate"><span class="pre">workgroup</span></code> but only synchronizes with
+other operations within the same address space.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">wavefront-one-as</span></code></td>
+<td>Same as <code class="docutils literal notranslate"><span class="pre">wavefront</span></code> but only synchronizes with
+other operations within the same address space.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">singlethread-one-as</span></code></td>
+<td>Same as <code class="docutils literal notranslate"><span class="pre">singlethread</span></code> but only synchronizes with
+other operations within the same address space.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="amdgpu-intrinsics">
+<h3><a class="toc-backref" href="#id55">AMDGPU Intrinsics</a><a class="headerlink" href="#amdgpu-intrinsics" title="Permalink to this headline">¶</a></h3>
+<p>The AMDGPU backend implements the following LLVM IR intrinsics.</p>
+<p><em>This section is WIP.</em></p>
+</div>
+<div class="section" id="amdgpu-attributes">
+<h3><a class="toc-backref" href="#id56">AMDGPU Attributes</a><a class="headerlink" href="#amdgpu-attributes" title="Permalink to this headline">¶</a></h3>
+<p>The AMDGPU backend supports the following LLVM IR attributes.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-llvm-ir-attributes-table">
+<caption><span class="caption-text">AMDGPU LLVM IR Attributes</span><a class="headerlink" href="#amdgpu-llvm-ir-attributes-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="36%" />
+<col width="64%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">LLVM Attribute</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>âamdgpu-flat-work-group-sizeâ=âmin,maxâ</td>
+<td>Specify the minimum and maximum flat work group sizes that
+will be specified when the kernel is dispatched. Generated
+by the <code class="docutils literal notranslate"><span class="pre">amdgpu_flat_work_group_size</span></code> CLANG attribute <a class="reference internal" href="#clang-attr" id="id15">[CLANG-ATTR]</a>.</td>
+</tr>
+<tr class="row-odd"><td>âamdgpu-implicitarg-num-bytesâ=ânâ</td>
+<td>Number of kernel argument bytes to add to the kernel
+argument block size for the implicit arguments. This
+varies by OS and language (for OpenCL see
+<a class="reference internal" href="#opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table"><span class="std std-ref">OpenCL kernel implicit arguments appended for AMDHSA OS</span></a>).</td>
+</tr>
+<tr class="row-even"><td>âamdgpu-num-sgprâ=ânâ</td>
+<td>Specifies the number of SGPRs to use. Generated by
+the <code class="docutils literal notranslate"><span class="pre">amdgpu_num_sgpr</span></code> CLANG attribute <a class="reference internal" href="#clang-attr" id="id16">[CLANG-ATTR]</a>.</td>
+</tr>
+<tr class="row-odd"><td>âamdgpu-num-vgprâ=ânâ</td>
+<td>Specifies the number of VGPRs to use. Generated by the
+<code class="docutils literal notranslate"><span class="pre">amdgpu_num_vgpr</span></code> CLANG attribute <a class="reference internal" href="#clang-attr" id="id17">[CLANG-ATTR]</a>.</td>
+</tr>
+<tr class="row-even"><td>âamdgpu-waves-per-euâ=âm,nâ</td>
+<td>Specify the minimum and maximum number of waves per
+execution unit. Generated by the <code class="docutils literal notranslate"><span class="pre">amdgpu_waves_per_eu</span></code>
+CLANG attribute <a class="reference internal" href="#clang-attr" id="id18">[CLANG-ATTR]</a>.</td>
+</tr>
+<tr class="row-odd"><td>âamdgpu-ieeeâ true/false.</td>
+<td>Specify whether the function expects the IEEE field of the
+mode register to be set on entry. Overrides the default for
+the calling convention.</td>
+</tr>
+<tr class="row-even"><td>âamdgpu-dx10-clampâ true/false.</td>
+<td>Specify whether the function expects the DX10_CLAMP field of
+the mode register to be set on entry. Overrides the default
+for the calling convention.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="code-object">
+<h2><a class="toc-backref" href="#id57">Code Object</a><a class="headerlink" href="#code-object" title="Permalink to this headline">¶</a></h2>
+<p>The AMDGPU backend generates a standard ELF <a class="reference internal" href="#elf" id="id19">[ELF]</a> relocatable code object that
+can be linked by <code class="docutils literal notranslate"><span class="pre">lld</span></code> to produce a standard ELF shared code object which can
+be loaded and executed on an AMDGPU target.</p>
+<div class="section" id="header">
+<h3><a class="toc-backref" href="#id58">Header</a><a class="headerlink" href="#header" title="Permalink to this headline">¶</a></h3>
+<p>The AMDGPU backend uses the following ELF header:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-header-table">
+<caption><span class="caption-text">AMDGPU ELF Header</span><a class="headerlink" href="#amdgpu-elf-header-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="38%" />
+<col width="62%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Field</th>
+<th class="head">Value</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">e_ident[EI_CLASS]</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">ELFCLASS64</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">e_ident[EI_DATA]</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">ELFDATA2LSB</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">e_ident[EI_OSABI]</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">ELFOSABI_NONE</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_HSA</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_PAL</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_MESA3D</span></code></li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">e_ident[EI_ABIVERSION]</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_HSA</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_PAL</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_MESA3D</span></code></li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">e_type</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">ET_REL</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">ET_DYN</span></code></li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">e_machine</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">EM_AMDGPU</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">e_entry</span></code></td>
+<td>0</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">e_flags</span></code></td>
+<td>See <a class="reference internal" href="#amdgpu-elf-header-e-flags-table"><span class="std std-ref">AMDGPU ELF Header e_flags</span></a></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-header-enumeration-values-table">
+<caption><span class="caption-text">AMDGPU ELF Header Enumeration Values</span><a class="headerlink" href="#amdgpu-elf-header-enumeration-values-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="86%" />
+<col width="14%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Value</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EM_AMDGPU</span></code></td>
+<td>224</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">ELFOSABI_NONE</span></code></td>
+<td>0</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_HSA</span></code></td>
+<td>64</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_PAL</span></code></td>
+<td>65</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_MESA3D</span></code></td>
+<td>66</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_HSA</span></code></td>
+<td>1</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_PAL</span></code></td>
+<td>0</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_MESA3D</span></code></td>
+<td>0</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<dl class="docutils">
+<dt><code class="docutils literal notranslate"><span class="pre">e_ident[EI_CLASS]</span></code></dt>
+<dd><p class="first">The ELF class is:</p>
+<ul class="last simple">
+<li><code class="docutils literal notranslate"><span class="pre">ELFCLASS32</span></code> for <code class="docutils literal notranslate"><span class="pre">r600</span></code> architecture.</li>
+<li><code class="docutils literal notranslate"><span class="pre">ELFCLASS64</span></code> for <code class="docutils literal notranslate"><span class="pre">amdgcn</span></code> architecture which only supports 64
+bit applications.</li>
+</ul>
+</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">e_ident[EI_DATA]</span></code></dt>
+<dd>All AMDGPU targets use <code class="docutils literal notranslate"><span class="pre">ELFDATA2LSB</span></code> for little-endian byte ordering.</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">e_ident[EI_OSABI]</span></code></dt>
+<dd><p class="first">One of the following AMD GPU architecture specific OS ABIs
+(see <a class="reference internal" href="#amdgpu-os-table"><span class="std std-ref">AMDGPU Operating Systems</span></a>):</p>
+<ul class="last simple">
+<li><code class="docutils literal notranslate"><span class="pre">ELFOSABI_NONE</span></code> for <em>unknown</em> OS.</li>
+<li><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_HSA</span></code> for <code class="docutils literal notranslate"><span class="pre">amdhsa</span></code> OS.</li>
+<li><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_PAL</span></code> for <code class="docutils literal notranslate"><span class="pre">amdpal</span></code> OS.</li>
+<li><code class="docutils literal notranslate"><span class="pre">ELFOSABI_AMDGPU_MESA3D</span></code> for <code class="docutils literal notranslate"><span class="pre">mesa3D</span></code> OS.</li>
+</ul>
+</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">e_ident[EI_ABIVERSION]</span></code></dt>
+<dd><p class="first">The ABI version of the AMD GPU architecture specific OS ABI to which the code
+object conforms:</p>
+<ul class="last simple">
+<li><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_HSA</span></code> is used to specify the version of AMD HSA
+runtime ABI.</li>
+<li><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_PAL</span></code> is used to specify the version of AMD PAL
+runtime ABI.</li>
+<li><code class="docutils literal notranslate"><span class="pre">ELFABIVERSION_AMDGPU_MESA3D</span></code> is used to specify the version of AMD MESA
+3D runtime ABI.</li>
+</ul>
+</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">e_type</span></code></dt>
+<dd><p class="first">Can be one of the following values:</p>
+<dl class="docutils">
+<dt><code class="docutils literal notranslate"><span class="pre">ET_REL</span></code></dt>
+<dd>The type produced by the AMD GPU backend compiler as it is relocatable code
+object.</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">ET_DYN</span></code></dt>
+<dd>The type produced by the linker as it is a shared code object.</dd>
+</dl>
+<p class="last">The AMD HSA runtime loader requires a <code class="docutils literal notranslate"><span class="pre">ET_DYN</span></code> code object.</p>
+</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">e_machine</span></code></dt>
+<dd>The value <code class="docutils literal notranslate"><span class="pre">EM_AMDGPU</span></code> is used for the machine for all processors supported
+by the <code class="docutils literal notranslate"><span class="pre">r600</span></code> and <code class="docutils literal notranslate"><span class="pre">amdgcn</span></code> architectures (see
+<a class="reference internal" href="#amdgpu-processor-table"><span class="std std-ref">AMDGPU Processors</span></a>). The specific processor is specified in the
+<code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH</span></code> bit field of the <code class="docutils literal notranslate"><span class="pre">e_flags</span></code> (see
+<a class="reference internal" href="#amdgpu-elf-header-e-flags-table"><span class="std std-ref">AMDGPU ELF Header e_flags</span></a>).</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">e_entry</span></code></dt>
+<dd>The entry point is 0 as the entry points for individual kernels must be
+selected in order to invoke them through AQL packets.</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">e_flags</span></code></dt>
+<dd><p class="first">The AMDGPU backend uses the following ELF header flags:</p>
+<table border="1" class="docutils" id="amdgpu-elf-header-e-flags-table">
+<caption><span class="caption-text">AMDGPU ELF Header <code class="docutils literal notranslate"><span class="pre">e_flags</span></code></span><a class="headerlink" href="#amdgpu-elf-header-e-flags-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="42%" />
+<col width="13%" />
+<col width="45%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Value</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td colspan="2"><strong>AMDGPU Processor Flag</strong></td>
+<td>See <a class="reference internal" href="#amdgpu-processor-table"><span class="std std-ref">AMDGPU Processors</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH</span></code></td>
+<td>0x000000ff</td>
+<td>AMDGPU processor selection
+mask for
+<code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_xxx</span></code> values
+defined in
+<a class="reference internal" href="#amdgpu-ef-amdgpu-mach-table"><span class="std std-ref">AMDGPU EF_AMDGPU_MACH Values</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_XNACK</span></code></td>
+<td>0x00000100</td>
+<td>Indicates if the <code class="docutils literal notranslate"><span class="pre">xnack</span></code>
+target feature is
+enabled for all code
+contained in the code object.
+If the processor
+does not support the
+<code class="docutils literal notranslate"><span class="pre">xnack</span></code> target
+feature then must
+be 0.
+See
+<a class="reference internal" href="#amdgpu-target-features"><span class="std std-ref">Target Features</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_SRAM_ECC</span></code></td>
+<td>0x00000200</td>
+<td>Indicates if the <code class="docutils literal notranslate"><span class="pre">sram-ecc</span></code>
+target feature is
+enabled for all code
+contained in the code object.
+If the processor
+does not support the
+<code class="docutils literal notranslate"><span class="pre">sram-ecc</span></code> target
+feature then must
+be 0.
+See
+<a class="reference internal" href="#amdgpu-target-features"><span class="std std-ref">Target Features</span></a>.</td>
+</tr>
+</tbody>
+</table>
+<table border="1" class="last docutils" id="amdgpu-ef-amdgpu-mach-table">
+<caption><span class="caption-text">AMDGPU <code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH</span></code> Values</span><a class="headerlink" href="#amdgpu-ef-amdgpu-mach-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="45%" />
+<col width="14%" />
+<col width="41%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Value</th>
+<th class="head">Description (see
+<a class="reference internal" href="#amdgpu-processor-table"><span class="std std-ref">AMDGPU Processors</span></a>)</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_NONE</span></code></td>
+<td>0x000</td>
+<td><em>not specified</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_R600</span></code></td>
+<td>0x001</td>
+<td><code class="docutils literal notranslate"><span class="pre">r600</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_R630</span></code></td>
+<td>0x002</td>
+<td><code class="docutils literal notranslate"><span class="pre">r630</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_RS880</span></code></td>
+<td>0x003</td>
+<td><code class="docutils literal notranslate"><span class="pre">rs880</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_RV670</span></code></td>
+<td>0x004</td>
+<td><code class="docutils literal notranslate"><span class="pre">rv670</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_RV710</span></code></td>
+<td>0x005</td>
+<td><code class="docutils literal notranslate"><span class="pre">rv710</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_RV730</span></code></td>
+<td>0x006</td>
+<td><code class="docutils literal notranslate"><span class="pre">rv730</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_RV770</span></code></td>
+<td>0x007</td>
+<td><code class="docutils literal notranslate"><span class="pre">rv770</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_CEDAR</span></code></td>
+<td>0x008</td>
+<td><code class="docutils literal notranslate"><span class="pre">cedar</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_CYPRESS</span></code></td>
+<td>0x009</td>
+<td><code class="docutils literal notranslate"><span class="pre">cypress</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_JUNIPER</span></code></td>
+<td>0x00a</td>
+<td><code class="docutils literal notranslate"><span class="pre">juniper</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_REDWOOD</span></code></td>
+<td>0x00b</td>
+<td><code class="docutils literal notranslate"><span class="pre">redwood</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_SUMO</span></code></td>
+<td>0x00c</td>
+<td><code class="docutils literal notranslate"><span class="pre">sumo</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_BARTS</span></code></td>
+<td>0x00d</td>
+<td><code class="docutils literal notranslate"><span class="pre">barts</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_CAICOS</span></code></td>
+<td>0x00e</td>
+<td><code class="docutils literal notranslate"><span class="pre">caicos</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_CAYMAN</span></code></td>
+<td>0x00f</td>
+<td><code class="docutils literal notranslate"><span class="pre">cayman</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_R600_TURKS</span></code></td>
+<td>0x010</td>
+<td><code class="docutils literal notranslate"><span class="pre">turks</span></code></td>
+</tr>
+<tr class="row-odd"><td><em>reserved</em></td>
+<td>0x011 -
+0x01f</td>
+<td>Reserved for <code class="docutils literal notranslate"><span class="pre">r600</span></code>
+architecture processors.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX600</span></code></td>
+<td>0x020</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx600</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX601</span></code></td>
+<td>0x021</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx601</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX700</span></code></td>
+<td>0x022</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx700</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX701</span></code></td>
+<td>0x023</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx701</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX702</span></code></td>
+<td>0x024</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx702</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX703</span></code></td>
+<td>0x025</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx703</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX704</span></code></td>
+<td>0x026</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx704</span></code></td>
+</tr>
+<tr class="row-odd"><td><em>reserved</em></td>
+<td>0x027</td>
+<td>Reserved.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX801</span></code></td>
+<td>0x028</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx801</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX802</span></code></td>
+<td>0x029</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx802</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX803</span></code></td>
+<td>0x02a</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx803</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX810</span></code></td>
+<td>0x02b</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx810</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX900</span></code></td>
+<td>0x02c</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx900</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX902</span></code></td>
+<td>0x02d</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx902</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX904</span></code></td>
+<td>0x02e</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx904</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX906</span></code></td>
+<td>0x02f</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx906</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX908</span></code></td>
+<td>0x030</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx908</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX909</span></code></td>
+<td>0x031</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx909</span></code></td>
+</tr>
+<tr class="row-even"><td><em>reserved</em></td>
+<td>0x032</td>
+<td>Reserved.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX1010</span></code></td>
+<td>0x033</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx1010</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX1011</span></code></td>
+<td>0x034</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx1011</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">EF_AMDGPU_MACH_AMDGCN_GFX1012</span></code></td>
+<td>0x035</td>
+<td><code class="docutils literal notranslate"><span class="pre">gfx1012</span></code></td>
+</tr>
+</tbody>
+</table>
+</dd>
+</dl>
+</div>
+<div class="section" id="sections">
+<h3><a class="toc-backref" href="#id59">Sections</a><a class="headerlink" href="#sections" title="Permalink to this headline">¶</a></h3>
+<p>An AMDGPU target ELF code object has the standard ELF sections which include:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-sections-table">
+<caption><span class="caption-text">AMDGPU ELF Sections</span><a class="headerlink" href="#amdgpu-elf-sections-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="27%" />
+<col width="24%" />
+<col width="49%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Type</th>
+<th class="head">Attributes</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.bss</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_NOBITS</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code> + <code class="docutils literal notranslate"><span class="pre">SHF_WRITE</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.data</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_PROGBITS</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code> + <code class="docutils literal notranslate"><span class="pre">SHF_WRITE</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.debug_</span></code><em>*</em></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_PROGBITS</span></code></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.dynamic</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_DYNAMIC</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.dynstr</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_PROGBITS</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.dynsym</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_PROGBITS</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.got</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_PROGBITS</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code> + <code class="docutils literal notranslate"><span class="pre">SHF_WRITE</span></code></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.hash</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_HASH</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.note</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_NOTE</span></code></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.rela</span></code><em>name</em></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_RELA</span></code></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.rela.dyn</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_RELA</span></code></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.rodata</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_PROGBITS</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.shstrtab</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_STRTAB</span></code></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.strtab</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_STRTAB</span></code></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.symtab</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_SYMTAB</span></code></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.text</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHT_PROGBITS</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">SHF_ALLOC</span></code> + <code class="docutils literal notranslate"><span class="pre">SHF_EXECINSTR</span></code></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>These sections have their standard meanings (see <a class="reference internal" href="#elf" id="id20">[ELF]</a>) and are only generated
+if needed.</p>
+<dl class="docutils">
+<dt><code class="docutils literal notranslate"><span class="pre">.debug</span></code><em>*</em></dt>
+<dd>The standard DWARF sections. See <a class="reference internal" href="#amdgpu-dwarf"><span class="std std-ref">DWARF</span></a> for information on the
+DWARF produced by the AMDGPU backend.</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">.dynamic</span></code>, <code class="docutils literal notranslate"><span class="pre">.dynstr</span></code>, <code class="docutils literal notranslate"><span class="pre">.dynsym</span></code>, <code class="docutils literal notranslate"><span class="pre">.hash</span></code></dt>
+<dd>The standard sections used by a dynamic loader.</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">.note</span></code></dt>
+<dd>See <a class="reference internal" href="#amdgpu-note-records"><span class="std std-ref">Note Records</span></a> for the note records supported by the AMDGPU
+backend.</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">.rela</span></code><em>name</em>, <code class="docutils literal notranslate"><span class="pre">.rela.dyn</span></code></dt>
+<dd><p class="first">For relocatable code objects, <em>name</em> is the name of the section that the
+relocation records apply. For example, <code class="docutils literal notranslate"><span class="pre">.rela.text</span></code> is the section name for
+relocation records associated with the <code class="docutils literal notranslate"><span class="pre">.text</span></code> section.</p>
+<p>For linked shared code objects, <code class="docutils literal notranslate"><span class="pre">.rela.dyn</span></code> contains all the relocation
+records from each of the relocatable code objectâs <code class="docutils literal notranslate"><span class="pre">.rela</span></code><em>name</em> sections.</p>
+<p class="last">See <a class="reference internal" href="#amdgpu-relocation-records"><span class="std std-ref">Relocation Records</span></a> for the relocation records supported by
+the AMDGPU backend.</p>
+</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">.text</span></code></dt>
+<dd>The executable machine code for the kernels and functions they call. Generated
+as position independent code. See <a class="reference internal" href="#amdgpu-code-conventions"><span class="std std-ref">Code Conventions</span></a> for
+information on conventions used in the isa generation.</dd>
+</dl>
+</div>
+<div class="section" id="note-records">
+<span id="amdgpu-note-records"></span><h3><a class="toc-backref" href="#id60">Note Records</a><a class="headerlink" href="#note-records" title="Permalink to this headline">¶</a></h3>
+<p>The AMDGPU backend code object contains ELF note records in the <code class="docutils literal notranslate"><span class="pre">.note</span></code>
+section. The set of generated notes and their semantics depend on the code
+object version; see <a class="reference internal" href="#amdgpu-note-records-v2"><span class="std std-ref">Code Object V2 Note Records (-mattr=-code-object-v3)</span></a> and
+<a class="reference internal" href="#amdgpu-note-records-v3"><span class="std std-ref">Code Object V3 Note Records (-mattr=+code-object-v3)</span></a>.</p>
+<p>As required by <code class="docutils literal notranslate"><span class="pre">ELFCLASS32</span></code> and <code class="docutils literal notranslate"><span class="pre">ELFCLASS64</span></code>, minimal zero byte padding
+must be generated after the <code class="docutils literal notranslate"><span class="pre">name</span></code> field to ensure the <code class="docutils literal notranslate"><span class="pre">desc</span></code> field is 4
+byte aligned. In addition, minimal zero byte padding must be generated to
+ensure the <code class="docutils literal notranslate"><span class="pre">desc</span></code> field size is a multiple of 4 bytes. The <code class="docutils literal notranslate"><span class="pre">sh_addralign</span></code>
+field of the <code class="docutils literal notranslate"><span class="pre">.note</span></code> section must be at least 4 to indicate at least 8 byte
+alignment.</p>
+<div class="section" id="code-object-v2-note-records-mattr-code-object-v3">
+<span id="amdgpu-note-records-v2"></span><h4><a class="toc-backref" href="#id61">Code Object V2 Note Records (-mattr=-code-object-v3)</a><a class="headerlink" href="#code-object-v2-note-records-mattr-code-object-v3" title="Permalink to this headline">¶</a></h4>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">Code Object V2 is not the default code object version emitted by
+this version of LLVM. For a description of the notes generated with the
+default configuration (Code Object V3) see <a class="reference internal" href="#amdgpu-note-records-v3"><span class="std std-ref">Code Object V3 Note Records (-mattr=+code-object-v3)</span></a>.</p>
+</div>
+<p>The AMDGPU backend code object uses the following ELF note record in the
+<code class="docutils literal notranslate"><span class="pre">.note</span></code> section when compiling for Code Object V2 (-mattr=-code-object-v3).</p>
+<p>Additional note records may be present, but any which are not documented here
+are deprecated and should not be used.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-note-records-table-v2">
+<caption><span class="caption-text">AMDGPU Code Object V2 ELF Note Records</span><a class="headerlink" href="#amdgpu-elf-note-records-table-v2" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="7%" />
+<col width="41%" />
+<col width="52%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>âAMDâ</td>
+<td><code class="docutils literal notranslate"><span class="pre">NT_AMD_AMDGPU_HSA_METADATA</span></code></td>
+<td><metadata null terminated string></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-note-record-enumeration-values-table-v2">
+<caption><span class="caption-text">AMDGPU Code Object V2 ELF Note Record Enumeration Values</span><a class="headerlink" href="#amdgpu-elf-note-record-enumeration-values-table-v2" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="86%" />
+<col width="14%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Value</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><em>reserved</em></td>
+<td>0-9</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">NT_AMD_AMDGPU_HSA_METADATA</span></code></td>
+<td>10</td>
+</tr>
+<tr class="row-even"><td><em>reserved</em></td>
+<td>11</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<dl class="docutils">
+<dt><code class="docutils literal notranslate"><span class="pre">NT_AMD_AMDGPU_HSA_METADATA</span></code></dt>
+<dd>Specifies extensible metadata associated with the code objects executed on HSA
+<a class="reference internal" href="#hsa" id="id21">[HSA]</a> compatible runtimes such as AMDâs ROCm <a class="reference internal" href="#amd-rocm" id="id22">[AMD-ROCm]</a>. It is required when
+the target triple OS is <code class="docutils literal notranslate"><span class="pre">amdhsa</span></code> (see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>). See
+<a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata-v2"><span class="std std-ref">Code Object V2 Metadata (-mattr=-code-object-v3)</span></a> for the syntax of the code
+object metadata string.</dd>
+</dl>
+</div>
+<div class="section" id="code-object-v3-note-records-mattr-code-object-v3">
+<span id="amdgpu-note-records-v3"></span><h4><a class="toc-backref" href="#id62">Code Object V3 Note Records (-mattr=+code-object-v3)</a><a class="headerlink" href="#code-object-v3-note-records-mattr-code-object-v3" title="Permalink to this headline">¶</a></h4>
+<p>The AMDGPU backend code object uses the following ELF note record in the
+<code class="docutils literal notranslate"><span class="pre">.note</span></code> section when compiling for Code Object V3 (-mattr=+code-object-v3).</p>
+<p>Additional note records may be present, but any which are not documented here
+are deprecated and should not be used.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-note-records-table-v3">
+<caption><span class="caption-text">AMDGPU Code Object V3 ELF Note Records</span><a class="headerlink" href="#amdgpu-elf-note-records-table-v3" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="11%" />
+<col width="39%" />
+<col width="50%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Type</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>âAMDGPUâ</td>
+<td><code class="docutils literal notranslate"><span class="pre">NT_AMDGPU_METADATA</span></code></td>
+<td>Metadata in Message Pack <a class="reference internal" href="#msgpack" id="id23">[MsgPack]</a>
+binary format.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-note-record-enumeration-values-table-v3">
+<caption><span class="caption-text">AMDGPU Code Object V3 ELF Note Record Enumeration Values</span><a class="headerlink" href="#amdgpu-elf-note-record-enumeration-values-table-v3" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="86%" />
+<col width="14%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Value</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><em>reserved</em></td>
+<td>0-31</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">NT_AMDGPU_METADATA</span></code></td>
+<td>32</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<dl class="docutils">
+<dt><code class="docutils literal notranslate"><span class="pre">NT_AMDGPU_METADATA</span></code></dt>
+<dd>Specifies extensible metadata associated with an AMDGPU code
+object. It is encoded as a map in the Message Pack <a class="reference internal" href="#msgpack" id="id24">[MsgPack]</a> binary
+data format. See <a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata-v3"><span class="std std-ref">Code Object V3 Metadata (-mattr=+code-object-v3)</span></a> for the
+map keys defined for the <code class="docutils literal notranslate"><span class="pre">amdhsa</span></code> OS.</dd>
+</dl>
+</div>
+</div>
+<div class="section" id="symbols">
+<span id="amdgpu-symbols"></span><h3><a class="toc-backref" href="#id63">Symbols</a><a class="headerlink" href="#symbols" title="Permalink to this headline">¶</a></h3>
+<p>Symbols include the following:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-symbols-table">
+<caption><span class="caption-text">AMDGPU ELF Symbols</span><a class="headerlink" href="#amdgpu-elf-symbols-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="27%" />
+<col width="23%" />
+<col width="21%" />
+<col width="29%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Name</th>
+<th class="head">Type</th>
+<th class="head">Section</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><em>link-name</em></td>
+<td><code class="docutils literal notranslate"><span class="pre">STT_OBJECT</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">.data</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">.rodata</span></code></li>
+<li><code class="docutils literal notranslate"><span class="pre">.bss</span></code></li>
+</ul>
+</td>
+<td>Global variable</td>
+</tr>
+<tr class="row-odd"><td><em>link-name</em><code class="docutils literal notranslate"><span class="pre">.kd</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">STT_OBJECT</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">.rodata</span></code></li>
+</ul>
+</td>
+<td>Kernel descriptor</td>
+</tr>
+<tr class="row-even"><td><em>link-name</em></td>
+<td><code class="docutils literal notranslate"><span class="pre">STT_FUNC</span></code></td>
+<td><ul class="first last simple">
+<li><code class="docutils literal notranslate"><span class="pre">.text</span></code></li>
+</ul>
+</td>
+<td>Kernel entry point</td>
+</tr>
+<tr class="row-odd"><td><em>link-name</em></td>
+<td><code class="docutils literal notranslate"><span class="pre">STT_OBJECT</span></code></td>
+<td><ul class="first last simple">
+<li>SHN_AMDGPU_LDS</li>
+</ul>
+</td>
+<td>Global variable in LDS</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<dl class="docutils">
+<dt>Global variable</dt>
+<dd><p class="first">Global variables both used and defined by the compilation unit.</p>
+<p>If the symbol is defined in the compilation unit then it is allocated in the
+appropriate section according to if it has initialized data or is readonly.</p>
+<p>If the symbol is external then its section is <code class="docutils literal notranslate"><span class="pre">STN_UNDEF</span></code> and the loader
+will resolve relocations using the definition provided by another code object
+or explicitly defined by the runtime.</p>
+<p class="last">If the symbol resides in local/group memory (LDS) then its section is the
+special processor-specific section name <code class="docutils literal notranslate"><span class="pre">SHN_AMDGPU_LDS</span></code>, and the
+<code class="docutils literal notranslate"><span class="pre">st_value</span></code> field describes alignment requirements as it does for common
+symbols.</p>
+</dd>
+<dt>Kernel descriptor</dt>
+<dd>Every HSA kernel has an associated kernel descriptor. It is the address of the
+kernel descriptor that is used in the AQL dispatch packet used to invoke the
+kernel, not the kernel entry point. The layout of the HSA kernel descriptor is
+defined in <a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>.</dd>
+<dt>Kernel entry point</dt>
+<dd>Every HSA kernel also has a symbol for its machine code entry point.</dd>
+</dl>
+</div>
+<div class="section" id="relocation-records">
+<span id="amdgpu-relocation-records"></span><h3><a class="toc-backref" href="#id64">Relocation Records</a><a class="headerlink" href="#relocation-records" title="Permalink to this headline">¶</a></h3>
+<p>AMDGPU backend generates <code class="docutils literal notranslate"><span class="pre">Elf64_Rela</span></code> relocation records. Supported
+relocatable fields are:</p>
+<dl class="docutils">
+<dt><code class="docutils literal notranslate"><span class="pre">word32</span></code></dt>
+<dd>This specifies a 32-bit field occupying 4 bytes with arbitrary byte
+alignment. These values use the same byte order as other word values in the
+AMD GPU architecture.</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">word64</span></code></dt>
+<dd>This specifies a 64-bit field occupying 8 bytes with arbitrary byte
+alignment. These values use the same byte order as other word values in the
+AMD GPU architecture.</dd>
+</dl>
+<p>Following notations are used for specifying relocation calculations:</p>
+<dl class="docutils">
+<dt><strong>A</strong></dt>
+<dd>Represents the addend used to compute the value of the relocatable field.</dd>
+<dt><strong>G</strong></dt>
+<dd>Represents the offset into the global offset table at which the relocation
+entryâs symbol will reside during execution.</dd>
+<dt><strong>GOT</strong></dt>
+<dd>Represents the address of the global offset table.</dd>
+<dt><strong>P</strong></dt>
+<dd>Represents the place (section offset for <code class="docutils literal notranslate"><span class="pre">et_rel</span></code> or address for <code class="docutils literal notranslate"><span class="pre">et_dyn</span></code>)
+of the storage unit being relocated (computed using <code class="docutils literal notranslate"><span class="pre">r_offset</span></code>).</dd>
+<dt><strong>S</strong></dt>
+<dd>Represents the value of the symbol whose index resides in the relocation
+entry. Relocations not using this must specify a symbol index of <code class="docutils literal notranslate"><span class="pre">STN_UNDEF</span></code>.</dd>
+<dt><strong>B</strong></dt>
+<dd>Represents the base address of a loaded executable or shared object which is
+the difference between the ELF address and the actual load address. Relocations
+using this are only valid in executable or shared objects.</dd>
+</dl>
+<p>The following relocation types are supported:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-elf-relocation-records-table">
+<caption><span class="caption-text">AMDGPU ELF Relocation Records</span><a class="headerlink" href="#amdgpu-elf-relocation-records-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="33%" />
+<col width="9%" />
+<col width="6%" />
+<col width="13%" />
+<col width="38%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Relocation Type</th>
+<th class="head">Kind</th>
+<th class="head">Value</th>
+<th class="head">Field</th>
+<th class="head">Calculation</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_NONE</span></code></td>
+<td> </td>
+<td>0</td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_ABS32_LO</span></code></td>
+<td>Static,
+Dynamic</td>
+<td>1</td>
+<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
+<td>(S + A) & 0xFFFFFFFF</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_ABS32_HI</span></code></td>
+<td>Static,
+Dynamic</td>
+<td>2</td>
+<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
+<td>(S + A) >> 32</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_ABS64</span></code></td>
+<td>Static,
+Dynamic</td>
+<td>3</td>
+<td><code class="docutils literal notranslate"><span class="pre">word64</span></code></td>
+<td>S + A</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_REL32</span></code></td>
+<td>Static</td>
+<td>4</td>
+<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
+<td>S + A - P</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_REL64</span></code></td>
+<td>Static</td>
+<td>5</td>
+<td><code class="docutils literal notranslate"><span class="pre">word64</span></code></td>
+<td>S + A - P</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_ABS32</span></code></td>
+<td>Static,
+Dynamic</td>
+<td>6</td>
+<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
+<td>S + A</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_GOTPCREL</span></code></td>
+<td>Static</td>
+<td>7</td>
+<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
+<td>G + GOT + A - P</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_GOTPCREL32_LO</span></code></td>
+<td>Static</td>
+<td>8</td>
+<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
+<td>(G + GOT + A - P) & 0xFFFFFFFF</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_GOTPCREL32_HI</span></code></td>
+<td>Static</td>
+<td>9</td>
+<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
+<td>(G + GOT + A - P) >> 32</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_REL32_LO</span></code></td>
+<td>Static</td>
+<td>10</td>
+<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
+<td>(S + A - P) & 0xFFFFFFFF</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_REL32_HI</span></code></td>
+<td>Static</td>
+<td>11</td>
+<td><code class="docutils literal notranslate"><span class="pre">word32</span></code></td>
+<td>(S + A - P) >> 32</td>
+</tr>
+<tr class="row-even"><td><em>reserved</em></td>
+<td> </td>
+<td>12</td>
+<td> </td>
+<td> </td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_RELATIVE64</span></code></td>
+<td>Dynamic</td>
+<td>13</td>
+<td><code class="docutils literal notranslate"><span class="pre">word64</span></code></td>
+<td>B + A</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p><code class="docutils literal notranslate"><span class="pre">R_AMDGPU_ABS32_LO</span></code> and <code class="docutils literal notranslate"><span class="pre">R_AMDGPU_ABS32_HI</span></code> are only supported by
+the <code class="docutils literal notranslate"><span class="pre">mesa3d</span></code> OS, which does not support <code class="docutils literal notranslate"><span class="pre">R_AMDGPU_ABS64</span></code>.</p>
+<p>There is no current OS loader support for 32 bit programs and so
+<code class="docutils literal notranslate"><span class="pre">R_AMDGPU_ABS32</span></code> is not used.</p>
+</div>
+<div class="section" id="dwarf">
+<span id="amdgpu-dwarf"></span><h3><a class="toc-backref" href="#id65">DWARF</a><a class="headerlink" href="#dwarf" title="Permalink to this headline">¶</a></h3>
+<p>Standard DWARF <a class="reference internal" href="#id46" id="id25">[DWARF]</a> Version 5 sections can be generated. These contain
+information that maps the code object executable code and data to the source
+language constructs. It can be used by tools such as debuggers and profilers.</p>
+<div class="section" id="address-space-mapping">
+<h4><a class="toc-backref" href="#id66">Address Space Mapping</a><a class="headerlink" href="#address-space-mapping" title="Permalink to this headline">¶</a></h4>
+<p>The following address space mapping is used:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-dwarf-address-space-mapping-table">
+<caption><span class="caption-text">AMDGPU DWARF Address Space Mapping</span><a class="headerlink" href="#amdgpu-dwarf-address-space-mapping-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="53%" />
+<col width="47%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">DWARF Address Space</th>
+<th class="head">Memory Space</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>1</td>
+<td>Private (Scratch)</td>
+</tr>
+<tr class="row-odd"><td>2</td>
+<td>Local (group/LDS)</td>
+</tr>
+<tr class="row-even"><td><em>omitted</em></td>
+<td>Global</td>
+</tr>
+<tr class="row-odd"><td><em>omitted</em></td>
+<td>Constant</td>
+</tr>
+<tr class="row-even"><td><em>omitted</em></td>
+<td>Generic (Flat)</td>
+</tr>
+<tr class="row-odd"><td><em>not supported</em></td>
+<td>Region (GDS)</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>See <a class="reference internal" href="#amdgpu-address-spaces"><span class="std std-ref">Address Spaces</span></a> for information on the memory space terminology
+used in the table.</p>
+<p>An <code class="docutils literal notranslate"><span class="pre">address_class</span></code> attribute is generated on pointer type DIEs to specify the
+DWARF address space of the value of the pointer when it is in the <em>private</em> or
+<em>local</em> address space. Otherwise the attribute is omitted.</p>
+<p>An <code class="docutils literal notranslate"><span class="pre">XDEREF</span></code> operation is generated in location list expressions for variables
+that are allocated in the <em>private</em> and <em>local</em> address space. Otherwise no
+<code class="docutils literal notranslate"><span class="pre">XDREF</span></code> is omitted.</p>
+</div>
+<div class="section" id="register-mapping">
+<h4><a class="toc-backref" href="#id67">Register Mapping</a><a class="headerlink" href="#register-mapping" title="Permalink to this headline">¶</a></h4>
+<p><em>This section is WIP.</em></p>
+</div>
+<div class="section" id="source-text">
+<h4><a class="toc-backref" href="#id68">Source Text</a><a class="headerlink" href="#source-text" title="Permalink to this headline">¶</a></h4>
+<p>Source text for online-compiled programs (e.g. those compiled by the OpenCL
+runtime) may be embedded into the DWARF v5 line table using the <code class="docutils literal notranslate"><span class="pre">clang</span>
+<span class="pre">-gembed-source</span></code> option, described in table <a class="reference internal" href="#amdgpu-debug-options"><span class="std std-ref">AMDGPU Debug Options</span></a>.</p>
+<p>For example:</p>
+<dl class="docutils">
+<dt><code class="docutils literal notranslate"><span class="pre">-gembed-source</span></code></dt>
+<dd>Enable the embedded source DWARF v5 extension.</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">-gno-embed-source</span></code></dt>
+<dd><p class="first">Disable the embedded source DWARF v5 extension.</p>
+<table border="1" class="last docutils" id="amdgpu-debug-options">
+<caption><span class="caption-text">AMDGPU Debug Options</span><a class="headerlink" href="#amdgpu-debug-options" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="29%" />
+<col width="71%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Debug Flag</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>-g[no-]embed-source</td>
+<td>Enable/disable embedding source text in DWARF
+debug sections. Useful for environments where
+source cannot be written to disk, such as
+when performing online compilation.</td>
+</tr>
+</tbody>
+</table>
+</dd>
+</dl>
+<p>This option enables one extended content types in the DWARF v5 Line Number
+Program Header, which is used to encode embedded source.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-dwarf-extended-content-types">
+<caption><span class="caption-text">AMDGPU DWARF Line Number Program Header Extended Content Types</span><a class="headerlink" href="#amdgpu-dwarf-extended-content-types" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="56%" />
+<col width="44%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Content Type</th>
+<th class="head">Form</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">DW_LNCT_LLVM_source</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">DW_FORM_line_strp</span></code></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>The source field will contain the UTF-8 encoded, null-terminated source text
+with <code class="docutils literal notranslate"><span class="pre">'\n'</span></code> line endings. When the source field is present, consumers can use
+the embedded source instead of attempting to discover the source on disk. When
+the source field is absent, consumers can access the file to get the source
+text.</p>
+<p>The above content type appears in the <code class="docutils literal notranslate"><span class="pre">file_name_entry_format</span></code> field of the
+line table prologue, and its corresponding value appear in the <code class="docutils literal notranslate"><span class="pre">file_names</span></code>
+field. The current encoding of the content type is documented in table
+<a class="reference internal" href="#amdgpu-dwarf-extended-content-types-encoding"><span class="std std-ref">AMDGPU DWARF Line Number Program Header Extended Content Types Encoding</span></a></p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-dwarf-extended-content-types-encoding">
+<caption><span class="caption-text">AMDGPU DWARF Line Number Program Header Extended Content Types Encoding</span><a class="headerlink" href="#amdgpu-dwarf-extended-content-types-encoding" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="58%" />
+<col width="42%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Content Type</th>
+<th class="head">Value</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">DW_LNCT_LLVM_source</span></code></td>
+<td>0x2001</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+</div>
+<div class="section" id="code-conventions">
+<span id="amdgpu-code-conventions"></span><h2><a class="toc-backref" href="#id69">Code Conventions</a><a class="headerlink" href="#code-conventions" title="Permalink to this headline">¶</a></h2>
+<p>This section provides code conventions used for each supported target triple OS
+(see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>).</p>
+<div class="section" id="amdhsa">
+<h3><a class="toc-backref" href="#id70">AMDHSA</a><a class="headerlink" href="#amdhsa" title="Permalink to this headline">¶</a></h3>
+<p>This section provides code conventions used when the target triple OS is
+<code class="docutils literal notranslate"><span class="pre">amdhsa</span></code> (see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>).</p>
+<div class="section" id="code-object-target-identification">
+<span id="amdgpu-amdhsa-code-object-target-identification"></span><h4><a class="toc-backref" href="#id71">Code Object Target Identification</a><a class="headerlink" href="#code-object-target-identification" title="Permalink to this headline">¶</a></h4>
+<p>The AMDHSA OS uses the following syntax to specify the code object
+target as a single string:</p>
+<blockquote>
+<div><code class="docutils literal notranslate"><span class="pre"><Architecture>-<Vendor>-<OS>-<Environment>-<Processor><Target</span> <span class="pre">Features></span></code></div></blockquote>
+<p>Where:</p>
+<blockquote>
+<div><ul class="simple">
+<li><code class="docutils literal notranslate"><span class="pre"><Architecture></span></code>, <code class="docutils literal notranslate"><span class="pre"><Vendor></span></code>, <code class="docutils literal notranslate"><span class="pre"><OS></span></code> and <code class="docutils literal notranslate"><span class="pre"><Environment></span></code>
+are the same as the <em>Target Triple</em> (see
+<a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>).</li>
+<li><code class="docutils literal notranslate"><span class="pre"><Processor></span></code> is the same as the <em>Processor</em> (see
+<a class="reference internal" href="#amdgpu-processors"><span class="std std-ref">Processors</span></a>).</li>
+<li><code class="docutils literal notranslate"><span class="pre"><Target</span> <span class="pre">Features></span></code> is a list of the enabled <em>Target Features</em>
+(see <a class="reference internal" href="#amdgpu-target-features"><span class="std std-ref">Target Features</span></a>), each prefixed by a plus, that
+apply to <em>Processor</em>. The list must be in the same order as listed
+in the table <a class="reference internal" href="#amdgpu-target-feature-table"><span class="std std-ref">AMDGPU Target Features</span></a>. Note that <em>Target
+Features</em> must be included in the list if they are enabled even if
+that is the default for <em>Processor</em>.</li>
+</ul>
+</div></blockquote>
+<p>For example:</p>
+<blockquote>
+<div><code class="docutils literal notranslate"><span class="pre">"amdgcn-amd-amdhsa--gfx902+xnack"</span></code></div></blockquote>
+</div>
+<div class="section" id="code-object-metadata">
+<span id="amdgpu-amdhsa-code-object-metadata"></span><h4><a class="toc-backref" href="#id72">Code Object Metadata</a><a class="headerlink" href="#code-object-metadata" title="Permalink to this headline">¶</a></h4>
+<p>The code object metadata specifies extensible metadata associated with the code
+objects executed on HSA <a class="reference internal" href="#hsa" id="id26">[HSA]</a> compatible runtimes such as AMDâs ROCm
+<a class="reference internal" href="#amd-rocm" id="id27">[AMD-ROCm]</a>. The encoding and semantics of this metadata depends on the code
+object version; see <a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata-v2"><span class="std std-ref">Code Object V2 Metadata (-mattr=-code-object-v3)</span></a> and
+<a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata-v3"><span class="std std-ref">Code Object V3 Metadata (-mattr=+code-object-v3)</span></a>.</p>
+<p>Code object metadata is specified in a note record (see
+<a class="reference internal" href="#amdgpu-note-records"><span class="std std-ref">Note Records</span></a>) and is required when the target triple OS is
+<code class="docutils literal notranslate"><span class="pre">amdhsa</span></code> (see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>). It must contain the minimum
+information necessary to support the ROCM kernel queries. For example, the
+segment sizes needed in a dispatch packet. In addition, a high level language
+runtime may require other information to be included. For example, the AMD
+OpenCL runtime records kernel argument information.</p>
+<div class="section" id="code-object-v2-metadata-mattr-code-object-v3">
+<span id="amdgpu-amdhsa-code-object-metadata-v2"></span><h5><a class="toc-backref" href="#id73">Code Object V2 Metadata (-mattr=-code-object-v3)</a><a class="headerlink" href="#code-object-v2-metadata-mattr-code-object-v3" title="Permalink to this headline">¶</a></h5>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">Code Object V2 is not the default code object version emitted by
+this version of LLVM. For a description of the metadata generated with the
+default configuration (Code Object V3) see
+<a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata-v3"><span class="std std-ref">Code Object V3 Metadata (-mattr=+code-object-v3)</span></a>.</p>
+</div>
+<p>Code object V2 metadata is specified by the <code class="docutils literal notranslate"><span class="pre">NT_AMD_AMDGPU_METADATA</span></code> note
+record (see <a class="reference internal" href="#amdgpu-note-records-v2"><span class="std std-ref">Code Object V2 Note Records (-mattr=-code-object-v3)</span></a>).</p>
+<p>The metadata is specified as a YAML formatted string (see <a class="reference internal" href="#yaml" id="id28">[YAML]</a> and
+<a class="reference internal" href="YamlIO.html"><span class="doc">YAML I/O</span></a>).</p>
+<p>The metadata is represented as a single YAML document comprised of the mapping
+defined in table <a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata-map-table-v2"><span class="std std-ref">AMDHSA Code Object V2 Metadata Map</span></a> and
+referenced tables.</p>
+<p>For boolean values, the string values of <code class="docutils literal notranslate"><span class="pre">false</span></code> and <code class="docutils literal notranslate"><span class="pre">true</span></code> are used for
+false and true respectively.</p>
+<p>Additional information can be added to the mappings. To avoid conflicts, any
+non-AMD key names should be prefixed by â<em>vendor-name</em>.â.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-metadata-map-table-v2">
+<caption><span class="caption-text">AMDHSA Code Object V2 Metadata Map</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-metadata-map-table-v2" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="11%" />
+<col width="15%" />
+<col width="10%" />
+<col width="65%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">String Key</th>
+<th class="head">Value Type</th>
+<th class="head">Required?</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>âVersionâ</td>
+<td>sequence of
+2 integers</td>
+<td>Required</td>
+<td><ul class="first last simple">
+<li>The first integer is the major
+version. Currently 1.</li>
+<li>The second integer is the minor
+version. Currently 0.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td>âPrintfâ</td>
+<td>sequence of
+strings</td>
+<td> </td>
+<td><p class="first">Each string is encoded information
+about a printf function call. The
+encoded information is organized as
+fields separated by colon (â:â):</p>
+<p><code class="docutils literal notranslate"><span class="pre">ID:N:S[0]:S[1]:...:S[N-1]:FormatString</span></code></p>
+<p>where:</p>
+<dl class="last docutils">
+<dt><code class="docutils literal notranslate"><span class="pre">ID</span></code></dt>
+<dd>A 32 bit integer as a unique id for
+each printf function call</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">N</span></code></dt>
+<dd>A 32 bit integer equal to the number
+of arguments of printf function call
+minus 1</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">S[i]</span></code> (where i = 0, 1, ⦠, N-1)</dt>
+<dd>32 bit integers for the size in bytes
+of the i-th FormatString argument of
+the printf function call</dd>
+<dt>FormatString</dt>
+<dd>The format string passed to the
+printf function call.</dd>
+</dl>
+</td>
+</tr>
+<tr class="row-even"><td>âKernelsâ</td>
+<td>sequence of
+mapping</td>
+<td>Required</td>
+<td>Sequence of the mappings for each
+kernel in the code object. See
+<a class="reference internal" href="#amdgpu-amdhsa-code-object-kernel-metadata-map-table-v2"><span class="std std-ref">AMDHSA Code Object V2 Kernel Metadata Map</span></a>
+for the definition of the mapping.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-kernel-metadata-map-table-v2">
+<caption><span class="caption-text">AMDHSA Code Object V2 Kernel Metadata Map</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-kernel-metadata-map-table-v2" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="15%" />
+<col width="12%" />
+<col width="8%" />
+<col width="66%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">String Key</th>
+<th class="head">Value Type</th>
+<th class="head">Required?</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>âNameâ</td>
+<td>string</td>
+<td>Required</td>
+<td>Source name of the kernel.</td>
+</tr>
+<tr class="row-odd"><td>âSymbolNameâ</td>
+<td>string</td>
+<td>Required</td>
+<td>Name of the kernel
+descriptor ELF symbol.</td>
+</tr>
+<tr class="row-even"><td>âLanguageâ</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">Source language of the kernel.
+Values include:</p>
+<ul class="last simple">
+<li>âOpenCL Câ</li>
+<li>âOpenCL C++â</li>
+<li>âHCCâ</li>
+<li>âOpenMPâ</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td>âLanguageVersionâ</td>
+<td>sequence of
+2 integers</td>
+<td> </td>
+<td><ul class="first last simple">
+<li>The first integer is the major
+version.</li>
+<li>The second integer is the
+minor version.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>âAttrsâ</td>
+<td>mapping</td>
+<td> </td>
+<td>Mapping of kernel attributes.
+See
+<a class="reference internal" href="#amdgpu-amdhsa-code-object-kernel-attribute-metadata-map-table-v2"><span class="std std-ref">AMDHSA Code Object V2 Kernel Attribute Metadata Map</span></a>
+for the mapping definition.</td>
+</tr>
+<tr class="row-odd"><td>âArgsâ</td>
+<td>sequence of
+mapping</td>
+<td> </td>
+<td>Sequence of mappings of the
+kernel arguments. See
+<a class="reference internal" href="#amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v2"><span class="std std-ref">AMDHSA Code Object V2 Kernel Argument Metadata Map</span></a>
+for the definition of the mapping.</td>
+</tr>
+<tr class="row-even"><td>âCodePropsâ</td>
+<td>mapping</td>
+<td> </td>
+<td>Mapping of properties related to
+the kernel code. See
+<a class="reference internal" href="#amdgpu-amdhsa-code-object-kernel-code-properties-metadata-map-table-v2"><span class="std std-ref">AMDHSA Code Object V2 Kernel Code Properties Metadata Map</span></a>
+for the mapping definition.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-kernel-attribute-metadata-map-table-v2">
+<caption><span class="caption-text">AMDHSA Code Object V2 Kernel Attribute Metadata Map</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-kernel-attribute-metadata-map-table-v2" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="26%" />
+<col width="19%" />
+<col width="13%" />
+<col width="42%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">String Key</th>
+<th class="head">Value Type</th>
+<th class="head">Required?</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>âReqdWorkGroupSizeâ</td>
+<td>sequence of
+3 integers</td>
+<td> </td>
+<td><p class="first">If not 0, 0, 0 then all values
+must be >=1 and the dispatch
+work-group size X, Y, Z must
+correspond to the specified
+values. Defaults to 0, 0, 0.</p>
+<p class="last">Corresponds to the OpenCL
+<code class="docutils literal notranslate"><span class="pre">reqd_work_group_size</span></code>
+attribute.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>âWorkGroupSizeHintâ</td>
+<td>sequence of
+3 integers</td>
+<td> </td>
+<td><p class="first">The dispatch work-group size
+X, Y, Z is likely to be the
+specified values.</p>
+<p class="last">Corresponds to the OpenCL
+<code class="docutils literal notranslate"><span class="pre">work_group_size_hint</span></code>
+attribute.</p>
+</td>
+</tr>
+<tr class="row-even"><td>âVecTypeHintâ</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">The name of a scalar or vector
+type.</p>
+<p class="last">Corresponds to the OpenCL
+<code class="docutils literal notranslate"><span class="pre">vec_type_hint</span></code> attribute.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>âRuntimeHandleâ</td>
+<td>string</td>
+<td> </td>
+<td>The external symbol name
+associated with a kernel.
+OpenCL runtime allocates a
+global buffer for the symbol
+and saves the kernelâs address
+to it, which is used for
+device side enqueueing. Only
+available for device side
+enqueued kernels.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v2">
+<caption><span class="caption-text">AMDHSA Code Object V2 Kernel Argument Metadata Map</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v2" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="22%" />
+<col width="18%" />
+<col width="12%" />
+<col width="49%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">String Key</th>
+<th class="head">Value Type</th>
+<th class="head">Required?</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>âNameâ</td>
+<td>string</td>
+<td> </td>
+<td>Kernel argument name.</td>
+</tr>
+<tr class="row-odd"><td>âTypeNameâ</td>
+<td>string</td>
+<td> </td>
+<td>Kernel argument type name.</td>
+</tr>
+<tr class="row-even"><td>âSizeâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>Kernel argument size in bytes.</td>
+</tr>
+<tr class="row-odd"><td>âAlignâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>Kernel argument alignment in
+bytes. Must be a power of two.</td>
+</tr>
+<tr class="row-even"><td>âValueKindâ</td>
+<td>string</td>
+<td>Required</td>
+<td><p class="first">Kernel argument kind that
+specifies how to set up the
+corresponding argument.
+Values include:</p>
+<dl class="last docutils">
+<dt>âByValueâ</dt>
+<dd>The argument is copied
+directly into the kernarg.</dd>
+<dt>âGlobalBufferâ</dt>
+<dd>A global address space pointer
+to the buffer data is passed
+in the kernarg.</dd>
+<dt>âDynamicSharedPointerâ</dt>
+<dd>A group address space pointer
+to dynamically allocated LDS
+is passed in the kernarg.</dd>
+<dt>âSamplerâ</dt>
+<dd>A global address space
+pointer to a S# is passed in
+the kernarg.</dd>
+<dt>âImageâ</dt>
+<dd>A global address space
+pointer to a T# is passed in
+the kernarg.</dd>
+<dt>âPipeâ</dt>
+<dd>A global address space pointer
+to an OpenCL pipe is passed in
+the kernarg.</dd>
+<dt>âQueueâ</dt>
+<dd>A global address space pointer
+to an OpenCL device enqueue
+queue is passed in the
+kernarg.</dd>
+<dt>âHiddenGlobalOffsetXâ</dt>
+<dd>The OpenCL grid dispatch
+global offset for the X
+dimension is passed in the
+kernarg.</dd>
+<dt>âHiddenGlobalOffsetYâ</dt>
+<dd>The OpenCL grid dispatch
+global offset for the Y
+dimension is passed in the
+kernarg.</dd>
+<dt>âHiddenGlobalOffsetZâ</dt>
+<dd>The OpenCL grid dispatch
+global offset for the Z
+dimension is passed in the
+kernarg.</dd>
+<dt>âHiddenNoneâ</dt>
+<dd>An argument that is not used
+by the kernel. Space needs to
+be left for it, but it does
+not need to be set up.</dd>
+<dt>âHiddenPrintfBufferâ</dt>
+<dd>A global address space pointer
+to the runtime printf buffer
+is passed in kernarg.</dd>
+<dt>âHiddenDefaultQueueâ</dt>
+<dd>A global address space pointer
+to the OpenCL device enqueue
+queue that should be used by
+the kernel by default is
+passed in the kernarg.</dd>
+<dt>âHiddenCompletionActionâ</dt>
+<dd>A global address space pointer
+to help link enqueued kernels into
+the ancestor tree for determining
+when the parent kernel has finished.</dd>
+<dt>âHiddenMultiGridSyncArgâ</dt>
+<dd>A global address space pointer for
+multi-grid synchronization is
+passed in the kernarg.</dd>
+</dl>
+</td>
+</tr>
+<tr class="row-odd"><td>âValueTypeâ</td>
+<td>string</td>
+<td>Required</td>
+<td><p class="first">Kernel argument value type. Only
+present if âValueKindâ is
+âByValueâ. For vector data
+types, the value is for the
+element type. Values include:</p>
+<ul class="last simple">
+<li>âStructâ</li>
+<li>âI8â</li>
+<li>âU8â</li>
+<li>âI16â</li>
+<li>âU16â</li>
+<li>âF16â</li>
+<li>âI32â</li>
+<li>âU32â</li>
+<li>âF32â</li>
+<li>âI64â</li>
+<li>âU64â</li>
+<li>âF64â</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>âPointeeAlignâ</td>
+<td>integer</td>
+<td> </td>
+<td>Alignment in bytes of pointee
+type for pointer type kernel
+argument. Must be a power
+of 2. Only present if
+âValueKindâ is
+âDynamicSharedPointerâ.</td>
+</tr>
+<tr class="row-odd"><td>âAddrSpaceQualâ</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">Kernel argument address space
+qualifier. Only present if
+âValueKindâ is âGlobalBufferâ or
+âDynamicSharedPointerâ. Values
+are:</p>
+<ul class="last simple">
+<li>âPrivateâ</li>
+<li>âGlobalâ</li>
+<li>âConstantâ</li>
+<li>âLocalâ</li>
+<li>âGenericâ</li>
+<li>âRegionâ</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>âAccQualâ</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">Kernel argument access
+qualifier. Only present if
+âValueKindâ is âImageâ or
+âPipeâ. Values
+are:</p>
+<ul class="last simple">
+<li>âReadOnlyâ</li>
+<li>âWriteOnlyâ</li>
+<li>âReadWriteâ</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td>âActualAccQualâ</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">The actual memory accesses
+performed by the kernel on the
+kernel argument. Only present if
+âValueKindâ is âGlobalBufferâ,
+âImageâ, or âPipeâ. This may be
+more restrictive than indicated
+by âAccQualâ to reflect what the
+kernel actual does. If not
+present then the runtime must
+assume what is implied by
+âAccQualâ and âIsConstâ. Values
+are:</p>
+<ul class="last simple">
+<li>âReadOnlyâ</li>
+<li>âWriteOnlyâ</li>
+<li>âReadWriteâ</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>âIsConstâ</td>
+<td>boolean</td>
+<td> </td>
+<td>Indicates if the kernel argument
+is const qualified. Only present
+if âValueKindâ is
+âGlobalBufferâ.</td>
+</tr>
+<tr class="row-odd"><td>âIsRestrictâ</td>
+<td>boolean</td>
+<td> </td>
+<td>Indicates if the kernel argument
+is restrict qualified. Only
+present if âValueKindâ is
+âGlobalBufferâ.</td>
+</tr>
+<tr class="row-even"><td>âIsVolatileâ</td>
+<td>boolean</td>
+<td> </td>
+<td>Indicates if the kernel argument
+is volatile qualified. Only
+present if âValueKindâ is
+âGlobalBufferâ.</td>
+</tr>
+<tr class="row-odd"><td>âIsPipeâ</td>
+<td>boolean</td>
+<td> </td>
+<td>Indicates if the kernel argument
+is pipe qualified. Only present
+if âValueKindâ is âPipeâ.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-kernel-code-properties-metadata-map-table-v2">
+<caption><span class="caption-text">AMDHSA Code Object V2 Kernel Code Properties Metadata Map</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-kernel-code-properties-metadata-map-table-v2" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="39%" />
+<col width="19%" />
+<col width="13%" />
+<col width="29%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">String Key</th>
+<th class="head">Value Type</th>
+<th class="head">Required?</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>âKernargSegmentSizeâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>The size in bytes of
+the kernarg segment
+that holds the values
+of the arguments to
+the kernel.</td>
+</tr>
+<tr class="row-odd"><td>âGroupSegmentFixedSizeâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>The amount of group
+segment memory
+required by a
+work-group in
+bytes. This does not
+include any
+dynamically allocated
+group segment memory
+that may be added
+when the kernel is
+dispatched.</td>
+</tr>
+<tr class="row-even"><td>âPrivateSegmentFixedSizeâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>The amount of fixed
+private address space
+memory required for a
+work-item in
+bytes. If the kernel
+uses a dynamic call
+stack then additional
+space must be added
+to this value for the
+call stack.</td>
+</tr>
+<tr class="row-odd"><td>âKernargSegmentAlignâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>The maximum byte
+alignment of
+arguments in the
+kernarg segment. Must
+be a power of 2.</td>
+</tr>
+<tr class="row-even"><td>âWavefrontSizeâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>Wavefront size. Must
+be a power of 2.</td>
+</tr>
+<tr class="row-odd"><td>âNumSGPRsâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>Number of scalar
+registers used by a
+wavefront for
+GFX6-GFX10. This
+includes the special
+SGPRs for VCC, Flat
+Scratch (GFX7-GFX10)
+and XNACK (for
+GFX8-GFX10). It does
+not include the 16
+SGPR added if a trap
+handler is
+enabled. It is not
+rounded up to the
+allocation
+granularity.</td>
+</tr>
+<tr class="row-even"><td>âNumVGPRsâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>Number of vector
+registers used by
+each work-item for
+GFX6-GFX10</td>
+</tr>
+<tr class="row-odd"><td>âMaxFlatWorkGroupSizeâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>Maximum flat
+work-group size
+supported by the
+kernel in work-items.
+Must be >=1 and
+consistent with
+ReqdWorkGroupSize if
+not 0, 0, 0.</td>
+</tr>
+<tr class="row-even"><td>âNumSpilledSGPRsâ</td>
+<td>integer</td>
+<td> </td>
+<td>Number of stores from
+a scalar register to
+a register allocator
+created spill
+location.</td>
+</tr>
+<tr class="row-odd"><td>âNumSpilledVGPRsâ</td>
+<td>integer</td>
+<td> </td>
+<td>Number of stores from
+a vector register to
+a register allocator
+created spill
+location.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="code-object-v3-metadata-mattr-code-object-v3">
+<span id="amdgpu-amdhsa-code-object-metadata-v3"></span><h5><a class="toc-backref" href="#id74">Code Object V3 Metadata (-mattr=+code-object-v3)</a><a class="headerlink" href="#code-object-v3-metadata-mattr-code-object-v3" title="Permalink to this headline">¶</a></h5>
+<p>Code object V3 metadata is specified by the <code class="docutils literal notranslate"><span class="pre">NT_AMDGPU_METADATA</span></code> note record
+(see <a class="reference internal" href="#amdgpu-note-records-v3"><span class="std std-ref">Code Object V3 Note Records (-mattr=+code-object-v3)</span></a>).</p>
+<p>The metadata is represented as Message Pack formatted binary data (see
+<a class="reference internal" href="#msgpack" id="id29">[MsgPack]</a>). The top level is a Message Pack map that includes the
+keys defined in table
+<a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata-map-table-v3"><span class="std std-ref">AMDHSA Code Object V3 Metadata Map</span></a> and referenced
+tables.</p>
+<p>Additional information can be added to the maps. To avoid conflicts,
+any key names should be prefixed by â<em>vendor-name</em>.â where
+<code class="docutils literal notranslate"><span class="pre">vendor-name</span></code> can be the the name of the vendor and specific vendor
+tool that generates the information. The prefix is abbreviated to
+simply â.â when it appears within a map that has been added by the
+same <em>vendor-name</em>.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-metadata-map-table-v3">
+<caption><span class="caption-text">AMDHSA Code Object V3 Metadata Map</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-metadata-map-table-v3" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="17%" />
+<col width="14%" />
+<col width="9%" />
+<col width="60%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">String Key</th>
+<th class="head">Value Type</th>
+<th class="head">Required?</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>âamdhsa.versionâ</td>
+<td>sequence of
+2 integers</td>
+<td>Required</td>
+<td><ul class="first last simple">
+<li>The first integer is the major
+version. Currently 1.</li>
+<li>The second integer is the minor
+version. Currently 0.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td>âamdhsa.printfâ</td>
+<td>sequence of
+strings</td>
+<td> </td>
+<td><p class="first">Each string is encoded information
+about a printf function call. The
+encoded information is organized as
+fields separated by colon (â:â):</p>
+<p><code class="docutils literal notranslate"><span class="pre">ID:N:S[0]:S[1]:...:S[N-1]:FormatString</span></code></p>
+<p>where:</p>
+<dl class="last docutils">
+<dt><code class="docutils literal notranslate"><span class="pre">ID</span></code></dt>
+<dd>A 32 bit integer as a unique id for
+each printf function call</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">N</span></code></dt>
+<dd>A 32 bit integer equal to the number
+of arguments of printf function call
+minus 1</dd>
+<dt><code class="docutils literal notranslate"><span class="pre">S[i]</span></code> (where i = 0, 1, ⦠, N-1)</dt>
+<dd>32 bit integers for the size in bytes
+of the i-th FormatString argument of
+the printf function call</dd>
+<dt>FormatString</dt>
+<dd>The format string passed to the
+printf function call.</dd>
+</dl>
+</td>
+</tr>
+<tr class="row-even"><td>âamdhsa.kernelsâ</td>
+<td>sequence of
+map</td>
+<td>Required</td>
+<td>Sequence of the maps for each
+kernel in the code object. See
+<a class="reference internal" href="#amdgpu-amdhsa-code-object-kernel-metadata-map-table-v3"><span class="std std-ref">AMDHSA Code Object V3 Kernel Metadata Map</span></a>
+for the definition of the keys included
+in that map.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-kernel-metadata-map-table-v3">
+<caption><span class="caption-text">AMDHSA Code Object V3 Kernel Metadata Map</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-kernel-metadata-map-table-v3" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="27%" />
+<col width="11%" />
+<col width="7%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">String Key</th>
+<th class="head">Value Type</th>
+<th class="head">Required?</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>â.nameâ</td>
+<td>string</td>
+<td>Required</td>
+<td>Source name of the kernel.</td>
+</tr>
+<tr class="row-odd"><td>â.symbolâ</td>
+<td>string</td>
+<td>Required</td>
+<td>Name of the kernel
+descriptor ELF symbol.</td>
+</tr>
+<tr class="row-even"><td>â.languageâ</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">Source language of the kernel.
+Values include:</p>
+<ul class="last simple">
+<li>âOpenCL Câ</li>
+<li>âOpenCL C++â</li>
+<li>âHCCâ</li>
+<li>âHIPâ</li>
+<li>âOpenMPâ</li>
+<li>âAssemblerâ</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td>â.language_versionâ</td>
+<td>sequence of
+2 integers</td>
+<td> </td>
+<td><ul class="first last simple">
+<li>The first integer is the major
+version.</li>
+<li>The second integer is the
+minor version.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>â.argsâ</td>
+<td>sequence of
+map</td>
+<td> </td>
+<td>Sequence of maps of the
+kernel arguments. See
+<a class="reference internal" href="#amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v3"><span class="std std-ref">AMDHSA Code Object V3 Kernel Argument Metadata Map</span></a>
+for the definition of the keys
+included in that map.</td>
+</tr>
+<tr class="row-odd"><td>â.reqd_workgroup_sizeâ</td>
+<td>sequence of
+3 integers</td>
+<td> </td>
+<td><p class="first">If not 0, 0, 0 then all values
+must be >=1 and the dispatch
+work-group size X, Y, Z must
+correspond to the specified
+values. Defaults to 0, 0, 0.</p>
+<p class="last">Corresponds to the OpenCL
+<code class="docutils literal notranslate"><span class="pre">reqd_work_group_size</span></code>
+attribute.</p>
+</td>
+</tr>
+<tr class="row-even"><td>â.workgroup_size_hintâ</td>
+<td>sequence of
+3 integers</td>
+<td> </td>
+<td><p class="first">The dispatch work-group size
+X, Y, Z is likely to be the
+specified values.</p>
+<p class="last">Corresponds to the OpenCL
+<code class="docutils literal notranslate"><span class="pre">work_group_size_hint</span></code>
+attribute.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>â.vec_type_hintâ</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">The name of a scalar or vector
+type.</p>
+<p class="last">Corresponds to the OpenCL
+<code class="docutils literal notranslate"><span class="pre">vec_type_hint</span></code> attribute.</p>
+</td>
+</tr>
+<tr class="row-even"><td>â.device_enqueue_symbolâ</td>
+<td>string</td>
+<td> </td>
+<td>The external symbol name
+associated with a kernel.
+OpenCL runtime allocates a
+global buffer for the symbol
+and saves the kernelâs address
+to it, which is used for
+device side enqueueing. Only
+available for device side
+enqueued kernels.</td>
+</tr>
+<tr class="row-odd"><td>â.kernarg_segment_sizeâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>The size in bytes of
+the kernarg segment
+that holds the values
+of the arguments to
+the kernel.</td>
+</tr>
+<tr class="row-even"><td>â.group_segment_fixed_sizeâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>The amount of group
+segment memory
+required by a
+work-group in
+bytes. This does not
+include any
+dynamically allocated
+group segment memory
+that may be added
+when the kernel is
+dispatched.</td>
+</tr>
+<tr class="row-odd"><td>â.private_segment_fixed_sizeâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>The amount of fixed
+private address space
+memory required for a
+work-item in
+bytes. If the kernel
+uses a dynamic call
+stack then additional
+space must be added
+to this value for the
+call stack.</td>
+</tr>
+<tr class="row-even"><td>â.kernarg_segment_alignâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>The maximum byte
+alignment of
+arguments in the
+kernarg segment. Must
+be a power of 2.</td>
+</tr>
+<tr class="row-odd"><td>â.wavefront_sizeâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>Wavefront size. Must
+be a power of 2.</td>
+</tr>
+<tr class="row-even"><td>â.sgpr_countâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>Number of scalar
+registers required by a
+wavefront for
+GFX6-GFX9. A register
+is required if it is
+used explicitly, or
+if a higher numbered
+register is used
+explicitly. This
+includes the special
+SGPRs for VCC, Flat
+Scratch (GFX7-GFX9)
+and XNACK (for
+GFX8-GFX9). It does
+not include the 16
+SGPR added if a trap
+handler is
+enabled. It is not
+rounded up to the
+allocation
+granularity.</td>
+</tr>
+<tr class="row-odd"><td>â.vgpr_countâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>Number of vector
+registers required by
+each work-item for
+GFX6-GFX9. A register
+is required if it is
+used explicitly, or
+if a higher numbered
+register is used
+explicitly.</td>
+</tr>
+<tr class="row-even"><td>â.max_flat_workgroup_sizeâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>Maximum flat
+work-group size
+supported by the
+kernel in work-items.
+Must be >=1 and
+consistent with
+ReqdWorkGroupSize if
+not 0, 0, 0.</td>
+</tr>
+<tr class="row-odd"><td>â.sgpr_spill_countâ</td>
+<td>integer</td>
+<td> </td>
+<td>Number of stores from
+a scalar register to
+a register allocator
+created spill
+location.</td>
+</tr>
+<tr class="row-even"><td>â.vgpr_spill_countâ</td>
+<td>integer</td>
+<td> </td>
+<td>Number of stores from
+a vector register to
+a register allocator
+created spill
+location.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v3">
+<caption><span class="caption-text">AMDHSA Code Object V3 Kernel Argument Metadata Map</span><a class="headerlink" href="#amdgpu-amdhsa-code-object-kernel-argument-metadata-map-table-v3" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="26%" />
+<col width="17%" />
+<col width="11%" />
+<col width="46%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">String Key</th>
+<th class="head">Value Type</th>
+<th class="head">Required?</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>â.nameâ</td>
+<td>string</td>
+<td> </td>
+<td>Kernel argument name.</td>
+</tr>
+<tr class="row-odd"><td>â.type_nameâ</td>
+<td>string</td>
+<td> </td>
+<td>Kernel argument type name.</td>
+</tr>
+<tr class="row-even"><td>â.sizeâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>Kernel argument size in bytes.</td>
+</tr>
+<tr class="row-odd"><td>â.offsetâ</td>
+<td>integer</td>
+<td>Required</td>
+<td>Kernel argument offset in
+bytes. The offset must be a
+multiple of the alignment
+required by the argument.</td>
+</tr>
+<tr class="row-even"><td>â.value_kindâ</td>
+<td>string</td>
+<td>Required</td>
+<td><p class="first">Kernel argument kind that
+specifies how to set up the
+corresponding argument.
+Values include:</p>
+<dl class="last docutils">
+<dt>âby_valueâ</dt>
+<dd>The argument is copied
+directly into the kernarg.</dd>
+<dt>âglobal_bufferâ</dt>
+<dd>A global address space pointer
+to the buffer data is passed
+in the kernarg.</dd>
+<dt>âdynamic_shared_pointerâ</dt>
+<dd>A group address space pointer
+to dynamically allocated LDS
+is passed in the kernarg.</dd>
+<dt>âsamplerâ</dt>
+<dd>A global address space
+pointer to a S# is passed in
+the kernarg.</dd>
+<dt>âimageâ</dt>
+<dd>A global address space
+pointer to a T# is passed in
+the kernarg.</dd>
+<dt>âpipeâ</dt>
+<dd>A global address space pointer
+to an OpenCL pipe is passed in
+the kernarg.</dd>
+<dt>âqueueâ</dt>
+<dd>A global address space pointer
+to an OpenCL device enqueue
+queue is passed in the
+kernarg.</dd>
+<dt>âhidden_global_offset_xâ</dt>
+<dd>The OpenCL grid dispatch
+global offset for the X
+dimension is passed in the
+kernarg.</dd>
+<dt>âhidden_global_offset_yâ</dt>
+<dd>The OpenCL grid dispatch
+global offset for the Y
+dimension is passed in the
+kernarg.</dd>
+<dt>âhidden_global_offset_zâ</dt>
+<dd>The OpenCL grid dispatch
+global offset for the Z
+dimension is passed in the
+kernarg.</dd>
+<dt>âhidden_noneâ</dt>
+<dd>An argument that is not used
+by the kernel. Space needs to
+be left for it, but it does
+not need to be set up.</dd>
+<dt>âhidden_printf_bufferâ</dt>
+<dd>A global address space pointer
+to the runtime printf buffer
+is passed in kernarg.</dd>
+<dt>âhidden_default_queueâ</dt>
+<dd>A global address space pointer
+to the OpenCL device enqueue
+queue that should be used by
+the kernel by default is
+passed in the kernarg.</dd>
+<dt>âhidden_completion_actionâ</dt>
+<dd>A global address space pointer
+to help link enqueued kernels into
+the ancestor tree for determining
+when the parent kernel has finished.</dd>
+<dt>âhidden_multigrid_sync_argâ</dt>
+<dd>A global address space pointer for
+multi-grid synchronization is
+passed in the kernarg.</dd>
+</dl>
+</td>
+</tr>
+<tr class="row-odd"><td>â.value_typeâ</td>
+<td>string</td>
+<td>Required</td>
+<td><p class="first">Kernel argument value type. Only
+present if â.value_kindâ is
+âby_valueâ. For vector data
+types, the value is for the
+element type. Values include:</p>
+<ul class="last simple">
+<li>âstructâ</li>
+<li>âi8â</li>
+<li>âu8â</li>
+<li>âi16â</li>
+<li>âu16â</li>
+<li>âf16â</li>
+<li>âi32â</li>
+<li>âu32â</li>
+<li>âf32â</li>
+<li>âi64â</li>
+<li>âu64â</li>
+<li>âf64â</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>â.pointee_alignâ</td>
+<td>integer</td>
+<td> </td>
+<td>Alignment in bytes of pointee
+type for pointer type kernel
+argument. Must be a power
+of 2. Only present if
+â.value_kindâ is
+âdynamic_shared_pointerâ.</td>
+</tr>
+<tr class="row-odd"><td>â.address_spaceâ</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">Kernel argument address space
+qualifier. Only present if
+â.value_kindâ is âglobal_bufferâ or
+âdynamic_shared_pointerâ. Values
+are:</p>
+<ul class="last simple">
+<li>âprivateâ</li>
+<li>âglobalâ</li>
+<li>âconstantâ</li>
+<li>âlocalâ</li>
+<li>âgenericâ</li>
+<li>âregionâ</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>â.accessâ</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">Kernel argument access
+qualifier. Only present if
+â.value_kindâ is âimageâ or
+âpipeâ. Values
+are:</p>
+<ul class="last simple">
+<li>âread_onlyâ</li>
+<li>âwrite_onlyâ</li>
+<li>âread_writeâ</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td>â.actual_accessâ</td>
+<td>string</td>
+<td> </td>
+<td><p class="first">The actual memory accesses
+performed by the kernel on the
+kernel argument. Only present if
+â.value_kindâ is âglobal_bufferâ,
+âimageâ, or âpipeâ. This may be
+more restrictive than indicated
+by â.accessâ to reflect what the
+kernel actual does. If not
+present then the runtime must
+assume what is implied by
+â.accessâ and â.is_constâ . Values
+are:</p>
+<ul class="last simple">
+<li>âread_onlyâ</li>
+<li>âwrite_onlyâ</li>
+<li>âread_writeâ</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>â.is_constâ</td>
+<td>boolean</td>
+<td> </td>
+<td>Indicates if the kernel argument
+is const qualified. Only present
+if â.value_kindâ is
+âglobal_bufferâ.</td>
+</tr>
+<tr class="row-odd"><td>â.is_restrictâ</td>
+<td>boolean</td>
+<td> </td>
+<td>Indicates if the kernel argument
+is restrict qualified. Only
+present if â.value_kindâ is
+âglobal_bufferâ.</td>
+</tr>
+<tr class="row-even"><td>â.is_volatileâ</td>
+<td>boolean</td>
+<td> </td>
+<td>Indicates if the kernel argument
+is volatile qualified. Only
+present if â.value_kindâ is
+âglobal_bufferâ.</td>
+</tr>
+<tr class="row-odd"><td>â.is_pipeâ</td>
+<td>boolean</td>
+<td> </td>
+<td>Indicates if the kernel argument
+is pipe qualified. Only present
+if â.value_kindâ is âpipeâ.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="kernel-dispatch">
+<h4><a class="toc-backref" href="#id75">Kernel Dispatch</a><a class="headerlink" href="#kernel-dispatch" title="Permalink to this headline">¶</a></h4>
+<p>The HSA architected queuing language (AQL) defines a user space memory interface
+that can be used to control the dispatch of kernels, in an agent independent
+way. An agent can have zero or more AQL queues created for it using the ROCm
+runtime, in which AQL packets (all of which are 64 bytes) can be placed. See the
+<em>HSA Platform System Architecture Specification</em> <a class="reference internal" href="#hsa" id="id30">[HSA]</a> for the AQL queue
+mechanics and packet layouts.</p>
+<p>The packet processor of a kernel agent is responsible for detecting and
+dispatching HSA kernels from the AQL queues associated with it. For AMD GPUs the
+packet processor is implemented by the hardware command processor (CP),
+asynchronous dispatch controller (ADC) and shader processor input controller
+(SPI).</p>
+<p>The ROCm runtime can be used to allocate an AQL queue object. It uses the kernel
+mode driver to initialize and register the AQL queue with CP.</p>
+<p>To dispatch a kernel the following actions are performed. This can occur in the
+CPU host program, or from an HSA kernel executing on a GPU.</p>
+<ol class="arabic simple">
+<li>A pointer to an AQL queue for the kernel agent on which the kernel is to be
+executed is obtained.</li>
+<li>A pointer to the kernel descriptor (see
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>) of the kernel to execute is
+obtained. It must be for a kernel that is contained in a code object that that
+was loaded by the ROCm runtime on the kernel agent with which the AQL queue is
+associated.</li>
+<li>Space is allocated for the kernel arguments using the ROCm runtime allocator
+for a memory region with the kernarg property for the kernel agent that will
+execute the kernel. It must be at least 16 byte aligned.</li>
+<li>Kernel argument values are assigned to the kernel argument memory
+allocation. The layout is defined in the <em>HSA Programmerâs Language Reference</em>
+<a class="reference internal" href="#hsa" id="id31">[HSA]</a>. For AMDGPU the kernel execution directly accesses the kernel argument
+memory in the same way constant memory is accessed. (Note that the HSA
+specification allows an implementation to copy the kernel argument contents to
+another location that is accessed by the kernel.)</li>
+<li>An AQL kernel dispatch packet is created on the AQL queue. The ROCm runtime
+api uses 64 bit atomic operations to reserve space in the AQL queue for the
+packet. The packet must be set up, and the final write must use an atomic
+store release to set the packet kind to ensure the packet contents are
+visible to the kernel agent. AQL defines a doorbell signal mechanism to
+notify the kernel agent that the AQL queue has been updated. These rules, and
+the layout of the AQL queue and kernel dispatch packet is defined in the <em>HSA
+System Architecture Specification</em> <a class="reference internal" href="#hsa" id="id32">[HSA]</a>.</li>
+<li>A kernel dispatch packet includes information about the actual dispatch,
+such as grid and work-group size, together with information from the code
+object about the kernel, such as segment sizes. The ROCm runtime queries on
+the kernel symbol can be used to obtain the code object values which are
+recorded in the <a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata"><span class="std std-ref">Code Object Metadata</span></a>.</li>
+<li>CP executes micro-code and is responsible for detecting and setting up the
+GPU to execute the wavefronts of a kernel dispatch.</li>
+<li>CP ensures that when the a wavefront starts executing the kernel machine
+code, the scalar general purpose registers (SGPR) and vector general purpose
+registers (VGPR) are set up as required by the machine code. The required
+setup is defined in the <a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>. The initial
+register state is defined in
+<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>.</li>
+<li>The prolog of the kernel machine code (see
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-prolog"><span class="std std-ref">Kernel Prolog</span></a>) sets up the machine state as necessary
+before continuing executing the machine code that corresponds to the kernel.</li>
+<li>When the kernel dispatch has completed execution, CP signals the completion
+signal specified in the kernel dispatch packet if not 0.</li>
+</ol>
+</div>
+<div class="section" id="memory-spaces">
+<span id="amdgpu-amdhsa-memory-spaces"></span><h4><a class="toc-backref" href="#id76">Memory Spaces</a><a class="headerlink" href="#memory-spaces" title="Permalink to this headline">¶</a></h4>
+<p>The memory space properties are:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-memory-spaces-table">
+<caption><span class="caption-text">AMDHSA Memory Spaces</span><a class="headerlink" href="#amdgpu-amdhsa-memory-spaces-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="28%" />
+<col width="18%" />
+<col width="13%" />
+<col width="11%" />
+<col width="30%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Memory Space Name</th>
+<th class="head">HSA Segment
+Name</th>
+<th class="head">Hardware
+Name</th>
+<th class="head">Address
+Size</th>
+<th class="head">NULL Value</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>Private</td>
+<td>private</td>
+<td>scratch</td>
+<td>32</td>
+<td>0x00000000</td>
+</tr>
+<tr class="row-odd"><td>Local</td>
+<td>group</td>
+<td>LDS</td>
+<td>32</td>
+<td>0xFFFFFFFF</td>
+</tr>
+<tr class="row-even"><td>Global</td>
+<td>global</td>
+<td>global</td>
+<td>64</td>
+<td>0x0000000000000000</td>
+</tr>
+<tr class="row-odd"><td>Constant</td>
+<td>constant</td>
+<td><em>same as
+global</em></td>
+<td>64</td>
+<td>0x0000000000000000</td>
+</tr>
+<tr class="row-even"><td>Generic</td>
+<td>flat</td>
+<td>flat</td>
+<td>64</td>
+<td>0x0000000000000000</td>
+</tr>
+<tr class="row-odd"><td>Region</td>
+<td>N/A</td>
+<td>GDS</td>
+<td>32</td>
+<td><em>not implemented
+for AMDHSA</em></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>The global and constant memory spaces both use global virtual addresses, which
+are the same virtual address space used by the CPU. However, some virtual
+addresses may only be accessible to the CPU, some only accessible by the GPU,
+and some by both.</p>
+<p>Using the constant memory space indicates that the data will not change during
+the execution of the kernel. This allows scalar read instructions to be
+used. The vector and scalar L1 caches are invalidated of volatile data before
+each kernel dispatch execution to allow constant memory to change values between
+kernel dispatches.</p>
+<p>The local memory space uses the hardware Local Data Store (LDS) which is
+automatically allocated when the hardware creates work-groups of wavefronts, and
+freed when all the wavefronts of a work-group have terminated. The data store
+(DS) instructions can be used to access it.</p>
+<p>The private memory space uses the hardware scratch memory support. If the kernel
+uses scratch, then the hardware allocates memory that is accessed using
+wavefront lane dword (4 byte) interleaving. The mapping used from private
+address to physical address is:</p>
+<blockquote>
+<div><code class="docutils literal notranslate"><span class="pre">wavefront-scratch-base</span> <span class="pre">+</span>
+<span class="pre">(private-address</span> <span class="pre">*</span> <span class="pre">wavefront-size</span> <span class="pre">*</span> <span class="pre">4)</span> <span class="pre">+</span>
+<span class="pre">(wavefront-lane-id</span> <span class="pre">*</span> <span class="pre">4)</span></code></div></blockquote>
+<p>There are different ways that the wavefront scratch base address is determined
+by a wavefront (see <a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>). This
+memory can be accessed in an interleaved manner using buffer instruction with
+the scratch buffer descriptor and per wavefront scratch offset, by the scratch
+instructions, or by flat instructions. If each lane of a wavefront accesses the
+same private address, the interleaving results in adjacent dwords being accessed
+and hence requires fewer cache lines to be fetched. Multi-dword access is not
+supported except by flat and scratch instructions in GFX9-GFX10.</p>
+<p>The generic address space uses the hardware flat address support available in
+GFX7-GFX10. This uses two fixed ranges of virtual addresses (the private and
+local appertures), that are outside the range of addressible global memory, to
+map from a flat address to a private or local address.</p>
+<p>FLAT instructions can take a flat address and access global, private (scratch)
+and group (LDS) memory depending in if the address is within one of the
+apperture ranges. Flat access to scratch requires hardware aperture setup and
+setup in the kernel prologue (see <a class="reference internal" href="#amdgpu-amdhsa-flat-scratch"><span class="std std-ref">Flat Scratch</span></a>). Flat
+access to LDS requires hardware aperture setup and M0 (GFX7-GFX8) register setup
+(see <a class="reference internal" href="#amdgpu-amdhsa-m0"><span class="std std-ref">M0</span></a>).</p>
+<p>To convert between a segment address and a flat address the base address of the
+appertures address can be used. For GFX7-GFX8 these are available in the
+<a class="reference internal" href="#amdgpu-amdhsa-hsa-aql-queue"><span class="std std-ref">HSA AQL Queue</span></a> the address of which can be obtained with
+Queue Ptr SGPR (see <a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>). For
+GFX9-GFX10 the appature base addresses are directly available as inline constant
+registers <code class="docutils literal notranslate"><span class="pre">SRC_SHARED_BASE/LIMIT</span></code> and <code class="docutils literal notranslate"><span class="pre">SRC_PRIVATE_BASE/LIMIT</span></code>. In 64 bit
+address mode the apperture sizes are 2^32 bytes and the base is aligned to 2^32
+which makes it easier to convert from flat to segment or segment to flat.</p>
+</div>
+<div class="section" id="image-and-samplers">
+<h4><a class="toc-backref" href="#id77">Image and Samplers</a><a class="headerlink" href="#image-and-samplers" title="Permalink to this headline">¶</a></h4>
+<p>Image and sample handles created by the ROCm runtime are 64 bit addresses of a
+hardware 32 byte V# and 48 byte S# object respectively. In order to support the
+HSA <code class="docutils literal notranslate"><span class="pre">query_sampler</span></code> operations two extra dwords are used to store the HSA BRIG
+enumeration values for the queries that are not trivially deducible from the S#
+representation.</p>
+</div>
+<div class="section" id="hsa-signals">
+<h4><a class="toc-backref" href="#id78">HSA Signals</a><a class="headerlink" href="#hsa-signals" title="Permalink to this headline">¶</a></h4>
+<p>HSA signal handles created by the ROCm runtime are 64 bit addresses of a
+structure allocated in memory accessible from both the CPU and GPU. The
+structure is defined by the ROCm runtime and subject to change between releases
+(see <a class="reference internal" href="#amd-rocm-github" id="id33">[AMD-ROCm-github]</a>).</p>
+</div>
+<div class="section" id="hsa-aql-queue">
+<span id="amdgpu-amdhsa-hsa-aql-queue"></span><h4><a class="toc-backref" href="#id79">HSA AQL Queue</a><a class="headerlink" href="#hsa-aql-queue" title="Permalink to this headline">¶</a></h4>
+<p>The HSA AQL queue structure is defined by the ROCm runtime and subject to change
+between releases (see <a class="reference internal" href="#amd-rocm-github" id="id34">[AMD-ROCm-github]</a>). For some processors it contains
+fields needed to implement certain language features such as the flat address
+aperture bases. It also contains fields used by CP such as managing the
+allocation of scratch memory.</p>
+</div>
+<div class="section" id="kernel-descriptor">
+<span id="amdgpu-amdhsa-kernel-descriptor"></span><h4><a class="toc-backref" href="#id80">Kernel Descriptor</a><a class="headerlink" href="#kernel-descriptor" title="Permalink to this headline">¶</a></h4>
+<p>A kernel descriptor consists of the information needed by CP to initiate the
+execution of a kernel, including the entry point address of the machine code
+that implements the kernel.</p>
+<div class="section" id="kernel-descriptor-for-gfx6-gfx10">
+<h5><a class="toc-backref" href="#id81">Kernel Descriptor for GFX6-GFX10</a><a class="headerlink" href="#kernel-descriptor-for-gfx6-gfx10" title="Permalink to this headline">¶</a></h5>
+<p>CP microcode requires the Kernel descriptor to be allocated on 64 byte
+alignment.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table">
+<caption><span class="caption-text">Kernel Descriptor for GFX6-GFX10</span><a class="headerlink" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="7%" />
+<col width="7%" />
+<col width="31%" />
+<col width="55%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Bits</th>
+<th class="head">Size</th>
+<th class="head">Field Name</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>31:0</td>
+<td>4 bytes</td>
+<td>GROUP_SEGMENT_FIXED_SIZE</td>
+<td>The amount of fixed local
+address space memory
+required for a work-group
+in bytes. This does not
+include any dynamically
+allocated local address
+space memory that may be
+added when the kernel is
+dispatched.</td>
+</tr>
+<tr class="row-odd"><td>63:32</td>
+<td>4 bytes</td>
+<td>PRIVATE_SEGMENT_FIXED_SIZE</td>
+<td>The amount of fixed
+private address space
+memory required for a
+work-item in bytes. If
+is_dynamic_callstack is 1
+then additional space must
+be added to this value for
+the call stack.</td>
+</tr>
+<tr class="row-even"><td>127:64</td>
+<td>8 bytes</td>
+<td> </td>
+<td>Reserved, must be 0.</td>
+</tr>
+<tr class="row-odd"><td>191:128</td>
+<td>8 bytes</td>
+<td>KERNEL_CODE_ENTRY_BYTE_OFFSET</td>
+<td>Byte offset (possibly
+negative) from base
+address of kernel
+descriptor to kernelâs
+entry point instruction
+which must be 256 byte
+aligned.</td>
+</tr>
+<tr class="row-even"><td>351:272</td>
+<td>20
+bytes</td>
+<td> </td>
+<td>Reserved, must be 0.</td>
+</tr>
+<tr class="row-odd"><td>383:352</td>
+<td>4 bytes</td>
+<td>COMPUTE_PGM_RSRC3</td>
+<td><dl class="first last docutils">
+<dt>GFX6-9</dt>
+<dd>Reserved, must be 0.</dd>
+<dt>GFX10</dt>
+<dd>Compute Shader (CS)
+program settings used by
+CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC3</span></code>
+configuration
+register. See
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc3-gfx10-table"><span class="std std-ref">compute_pgm_rsrc3 for GFX10</span></a>.</dd>
+</dl>
+</td>
+</tr>
+<tr class="row-even"><td>415:384</td>
+<td>4 bytes</td>
+<td>COMPUTE_PGM_RSRC1</td>
+<td>Compute Shader (CS)
+program settings used by
+CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1</span></code>
+configuration
+register. See
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-odd"><td>447:416</td>
+<td>4 bytes</td>
+<td>COMPUTE_PGM_RSRC2</td>
+<td>Compute Shader (CS)
+program settings used by
+CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2</span></code>
+configuration
+register. See
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-even"><td>448</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_PRIVATE_SEGMENT
+_BUFFER</td>
+<td><p class="first">Enable the setup of the
+SGPR user data registers
+(see
+<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>).</p>
+<p class="last">The total number of SGPR
+user data registers
+requested must not exceed
+16 and match value in
+<code class="docutils literal notranslate"><span class="pre">compute_pgm_rsrc2.user_sgpr.user_sgpr_count</span></code>.
+Any requests beyond 16
+will be ignored.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>449</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_DISPATCH_PTR</td>
+<td><em>see above</em></td>
+</tr>
+<tr class="row-even"><td>450</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_QUEUE_PTR</td>
+<td><em>see above</em></td>
+</tr>
+<tr class="row-odd"><td>451</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_KERNARG_SEGMENT_PTR</td>
+<td><em>see above</em></td>
+</tr>
+<tr class="row-even"><td>452</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_DISPATCH_ID</td>
+<td><em>see above</em></td>
+</tr>
+<tr class="row-odd"><td>453</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_FLAT_SCRATCH_INIT</td>
+<td><em>see above</em></td>
+</tr>
+<tr class="row-even"><td>454</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_PRIVATE_SEGMENT
+_SIZE</td>
+<td><em>see above</em></td>
+</tr>
+<tr class="row-odd"><td>457:455</td>
+<td>3 bits</td>
+<td> </td>
+<td>Reserved, must be 0.</td>
+</tr>
+<tr class="row-even"><td>458</td>
+<td>1 bit</td>
+<td>ENABLE_WAVEFRONT_SIZE32</td>
+<td><dl class="first last docutils">
+<dt>GFX6-9</dt>
+<dd>Reserved, must be 0.</dd>
+<dt>GFX10</dt>
+<dd><ul class="first last simple">
+<li>If 0 execute in
+wavefront size 64 mode.</li>
+<li>If 1 execute in
+native wavefront size
+32 mode.</li>
+</ul>
+</dd>
+</dl>
+</td>
+</tr>
+<tr class="row-odd"><td>463:459</td>
+<td>5 bits</td>
+<td> </td>
+<td>Reserved, must be 0.</td>
+</tr>
+<tr class="row-even"><td>511:464</td>
+<td>6 bytes</td>
+<td> </td>
+<td>Reserved, must be 0.</td>
+</tr>
+<tr class="row-odd"><td>512</td>
+<td colspan="3"><strong>Total size 64 bytes.</strong></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx10-table">
+<caption><span class="caption-text">compute_pgm_rsrc1 for GFX6-GFX10</span><a class="headerlink" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx10-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="6%" />
+<col width="6%" />
+<col width="26%" />
+<col width="63%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Bits</th>
+<th class="head">Size</th>
+<th class="head">Field Name</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>5:0</td>
+<td>6 bits</td>
+<td>GRANULATED_WORKITEM_VGPR_COUNT</td>
+<td><p class="first">Number of vector register
+blocks used by each work-item;
+granularity is device
+specific:</p>
+<dl class="docutils">
+<dt>GFX6-GFX9</dt>
+<dd><ul class="first last simple">
+<li>vgprs_used 0..256</li>
+<li>max(0, ceil(vgprs_used / 4) - 1)</li>
+</ul>
+</dd>
+<dt>GFX10 (wavefront size 64)</dt>
+<dd><ul class="first last simple">
+<li>max_vgpr 1..256</li>
+<li>max(0, ceil(vgprs_used / 4) - 1)</li>
+</ul>
+</dd>
+<dt>GFX10 (wavefront size 32)</dt>
+<dd><ul class="first last simple">
+<li>max_vgpr 1..256</li>
+<li>max(0, ceil(vgprs_used / 8) - 1)</li>
+</ul>
+</dd>
+</dl>
+<p>Where vgprs_used is defined
+as the highest VGPR number
+explicitly referenced plus
+one.</p>
+<p>Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.VGPRS</span></code>.</p>
+<p class="last">The
+<a class="reference internal" href="#amdgpu-assembler"><span class="std std-ref">Assembler</span></a>
+calculates this
+automatically for the
+selected processor from
+values provided to the
+<cite>.amdhsa_kernel</cite> directive
+by the
+<cite>.amdhsa_next_free_vgpr</cite>
+nested directive (see
+<a class="reference internal" href="#amdhsa-kernel-directives-table"><span class="std std-ref">AMDHSA Kernel Assembler Directives</span></a>).</p>
+</td>
+</tr>
+<tr class="row-odd"><td>9:6</td>
+<td>4 bits</td>
+<td>GRANULATED_WAVEFRONT_SGPR_COUNT</td>
+<td><p class="first">Number of scalar register
+blocks used by a wavefront;
+granularity is device
+specific:</p>
+<dl class="docutils">
+<dt>GFX6-GFX8</dt>
+<dd><ul class="first last simple">
+<li>sgprs_used 0..112</li>
+<li>max(0, ceil(sgprs_used / 8) - 1)</li>
+</ul>
+</dd>
+<dt>GFX9</dt>
+<dd><ul class="first last simple">
+<li>sgprs_used 0..112</li>
+<li>2 * max(0, ceil(sgprs_used / 16) - 1)</li>
+</ul>
+</dd>
+<dt>GFX10</dt>
+<dd>Reserved, must be 0.
+(128 SGPRs always
+allocated.)</dd>
+</dl>
+<p>Where sgprs_used is
+defined as the highest
+SGPR number explicitly
+referenced plus one, plus
+a target-specific number
+of additional special
+SGPRs for VCC,
+FLAT_SCRATCH (GFX7+) and
+XNACK_MASK (GFX8+), and
+any additional
+target-specific
+limitations. It does not
+include the 16 SGPRs added
+if a trap handler is
+enabled.</p>
+<p>The target-specific
+limitations and special
+SGPR layout are defined in
+the hardware
+documentation, which can
+be found in the
+<a class="reference internal" href="#amdgpu-processors"><span class="std std-ref">Processors</span></a>
+table.</p>
+<p>Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.SGPRS</span></code>.</p>
+<p class="last">The
+<a class="reference internal" href="#amdgpu-assembler"><span class="std std-ref">Assembler</span></a>
+calculates this
+automatically for the
+selected processor from
+values provided to the
+<cite>.amdhsa_kernel</cite> directive
+by the
+<cite>.amdhsa_next_free_sgpr</cite>
+and <cite>.amdhsa_reserve_*</cite>
+nested directives (see
+<a class="reference internal" href="#amdhsa-kernel-directives-table"><span class="std std-ref">AMDHSA Kernel Assembler Directives</span></a>).</p>
+</td>
+</tr>
+<tr class="row-even"><td>11:10</td>
+<td>2 bits</td>
+<td>PRIORITY</td>
+<td><p class="first">Must be 0.</p>
+<p>Start executing wavefront
+at the specified priority.</p>
+<p class="last">CP is responsible for
+filling in
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.PRIORITY</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>13:12</td>
+<td>2 bits</td>
+<td>FLOAT_ROUND_MODE_32</td>
+<td><p class="first">Wavefront starts execution
+with specified rounding
+mode for single (32
+bit) floating point
+precision floating point
+operations.</p>
+<p>Floating point rounding
+mode values are defined in
+<a class="reference internal" href="#amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table"><span class="std std-ref">Floating Point Rounding Mode Enumeration Values</span></a>.</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.FLOAT_MODE</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>15:14</td>
+<td>2 bits</td>
+<td>FLOAT_ROUND_MODE_16_64</td>
+<td><p class="first">Wavefront starts execution
+with specified rounding
+denorm mode for half/double (16
+and 64 bit) floating point
+precision floating point
+operations.</p>
+<p>Floating point rounding
+mode values are defined in
+<a class="reference internal" href="#amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table"><span class="std std-ref">Floating Point Rounding Mode Enumeration Values</span></a>.</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.FLOAT_MODE</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>17:16</td>
+<td>2 bits</td>
+<td>FLOAT_DENORM_MODE_32</td>
+<td><p class="first">Wavefront starts execution
+with specified denorm mode
+for single (32
+bit) floating point
+precision floating point
+operations.</p>
+<p>Floating point denorm mode
+values are defined in
+<a class="reference internal" href="#amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table"><span class="std std-ref">Floating Point Denorm Mode Enumeration Values</span></a>.</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.FLOAT_MODE</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>19:18</td>
+<td>2 bits</td>
+<td>FLOAT_DENORM_MODE_16_64</td>
+<td><p class="first">Wavefront starts execution
+with specified denorm mode
+for half/double (16
+and 64 bit) floating point
+precision floating point
+operations.</p>
+<p>Floating point denorm mode
+values are defined in
+<a class="reference internal" href="#amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table"><span class="std std-ref">Floating Point Denorm Mode Enumeration Values</span></a>.</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.FLOAT_MODE</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>20</td>
+<td>1 bit</td>
+<td>PRIV</td>
+<td><p class="first">Must be 0.</p>
+<p>Start executing wavefront
+in privilege trap handler
+mode.</p>
+<p class="last">CP is responsible for
+filling in
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.PRIV</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>21</td>
+<td>1 bit</td>
+<td>ENABLE_DX10_CLAMP</td>
+<td><p class="first">Wavefront starts execution
+with DX10 clamp mode
+enabled. Used by the vector
+ALU to force DX10 style
+treatment of NaNâs (when
+set, clamp NaN to zero,
+otherwise pass NaN
+through).</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.DX10_CLAMP</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>22</td>
+<td>1 bit</td>
+<td>DEBUG_MODE</td>
+<td><p class="first">Must be 0.</p>
+<p>Start executing wavefront
+in single step mode.</p>
+<p class="last">CP is responsible for
+filling in
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.DEBUG_MODE</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>23</td>
+<td>1 bit</td>
+<td>ENABLE_IEEE_MODE</td>
+<td><p class="first">Wavefront starts execution
+with IEEE mode
+enabled. Floating point
+opcodes that support
+exception flag gathering
+will quiet and propagate
+signaling-NaN inputs per
+IEEE 754-2008. Min_dx10 and
+max_dx10 become IEEE
+754-2008 compliant due to
+signaling-NaN propagation
+and quieting.</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.IEEE_MODE</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>24</td>
+<td>1 bit</td>
+<td>BULKY</td>
+<td><p class="first">Must be 0.</p>
+<p>Only one work-group allowed
+to execute on a compute
+unit.</p>
+<p class="last">CP is responsible for
+filling in
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.BULKY</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>25</td>
+<td>1 bit</td>
+<td>CDBG_USER</td>
+<td><p class="first">Must be 0.</p>
+<p>Flag that can be used to
+control debugging code.</p>
+<p class="last">CP is responsible for
+filling in
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.CDBG_USER</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>26</td>
+<td>1 bit</td>
+<td>FP16_OVFL</td>
+<td><dl class="first last docutils">
+<dt>GFX6-GFX8</dt>
+<dd>Reserved, must be 0.</dd>
+<dt>GFX9-GFX10</dt>
+<dd><p class="first">Wavefront starts execution
+with specified fp16 overflow
+mode.</p>
+<ul class="simple">
+<li>If 0, fp16 overflow generates
++/-INF values.</li>
+<li>If 1, fp16 overflow that is the
+result of an +/-INF input value
+or divide by 0 produces a +/-INF,
+otherwise clamps computed
+overflow to +/-MAX_FP16 as
+appropriate.</li>
+</ul>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.FP16_OVFL</span></code>.</p>
+</dd>
+</dl>
+</td>
+</tr>
+<tr class="row-even"><td>28:27</td>
+<td>2 bits</td>
+<td> </td>
+<td>Reserved, must be 0.</td>
+</tr>
+<tr class="row-odd"><td>29</td>
+<td>1 bit</td>
+<td>WGP_MODE</td>
+<td><dl class="first last docutils">
+<dt>GFX6-GFX9</dt>
+<dd>Reserved, must be 0.</dd>
+<dt>GFX10</dt>
+<dd><ul class="first simple">
+<li>If 0 execute work-groups in
+CU wavefront execution mode.</li>
+<li>If 1 execute work-groups on
+in WGP wavefront execution mode.</li>
+</ul>
+<p>See <a class="reference internal" href="#amdgpu-amdhsa-memory-model"><span class="std std-ref">Memory Model</span></a>.</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.WGP_MODE</span></code>.</p>
+</dd>
+</dl>
+</td>
+</tr>
+<tr class="row-even"><td>30</td>
+<td>1 bit</td>
+<td>MEM_ORDERED</td>
+<td><dl class="first last docutils">
+<dt>GFX6-9</dt>
+<dd>Reserved, must be 0.</dd>
+<dt>GFX10</dt>
+<dd><p class="first">Controls the behavior of the
+waitcntâs vmcnt and vscnt
+counters.</p>
+<ul class="simple">
+<li>If 0 vmcnt reports completion
+of load and atomic with return
+out of order with sample
+instructions, and the vscnt
+reports the completion of
+store and atomic without
+return in order.</li>
+<li>If 1 vmcnt reports completion
+of load, atomic with return
+and sample instructions in
+order, and the vscnt reports
+the completion of store and
+atomic without return in order.</li>
+</ul>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.MEM_ORDERED</span></code>.</p>
+</dd>
+</dl>
+</td>
+</tr>
+<tr class="row-odd"><td>31</td>
+<td>1 bit</td>
+<td>FWD_PROGRESS</td>
+<td><dl class="first last docutils">
+<dt>GFX6-9</dt>
+<dd>Reserved, must be 0.</dd>
+<dt>GFX10</dt>
+<dd><ul class="first simple">
+<li>If 0 execute SIMD wavefronts
+using oldest first policy.</li>
+<li>If 1 execute SIMD wavefronts to
+ensure wavefronts will make some
+forward progress.</li>
+</ul>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC1.FWD_PROGRESS</span></code>.</p>
+</dd>
+</dl>
+</td>
+</tr>
+<tr class="row-even"><td>32</td>
+<td colspan="3"><strong>Total size 4 bytes</strong></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx10-table">
+<caption><span class="caption-text">compute_pgm_rsrc2 for GFX6-GFX10</span><a class="headerlink" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx10-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="6%" />
+<col width="6%" />
+<col width="26%" />
+<col width="63%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Bits</th>
+<th class="head">Size</th>
+<th class="head">Field Name</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>0</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_PRIVATE_SEGMENT
+_WAVEFRONT_OFFSET</td>
+<td><p class="first">Enable the setup of the
+SGPR wavefront scratch offset
+system register (see
+<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>).</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.SCRATCH_EN</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>5:1</td>
+<td>5 bits</td>
+<td>USER_SGPR_COUNT</td>
+<td><p class="first">The total number of SGPR
+user data registers
+requested. This number must
+match the number of user
+data registers enabled.</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.USER_SGPR</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>6</td>
+<td>1 bit</td>
+<td>ENABLE_TRAP_HANDLER</td>
+<td><p class="first">Must be 0.</p>
+<p class="last">This bit represents
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.TRAP_PRESENT</span></code>,
+which is set by the CP if
+the runtime has installed a
+trap handler.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>7</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_WORKGROUP_ID_X</td>
+<td><p class="first">Enable the setup of the
+system SGPR register for
+the work-group id in the X
+dimension (see
+<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>).</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.TGID_X_EN</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>8</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_WORKGROUP_ID_Y</td>
+<td><p class="first">Enable the setup of the
+system SGPR register for
+the work-group id in the Y
+dimension (see
+<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>).</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.TGID_Y_EN</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>9</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_WORKGROUP_ID_Z</td>
+<td><p class="first">Enable the setup of the
+system SGPR register for
+the work-group id in the Z
+dimension (see
+<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>).</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.TGID_Z_EN</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>10</td>
+<td>1 bit</td>
+<td>ENABLE_SGPR_WORKGROUP_INFO</td>
+<td><p class="first">Enable the setup of the
+system SGPR register for
+work-group information (see
+<a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>).</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.TGID_SIZE_EN</span></code>.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>12:11</td>
+<td>2 bits</td>
+<td>ENABLE_VGPR_WORKITEM_ID</td>
+<td><p class="first">Enable the setup of the
+VGPR system registers used
+for the work-item ID.
+<a class="reference internal" href="#amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table"><span class="std std-ref">System VGPR Work-Item ID Enumeration Values</span></a>
+defines the values.</p>
+<p class="last">Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.TIDIG_CMP_CNT</span></code>.</p>
+</td>
+</tr>
+<tr class="row-even"><td>13</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_ADDRESS_WATCH</td>
+<td><p class="first">Must be 0.</p>
+<p>Wavefront starts execution
+with address watch
+exceptions enabled which
+are generated when L1 has
+witnessed a thread access
+an <em>address of
+interest</em>.</p>
+<p class="last">CP is responsible for
+filling in the address
+watch bit in
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.EXCP_EN_MSB</span></code>
+according to what the
+runtime requests.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>14</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_MEMORY</td>
+<td><p class="first">Must be 0.</p>
+<p>Wavefront starts execution
+with memory violation
+exceptions exceptions
+enabled which are generated
+when a memory violation has
+occurred for this wavefront from
+L1 or LDS
+(write-to-read-only-memory,
+mis-aligned atomic, LDS
+address out of range,
+illegal address, etc.).</p>
+<p class="last">CP sets the memory
+violation bit in
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.EXCP_EN_MSB</span></code>
+according to what the
+runtime requests.</p>
+</td>
+</tr>
+<tr class="row-even"><td>23:15</td>
+<td>9 bits</td>
+<td>GRANULATED_LDS_SIZE</td>
+<td><p class="first">Must be 0.</p>
+<p>CP uses the rounded value
+from the dispatch packet,
+not this value, as the
+dispatch may contain
+dynamically allocated group
+segment memory. CP writes
+directly to
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.LDS_SIZE</span></code>.</p>
+<p>Amount of group segment
+(LDS) to allocate for each
+work-group. Granularity is
+device specific:</p>
+<dl class="last docutils">
+<dt>GFX6:</dt>
+<dd>roundup(lds-size / (64 * 4))</dd>
+<dt>GFX7-GFX10:</dt>
+<dd>roundup(lds-size / (128 * 4))</dd>
+</dl>
+</td>
+</tr>
+<tr class="row-odd"><td>24</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_IEEE_754_FP
+_INVALID_OPERATION</td>
+<td><p class="first">Wavefront starts execution
+with specified exceptions
+enabled.</p>
+<p>Used by CP to set up
+<code class="docutils literal notranslate"><span class="pre">COMPUTE_PGM_RSRC2.EXCP_EN</span></code>
+(set from bits 0..6).</p>
+<p class="last">IEEE 754 FP Invalid
+Operation</p>
+</td>
+</tr>
+<tr class="row-even"><td>25</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_FP_DENORMAL
+_SOURCE</td>
+<td>FP Denormal one or more
+input operands is a
+denormal number</td>
+</tr>
+<tr class="row-odd"><td>26</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_IEEE_754_FP
+_DIVISION_BY_ZERO</td>
+<td>IEEE 754 FP Division by
+Zero</td>
+</tr>
+<tr class="row-even"><td>27</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_IEEE_754_FP
+_OVERFLOW</td>
+<td>IEEE 754 FP FP Overflow</td>
+</tr>
+<tr class="row-odd"><td>28</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_IEEE_754_FP
+_UNDERFLOW</td>
+<td>IEEE 754 FP Underflow</td>
+</tr>
+<tr class="row-even"><td>29</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_IEEE_754_FP
+_INEXACT</td>
+<td>IEEE 754 FP Inexact</td>
+</tr>
+<tr class="row-odd"><td>30</td>
+<td>1 bit</td>
+<td>ENABLE_EXCEPTION_INT_DIVIDE_BY
+_ZERO</td>
+<td>Integer Division by Zero
+(rcp_iflag_f32 instruction
+only)</td>
+</tr>
+<tr class="row-even"><td>31</td>
+<td>1 bit</td>
+<td> </td>
+<td>Reserved, must be 0.</td>
+</tr>
+<tr class="row-odd"><td>32</td>
+<td colspan="3"><strong>Total size 4 bytes.</strong></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-compute-pgm-rsrc3-gfx10-table">
+<caption><span class="caption-text">compute_pgm_rsrc3 for GFX10</span><a class="headerlink" href="#amdgpu-amdhsa-compute-pgm-rsrc3-gfx10-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="6%" />
+<col width="6%" />
+<col width="26%" />
+<col width="63%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Bits</th>
+<th class="head">Size</th>
+<th class="head">Field Name</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>3:0</td>
+<td>4 bits</td>
+<td>SHARED_VGPR_COUNT</td>
+<td>Number of shared VGPRs for wavefront size 64. Granularity 8. Value 0-120.
+compute_pgm_rsrc1.vgprs + shared_vgpr_cnt cannot exceed 64.</td>
+</tr>
+<tr class="row-odd"><td>31:4</td>
+<td>28
+bits</td>
+<td> </td>
+<td>Reserved, must be 0.</td>
+</tr>
+<tr class="row-even"><td>32</td>
+<td colspan="3"><strong>Total size 4 bytes.</strong></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table">
+<caption><span class="caption-text">Floating Point Rounding Mode Enumeration Values</span><a class="headerlink" href="#amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="52%" />
+<col width="7%" />
+<col width="41%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Enumeration Name</th>
+<th class="head">Value</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>FLOAT_ROUND_MODE_NEAR_EVEN</td>
+<td>0</td>
+<td>Round Ties To Even</td>
+</tr>
+<tr class="row-odd"><td>FLOAT_ROUND_MODE_PLUS_INFINITY</td>
+<td>1</td>
+<td>Round Toward +infinity</td>
+</tr>
+<tr class="row-even"><td>FLOAT_ROUND_MODE_MINUS_INFINITY</td>
+<td>2</td>
+<td>Round Toward -infinity</td>
+</tr>
+<tr class="row-odd"><td>FLOAT_ROUND_MODE_ZERO</td>
+<td>3</td>
+<td>Round Toward 0</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table">
+<caption><span class="caption-text">Floating Point Denorm Mode Enumeration Values</span><a class="headerlink" href="#amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="52%" />
+<col width="7%" />
+<col width="41%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Enumeration Name</th>
+<th class="head">Value</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>FLOAT_DENORM_MODE_FLUSH_SRC_DST</td>
+<td>0</td>
+<td>Flush Source and Destination
+Denorms</td>
+</tr>
+<tr class="row-odd"><td>FLOAT_DENORM_MODE_FLUSH_DST</td>
+<td>1</td>
+<td>Flush Output Denorms</td>
+</tr>
+<tr class="row-even"><td>FLOAT_DENORM_MODE_FLUSH_SRC</td>
+<td>2</td>
+<td>Flush Source Denorms</td>
+</tr>
+<tr class="row-odd"><td>FLOAT_DENORM_MODE_FLUSH_NONE</td>
+<td>3</td>
+<td>No Flush</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table">
+<caption><span class="caption-text">System VGPR Work-Item ID Enumeration Values</span><a class="headerlink" href="#amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="55%" />
+<col width="7%" />
+<col width="38%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Enumeration Name</th>
+<th class="head">Value</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>SYSTEM_VGPR_WORKITEM_ID_X</td>
+<td>0</td>
+<td>Set work-item X dimension
+ID.</td>
+</tr>
+<tr class="row-odd"><td>SYSTEM_VGPR_WORKITEM_ID_X_Y</td>
+<td>1</td>
+<td>Set work-item X and Y
+dimensions ID.</td>
+</tr>
+<tr class="row-even"><td>SYSTEM_VGPR_WORKITEM_ID_X_Y_Z</td>
+<td>2</td>
+<td>Set work-item X, Y and Z
+dimensions ID.</td>
+</tr>
+<tr class="row-odd"><td>SYSTEM_VGPR_WORKITEM_ID_UNDEFINED</td>
+<td>3</td>
+<td>Undefined.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="initial-kernel-execution-state">
+<span id="amdgpu-amdhsa-initial-kernel-execution-state"></span><h4><a class="toc-backref" href="#id82">Initial Kernel Execution State</a><a class="headerlink" href="#initial-kernel-execution-state" title="Permalink to this headline">¶</a></h4>
+<p>This section defines the register state that will be set up by the packet
+processor prior to the start of execution of every wavefront. This is limited by
+the constraints of the hardware controllers of CP/ADC/SPI.</p>
+<p>The order of the SGPR registers is defined, but the compiler can specify which
+ones are actually setup in the kernel descriptor using the <code class="docutils literal notranslate"><span class="pre">enable_sgpr_*</span></code> bit
+fields (see <a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>). The register numbers used
+for enabled registers are dense starting at SGPR0: the first enabled register is
+SGPR0, the next enabled register is SGPR1 etc.; disabled registers do not have
+an SGPR number.</p>
+<p>The initial SGPRs comprise up to 16 User SRGPs that are set by CP and apply to
+all wavefronts of the grid. It is possible to specify more than 16 User SGPRs using
+the <code class="docutils literal notranslate"><span class="pre">enable_sgpr_*</span></code> bit fields, in which case only the first 16 are actually
+initialized. These are then immediately followed by the System SGPRs that are
+set up by ADC/SPI and can have different values for each wavefront of the grid
+dispatch.</p>
+<p>SGPR register initial state is defined in
+<a class="reference internal" href="#amdgpu-amdhsa-sgpr-register-set-up-order-table"><span class="std std-ref">SGPR Register Set Up Order</span></a>.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-sgpr-register-set-up-order-table">
+<caption><span class="caption-text">SGPR Register Set Up Order</span><a class="headerlink" href="#amdgpu-amdhsa-sgpr-register-set-up-order-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="13%" />
+<col width="33%" />
+<col width="8%" />
+<col width="46%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">SGPR Order</th>
+<th class="head">Name
+(kernel descriptor enable
+field)</th>
+<th class="head">Number
+of
+SGPRs</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>First</td>
+<td>Private Segment Buffer
+(enable_sgpr_private
+_segment_buffer)</td>
+<td>4</td>
+<td><p class="first">V# that can be used, together
+with Scratch Wavefront Offset
+as an offset, to access the
+private memory space using a
+segment address.</p>
+<p class="last">CP uses the value provided by
+the runtime.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>then</td>
+<td>Dispatch Ptr
+(enable_sgpr_dispatch_ptr)</td>
+<td>2</td>
+<td>64 bit address of AQL dispatch
+packet for kernel dispatch
+actually executing.</td>
+</tr>
+<tr class="row-even"><td>then</td>
+<td>Queue Ptr
+(enable_sgpr_queue_ptr)</td>
+<td>2</td>
+<td>64 bit address of amd_queue_t
+object for AQL queue on which
+the dispatch packet was
+queued.</td>
+</tr>
+<tr class="row-odd"><td>then</td>
+<td>Kernarg Segment Ptr
+(enable_sgpr_kernarg
+_segment_ptr)</td>
+<td>2</td>
+<td><p class="first">64 bit address of Kernarg
+segment. This is directly
+copied from the
+kernarg_address in the kernel
+dispatch packet.</p>
+<p class="last">Having CP load it once avoids
+loading it at the beginning of
+every wavefront.</p>
+</td>
+</tr>
+<tr class="row-even"><td>then</td>
+<td>Dispatch Id
+(enable_sgpr_dispatch_id)</td>
+<td>2</td>
+<td>64 bit Dispatch ID of the
+dispatch packet being
+executed.</td>
+</tr>
+<tr class="row-odd"><td>then</td>
+<td>Flat Scratch Init
+(enable_sgpr_flat_scratch
+_init)</td>
+<td>2</td>
+<td><p class="first">This is 2 SGPRs:</p>
+<dl class="last docutils">
+<dt>GFX6</dt>
+<dd>Not supported.</dd>
+<dt>GFX7-GFX8</dt>
+<dd><p class="first">The first SGPR is a 32 bit
+byte offset from
+<code class="docutils literal notranslate"><span class="pre">SH_HIDDEN_PRIVATE_BASE_VIMID</span></code>
+to per SPI base of memory
+for scratch for the queue
+executing the kernel
+dispatch. CP obtains this
+from the runtime. (The
+Scratch Segment Buffer base
+address is
+<code class="docutils literal notranslate"><span class="pre">SH_HIDDEN_PRIVATE_BASE_VIMID</span></code>
+plus this offset.) The value
+of Scratch Wavefront Offset must
+be added to this offset by
+the kernel machine code,
+right shifted by 8, and
+moved to the FLAT_SCRATCH_HI
+SGPR register.
+FLAT_SCRATCH_HI corresponds
+to SGPRn-4 on GFX7, and
+SGPRn-6 on GFX8 (where SGPRn
+is the highest numbered SGPR
+allocated to the wavefront).
+FLAT_SCRATCH_HI is
+multiplied by 256 (as it is
+in units of 256 bytes) and
+added to
+<code class="docutils literal notranslate"><span class="pre">SH_HIDDEN_PRIVATE_BASE_VIMID</span></code>
+to calculate the per wavefront
+FLAT SCRATCH BASE in flat
+memory instructions that
+access the scratch
+apperture.</p>
+<p class="last">The second SGPR is 32 bit
+byte size of a single
+work-itemâs scratch memory
+usage. CP obtains this from
+the runtime, and it is
+always a multiple of DWORD.
+CP checks that the value in
+the kernel dispatch packet
+Private Segment Byte Size is
+not larger, and requests the
+runtime to increase the
+queueâs scratch size if
+necessary. The kernel code
+must move it to
+FLAT_SCRATCH_LO which is
+SGPRn-3 on GFX7 and SGPRn-5
+on GFX8. FLAT_SCRATCH_LO is
+used as the FLAT SCRATCH
+SIZE in flat memory
+instructions. Having CP load
+it once avoids loading it at
+the beginning of every
+wavefront.</p>
+</dd>
+<dt>GFX9-GFX10</dt>
+<dd>This is the
+64 bit base address of the
+per SPI scratch backing
+memory managed by SPI for
+the queue executing the
+kernel dispatch. CP obtains
+this from the runtime (and
+divides it if there are
+multiple Shader Arrays each
+with its own SPI). The value
+of Scratch Wavefront Offset must
+be added by the kernel
+machine code and the result
+moved to the FLAT_SCRATCH
+SGPR which is SGPRn-6 and
+SGPRn-5. It is used as the
+FLAT SCRATCH BASE in flat
+memory instructions.</dd>
+</dl>
+</td>
+</tr>
+<tr class="row-even"><td>then</td>
+<td>Private Segment Size</td>
+<td>1</td>
+<td><p class="first">The 32 bit byte size of a
+(enable_sgpr_private single
+work-itemâs
+scratch_segment_size) memory
+allocation. This is the
+value from the kernel
+dispatch packet Private
+Segment Byte Size rounded up
+by CP to a multiple of
+DWORD.</p>
+<p>Having CP load it once avoids
+loading it at the beginning of
+every wavefront.</p>
+<p class="last">This is not used for
+GFX7-GFX8 since it is the same
+value as the second SGPR of
+Flat Scratch Init. However, it
+may be needed for GFX9-GFX10 which
+changes the meaning of the
+Flat Scratch Init value.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>then</td>
+<td>Grid Work-Group Count X
+(enable_sgpr_grid
+_workgroup_count_X)</td>
+<td>1</td>
+<td>32 bit count of the number of
+work-groups in the X dimension
+for the grid being
+executed. Computed from the
+fields in the kernel dispatch
+packet as ((grid_size.x +
+workgroup_size.x - 1) /
+workgroup_size.x).</td>
+</tr>
+<tr class="row-even"><td>then</td>
+<td>Grid Work-Group Count Y
+(enable_sgpr_grid
+_workgroup_count_Y &&
+less than 16 previous
+SGPRs)</td>
+<td>1</td>
+<td><p class="first">32 bit count of the number of
+work-groups in the Y dimension
+for the grid being
+executed. Computed from the
+fields in the kernel dispatch
+packet as ((grid_size.y +
+workgroup_size.y - 1) /
+workgroupSize.y).</p>
+<p class="last">Only initialized if <16
+previous SGPRs initialized.</p>
+</td>
+</tr>
+<tr class="row-odd"><td>then</td>
+<td>Grid Work-Group Count Z
+(enable_sgpr_grid
+_workgroup_count_Z &&
+less than 16 previous
+SGPRs)</td>
+<td>1</td>
+<td><p class="first">32 bit count of the number of
+work-groups in the Z dimension
+for the grid being
+executed. Computed from the
+fields in the kernel dispatch
+packet as ((grid_size.z +
+workgroup_size.z - 1) /
+workgroupSize.z).</p>
+<p class="last">Only initialized if <16
+previous SGPRs initialized.</p>
+</td>
+</tr>
+<tr class="row-even"><td>then</td>
+<td>Work-Group Id X
+(enable_sgpr_workgroup_id
+_X)</td>
+<td>1</td>
+<td>32 bit work-group id in X
+dimension of grid for
+wavefront.</td>
+</tr>
+<tr class="row-odd"><td>then</td>
+<td>Work-Group Id Y
+(enable_sgpr_workgroup_id
+_Y)</td>
+<td>1</td>
+<td>32 bit work-group id in Y
+dimension of grid for
+wavefront.</td>
+</tr>
+<tr class="row-even"><td>then</td>
+<td>Work-Group Id Z
+(enable_sgpr_workgroup_id
+_Z)</td>
+<td>1</td>
+<td>32 bit work-group id in Z
+dimension of grid for
+wavefront.</td>
+</tr>
+<tr class="row-odd"><td>then</td>
+<td>Work-Group Info
+(enable_sgpr_workgroup
+_info)</td>
+<td>1</td>
+<td>{first_wavefront, 14âb0000,
+ordered_append_term[10:0],
+threadgroup_size_in_wavefronts[5:0]}</td>
+</tr>
+<tr class="row-even"><td>then</td>
+<td>Scratch Wavefront Offset
+(enable_sgpr_private
+_segment_wavefront_offset)</td>
+<td>1</td>
+<td>32 bit byte offset from base
+of scratch base of queue
+executing the kernel
+dispatch. Must be used as an
+offset with Private
+segment address when using
+Scratch Segment Buffer. It
+must be used to set up FLAT
+SCRATCH for flat addressing
+(see
+<a class="reference internal" href="#amdgpu-amdhsa-flat-scratch"><span class="std std-ref">Flat Scratch</span></a>).</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>The order of the VGPR registers is defined, but the compiler can specify which
+ones are actually setup in the kernel descriptor using the <code class="docutils literal notranslate"><span class="pre">enable_vgpr*</span></code> bit
+fields (see <a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>). The register numbers used
+for enabled registers are dense starting at VGPR0: the first enabled register is
+VGPR0, the next enabled register is VGPR1 etc.; disabled registers do not have a
+VGPR number.</p>
+<p>VGPR register initial state is defined in
+<a class="reference internal" href="#amdgpu-amdhsa-vgpr-register-set-up-order-table"><span class="std std-ref">VGPR Register Set Up Order</span></a>.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-vgpr-register-set-up-order-table">
+<caption><span class="caption-text">VGPR Register Set Up Order</span><a class="headerlink" href="#amdgpu-amdhsa-vgpr-register-set-up-order-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="14%" />
+<col width="36%" />
+<col width="8%" />
+<col width="42%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">VGPR Order</th>
+<th class="head">Name
+(kernel descriptor enable
+field)</th>
+<th class="head">Number
+of
+VGPRs</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>First</td>
+<td>Work-Item Id X
+(Always initialized)</td>
+<td>1</td>
+<td>32 bit work item id in X
+dimension of work-group for
+wavefront lane.</td>
+</tr>
+<tr class="row-odd"><td>then</td>
+<td>Work-Item Id Y
+(enable_vgpr_workitem_id
+> 0)</td>
+<td>1</td>
+<td>32 bit work item id in Y
+dimension of work-group for
+wavefront lane.</td>
+</tr>
+<tr class="row-even"><td>then</td>
+<td>Work-Item Id Z
+(enable_vgpr_workitem_id
+> 1)</td>
+<td>1</td>
+<td>32 bit work item id in Z
+dimension of work-group for
+wavefront lane.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>The setting of registers is done by GPU CP/ADC/SPI hardware as follows:</p>
+<ol class="arabic simple">
+<li>SGPRs before the Work-Group Ids are set by CP using the 16 User Data
+registers.</li>
+<li>Work-group Id registers X, Y, Z are set by ADC which supports any
+combination including none.</li>
+<li>Scratch Wavefront Offset is set by SPI in a per wavefront basis which is why
+its value cannot included with the flat scratch init value which is per queue.</li>
+<li>The VGPRs are set by SPI which only supports specifying either (X), (X, Y)
+or (X, Y, Z).</li>
+</ol>
+<p>Flat Scratch register pair are adjacent SGRRs so they can be moved as a 64 bit
+value to the hardware required SGPRn-3 and SGPRn-4 respectively.</p>
+<p>The global segment can be accessed either using buffer instructions (GFX6 which
+has V# 64 bit address support), flat instructions (GFX7-GFX10), or global
+instructions (GFX9-GFX10).</p>
+<p>If buffer operations are used then the compiler can generate a V# with the
+following properties:</p>
+<ul class="simple">
+<li>base address of 0</li>
+<li>no swizzle</li>
+<li>ATC: 1 if IOMMU present (such as APU)</li>
+<li>ptr64: 1</li>
+<li>MTYPE set to support memory coherence that matches the runtime (such as CC for
+APU and NC for dGPU).</li>
+</ul>
+</div>
+<div class="section" id="kernel-prolog">
+<span id="amdgpu-amdhsa-kernel-prolog"></span><h4><a class="toc-backref" href="#id83">Kernel Prolog</a><a class="headerlink" href="#kernel-prolog" title="Permalink to this headline">¶</a></h4>
+<div class="section" id="m0">
+<span id="amdgpu-amdhsa-m0"></span><h5><a class="toc-backref" href="#id84">M0</a><a class="headerlink" href="#m0" title="Permalink to this headline">¶</a></h5>
+<dl class="docutils">
+<dt>GFX6-GFX8</dt>
+<dd>The M0 register must be initialized with a value at least the total LDS size
+if the kernel may access LDS via DS or flat operations. Total LDS size is
+available in dispatch packet. For M0, it is also possible to use maximum
+possible value of LDS for given target (0x7FFF for GFX6 and 0xFFFF for
+GFX7-GFX8).</dd>
+<dt>GFX9-GFX10</dt>
+<dd>The M0 register is not used for range checking LDS accesses and so does not
+need to be initialized in the prolog.</dd>
+</dl>
+</div>
+<div class="section" id="flat-scratch">
+<span id="amdgpu-amdhsa-flat-scratch"></span><h5><a class="toc-backref" href="#id85">Flat Scratch</a><a class="headerlink" href="#flat-scratch" title="Permalink to this headline">¶</a></h5>
+<p>If the kernel may use flat operations to access scratch memory, the prolog code
+must set up FLAT_SCRATCH register pair (FLAT_SCRATCH_LO/FLAT_SCRATCH_HI which
+are in SGPRn-4/SGPRn-3). Initialization uses Flat Scratch Init and Scratch Wavefront
+Offset SGPR registers (see <a class="reference internal" href="#amdgpu-amdhsa-initial-kernel-execution-state"><span class="std std-ref">Initial Kernel Execution State</span></a>):</p>
+<dl class="docutils">
+<dt>GFX6</dt>
+<dd>Flat scratch is not supported.</dd>
+<dt>GFX7-GFX8</dt>
+<dd><ol class="first last arabic simple">
+<li>The low word of Flat Scratch Init is 32 bit byte offset from
+<code class="docutils literal notranslate"><span class="pre">SH_HIDDEN_PRIVATE_BASE_VIMID</span></code> to the base of scratch backing memory
+being managed by SPI for the queue executing the kernel dispatch. This is
+the same value used in the Scratch Segment Buffer V# base address. The
+prolog must add the value of Scratch Wavefront Offset to get the wavefrontâs byte
+scratch backing memory offset from <code class="docutils literal notranslate"><span class="pre">SH_HIDDEN_PRIVATE_BASE_VIMID</span></code>. Since
+FLAT_SCRATCH_LO is in units of 256 bytes, the offset must be right shifted
+by 8 before moving into FLAT_SCRATCH_LO.</li>
+<li>The second word of Flat Scratch Init is 32 bit byte size of a single
+work-items scratch memory usage. This is directly loaded from the kernel
+dispatch packet Private Segment Byte Size and rounded up to a multiple of
+DWORD. Having CP load it once avoids loading it at the beginning of every
+wavefront. The prolog must move it to FLAT_SCRATCH_LO for use as FLAT SCRATCH
+SIZE.</li>
+</ol>
+</dd>
+<dt>GFX9-GFX10</dt>
+<dd>The Flat Scratch Init is the 64 bit address of the base of scratch backing
+memory being managed by SPI for the queue executing the kernel dispatch. The
+prolog must add the value of Scratch Wavefront Offset and moved to the FLAT_SCRATCH
+pair for use as the flat scratch base in flat memory instructions.</dd>
+</dl>
+</div>
+</div>
+<div class="section" id="memory-model">
+<span id="amdgpu-amdhsa-memory-model"></span><h4><a class="toc-backref" href="#id86">Memory Model</a><a class="headerlink" href="#memory-model" title="Permalink to this headline">¶</a></h4>
+<p>This section describes the mapping of LLVM memory model onto AMDGPU machine code
+(see <a class="reference internal" href="LangRef.html#memmodel"><span class="std std-ref">Memory Model for Concurrent Operations</span></a>). <em>The implementation is WIP.</em></p>
+<p>The AMDGPU backend supports the memory synchronization scopes specified in
+<a class="reference internal" href="#amdgpu-memory-scopes"><span class="std std-ref">Memory Scopes</span></a>.</p>
+<p>The code sequences used to implement the memory model are defined in table
+<a class="reference internal" href="#amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx10-table"><span class="std std-ref">AMDHSA Memory Model Code Sequences GFX6-GFX10</span></a>.</p>
+<p>The sequences specify the order of instructions that a single thread must
+execute. The <code class="docutils literal notranslate"><span class="pre">s_waitcnt</span></code> and <code class="docutils literal notranslate"><span class="pre">buffer_wbinvl1_vol</span></code> are defined with respect
+to other memory instructions executed by the same thread. This allows them to be
+moved earlier or later which can allow them to be combined with other instances
+of the same instruction, or hoisted/sunk out of loops to improve
+performance. Only the instructions related to the memory model are given;
+additional <code class="docutils literal notranslate"><span class="pre">s_waitcnt</span></code> instructions are required to ensure registers are
+defined before being used. These may be able to be combined with the memory
+model <code class="docutils literal notranslate"><span class="pre">s_waitcnt</span></code> instructions as described above.</p>
+<p>The AMDGPU backend supports the following memory models:</p>
+<blockquote>
+<div><dl class="docutils">
+<dt>HSA Memory Model <a class="reference internal" href="#hsa" id="id35">[HSA]</a></dt>
+<dd>The HSA memory model uses a single happens-before relation for all address
+spaces (see <a class="reference internal" href="#amdgpu-address-spaces"><span class="std std-ref">Address Spaces</span></a>).</dd>
+<dt>OpenCL Memory Model <a class="reference internal" href="#id47" id="id36">[OpenCL]</a></dt>
+<dd>The OpenCL memory model which has separate happens-before relations for the
+global and local address spaces. Only a fence specifying both global and
+local address space, and seq_cst instructions join the relationships. Since
+the LLVM <code class="docutils literal notranslate"><span class="pre">memfence</span></code> instruction does not allow an address space to be
+specified the OpenCL fence has to convervatively assume both local and
+global address space was specified. However, optimizations can often be
+done to eliminate the additional <code class="docutils literal notranslate"><span class="pre">s_waitcnt</span></code> instructions when there are
+no intervening memory instructions which access the corresponding address
+space. The code sequences in the table indicate what can be omitted for the
+OpenCL memory. The target triple environment is used to determine if the
+source language is OpenCL (see <a class="reference internal" href="#amdgpu-opencl"><span class="std std-ref">OpenCL</span></a>).</dd>
+</dl>
+</div></blockquote>
+<p><code class="docutils literal notranslate"><span class="pre">ds/flat_load/store/atomic</span></code> instructions to local memory are termed LDS
+operations.</p>
+<p><code class="docutils literal notranslate"><span class="pre">buffer/global/flat_load/store/atomic</span></code> instructions to global memory are
+termed vector memory operations.</p>
+<p>For GFX6-GFX9:</p>
+<ul class="simple">
+<li>Each agent has multiple shader arrays (SA).</li>
+<li>Each SA has multiple compute units (CU).</li>
+<li>Each CU has multiple SIMDs that execute wavefronts.</li>
+<li>The wavefronts for a single work-group are executed in the same CU but may be
+executed by different SIMDs.</li>
+<li>Each CU has a single LDS memory shared by the wavefronts of the work-groups
+executing on it.</li>
+<li>All LDS operations of a CU are performed as wavefront wide operations in a
+global order and involve no caching. Completion is reported to a wavefront in
+execution order.</li>
+<li>The LDS memory has multiple request queues shared by the SIMDs of a
+CU. Therefore, the LDS operations performed by different wavefronts of a work-group
+can be reordered relative to each other, which can result in reordering the
+visibility of vector memory operations with respect to LDS operations of other
+wavefronts in the same work-group. A <code class="docutils literal notranslate"><span class="pre">s_waitcnt</span> <span class="pre">lgkmcnt(0)</span></code> is required to
+ensure synchronization between LDS operations and vector memory operations
+between wavefronts of a work-group, but not between operations performed by the
+same wavefront.</li>
+<li>The vector memory operations are performed as wavefront wide operations and
+completion is reported to a wavefront in execution order. The exception is
+that for GFX7-GFX9 <code class="docutils literal notranslate"><span class="pre">flat_load/store/atomic</span></code> instructions can report out of
+vector memory order if they access LDS memory, and out of LDS operation order
+if they access global memory.</li>
+<li>The vector memory operations access a single vector L1 cache shared by all
+SIMDs a CU. Therefore, no special action is required for coherence between the
+lanes of a single wavefront, or for coherence between wavefronts in the same
+work-group. A <code class="docutils literal notranslate"><span class="pre">buffer_wbinvl1_vol</span></code> is required for coherence between wavefronts
+executing in different work-groups as they may be executing on different CUs.</li>
+<li>The scalar memory operations access a scalar L1 cache shared by all wavefronts
+on a group of CUs. The scalar and vector L1 caches are not coherent. However,
+scalar operations are used in a restricted way so do not impact the memory
+model. See <a class="reference internal" href="#amdgpu-amdhsa-memory-spaces"><span class="std std-ref">Memory Spaces</span></a>.</li>
+<li>The vector and scalar memory operations use an L2 cache shared by all CUs on
+the same agent.</li>
+<li>The L2 cache has independent channels to service disjoint ranges of virtual
+addresses.</li>
+<li>Each CU has a separate request queue per channel. Therefore, the vector and
+scalar memory operations performed by wavefronts executing in different work-groups
+(which may be executing on different CUs) of an agent can be reordered
+relative to each other. A <code class="docutils literal notranslate"><span class="pre">s_waitcnt</span> <span class="pre">vmcnt(0)</span></code> is required to ensure
+synchronization between vector memory operations of different CUs. It ensures a
+previous vector memory operation has completed before executing a subsequent
+vector memory or LDS operation and so can be used to meet the requirements of
+acquire and release.</li>
+<li>The L2 cache can be kept coherent with other agents on some targets, or ranges
+of virtual addresses can be set up to bypass it to ensure system coherence.</li>
+</ul>
+<p>For GFX10:</p>
+<ul class="simple">
+<li>Each agent has multiple shader arrays (SA).</li>
+<li>Each SA has multiple work-group processors (WGP).</li>
+<li>Each WGP has multiple compute units (CU).</li>
+<li>Each CU has multiple SIMDs that execute wavefronts.</li>
+<li>The wavefronts for a single work-group are executed in the same
+WGP. In CU wavefront execution mode the wavefronts may be executed by
+different SIMDs in the same CU. In WGP wavefront execution mode the
+wavefronts may be executed by different SIMDs in different CUs in the same
+WGP.</li>
+<li>Each WGP has a single LDS memory shared by the wavefronts of the work-groups
+executing on it.</li>
+<li>All LDS operations of a WGP are performed as wavefront wide operations in a
+global order and involve no caching. Completion is reported to a wavefront in
+execution order.</li>
+<li>The LDS memory has multiple request queues shared by the SIMDs of a
+WGP. Therefore, the LDS operations performed by different wavefronts of a work-group
+can be reordered relative to each other, which can result in reordering the
+visibility of vector memory operations with respect to LDS operations of other
+wavefronts in the same work-group. A <code class="docutils literal notranslate"><span class="pre">s_waitcnt</span> <span class="pre">lgkmcnt(0)</span></code> is required to
+ensure synchronization between LDS operations and vector memory operations
+between wavefronts of a work-group, but not between operations performed by the
+same wavefront.</li>
+<li>The vector memory operations are performed as wavefront wide operations.
+Completion of load/store/sample operations are reported to a wavefront in
+execution order of other load/store/sample operations performed by that
+wavefront.</li>
+<li>The vector memory operations access a vector L0 cache. There is a single L0
+cache per CU. Each SIMD of a CU accesses the same L0 cache.
+Therefore, no special action is required for coherence between the lanes of a
+single wavefront. However, a <code class="docutils literal notranslate"><span class="pre">BUFFER_GL0_INV</span></code> is required for coherence
+between wavefronts executing in the same work-group as they may be executing on
+SIMDs of different CUs that access different L0s. A <code class="docutils literal notranslate"><span class="pre">BUFFER_GL0_INV</span></code> is also
+required for coherence between wavefronts executing in different work-groups as
+they may be executing on different WGPs.</li>
+<li>The scalar memory operations access a scalar L0 cache shared by all wavefronts
+on a WGP. The scalar and vector L0 caches are not coherent. However, scalar
+operations are used in a restricted way so do not impact the memory model. See
+<a class="reference internal" href="#amdgpu-amdhsa-memory-spaces"><span class="std std-ref">Memory Spaces</span></a>.</li>
+<li>The vector and scalar memory L0 caches use an L1 cache shared by all WGPs on
+the same SA. Therefore, no special action is required for coherence between
+the wavefronts of a single work-group. However, a <code class="docutils literal notranslate"><span class="pre">BUFFER_GL1_INV</span></code> is
+required for coherence between wavefronts executing in different work-groups as
+they may be executing on different SAs that access different L1s.</li>
+<li>The L1 caches have independent quadrants to service disjoint ranges of virtual
+addresses.</li>
+<li>Each L0 cache has a separate request queue per L1 quadrant. Therefore, the
+vector and scalar memory operations performed by different wavefronts, whether
+executing in the same or different work-groups (which may be executing on
+different CUs accessing different L0s), can be reordered relative to each
+other. A <code class="docutils literal notranslate"><span class="pre">s_waitcnt</span> <span class="pre">vmcnt(0)</span> <span class="pre">&</span> <span class="pre">vscnt(0)</span></code> is required to ensure synchronization
+between vector memory operations of different wavefronts. It ensures a previous
+vector memory operation has completed before executing a subsequent vector
+memory or LDS operation and so can be used to meet the requirements of acquire,
+release and sequential consistency.</li>
+<li>The L1 caches use an L2 cache shared by all SAs on the same agent.</li>
+<li>The L2 cache has independent channels to service disjoint ranges of virtual
+addresses.</li>
+<li>Each L1 quadrant of a single SA accesses a different L2 channel. Each L1
+quadrant has a separate request queue per L2 channel. Therefore, the vector
+and scalar memory operations performed by wavefronts executing in different
+work-groups (which may be executing on different SAs) of an agent can be
+reordered relative to each other. A <code class="docutils literal notranslate"><span class="pre">s_waitcnt</span> <span class="pre">vmcnt(0)</span> <span class="pre">&</span> <span class="pre">vscnt(0)</span></code> is
+required to ensure synchronization between vector memory operations of
+different SAs. It ensures a previous vector memory operation has completed
+before executing a subsequent vector memory and so can be used to meet the
+requirements of acquire, release and sequential consistency.</li>
+<li>The L2 cache can be kept coherent with other agents on some targets, or ranges
+of virtual addresses can be set up to bypass it to ensure system coherence.</li>
+</ul>
+<p>Private address space uses <code class="docutils literal notranslate"><span class="pre">buffer_load/store</span></code> using the scratch V# (GFX6-GFX8),
+or <code class="docutils literal notranslate"><span class="pre">scratch_load/store</span></code> (GFX9-GFX10). Since only a single thread is accessing the
+memory, atomic memory orderings are not meaningful and all accesses are treated
+as non-atomic.</p>
+<p>Constant address space uses <code class="docutils literal notranslate"><span class="pre">buffer/global_load</span></code> instructions (or equivalent
+scalar memory instructions). Since the constant address space contents do not
+change during the execution of a kernel dispatch it is not legal to perform
+stores, and atomic memory orderings are not meaningful and all access are
+treated as non-atomic.</p>
+<p>A memory synchronization scope wider than work-group is not meaningful for the
+group (LDS) address space and is treated as work-group.</p>
+<p>The memory model does not support the region address space which is treated as
+non-atomic.</p>
+<p>Acquire memory ordering is not meaningful on store atomic instructions and is
+treated as non-atomic.</p>
+<p>Release memory ordering is not meaningful on load atomic instructions and is
+treated a non-atomic.</p>
+<p>Acquire-release memory ordering is not meaningful on load or store atomic
+instructions and is treated as acquire and release respectively.</p>
+<p>AMDGPU backend only uses scalar memory operations to access memory that is
+proven to not change during the execution of the kernel dispatch. This includes
+constant address space and global address space for program scope const
+variables. Therefore the kernel machine code does not have to maintain the
+scalar L1 cache to ensure it is coherent with the vector L1 cache. The scalar
+and vector L1 caches are invalidated between kernel dispatches by CP since
+constant address space data may change between kernel dispatch executions. See
+<a class="reference internal" href="#amdgpu-amdhsa-memory-spaces"><span class="std std-ref">Memory Spaces</span></a>.</p>
+<p>The one execption is if scalar writes are used to spill SGPR registers. In this
+case the AMDGPU backend ensures the memory location used to spill is never
+accessed by vector memory operations at the same time. If scalar writes are used
+then a <code class="docutils literal notranslate"><span class="pre">s_dcache_wb</span></code> is inserted before the <code class="docutils literal notranslate"><span class="pre">s_endpgm</span></code> and before a function
+return since the locations may be used for vector memory instructions by a
+future wavefront that uses the same scratch area, or a function call that creates a
+frame at the same address, respectively. There is no need for a <code class="docutils literal notranslate"><span class="pre">s_dcache_inv</span></code>
+as all scalar writes are write-before-read in the same thread.</p>
+<p>For GFX6-GFX9, scratch backing memory (which is used for the private address space)
+is accessed with MTYPE NC_NV (non-coherenent non-volatile). Since the private
+address space is only accessed by a single thread, and is always
+write-before-read, there is never a need to invalidate these entries from the L1
+cache. Hence all cache invalidates are done as <code class="docutils literal notranslate"><span class="pre">*_vol</span></code> to only invalidate the
+volatile cache lines.</p>
+<p>For GFX10, scratch backing memory (which is used for the private address space)
+is accessed with MTYPE NC (non-coherenent). Since the private address space is
+only accessed by a single thread, and is always write-before-read, there is
+never a need to invalidate these entries from the L0 or L1 caches.</p>
+<p>For GFX10, wavefronts are executed in native mode with in-order reporting of loads
+and sample instructions. In this mode vmcnt reports completion of load, atomic
+with return and sample instructions in order, and the vscnt reports the
+completion of store and atomic without return in order. See <code class="docutils literal notranslate"><span class="pre">MEM_ORDERED</span></code> field
+in <a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX10</span></a>.</p>
+<p>In GFX10, wavefronts can be executed in WGP or CU wavefront execution mode:</p>
+<ul class="simple">
+<li>In WGP wavefront execution mode the wavefronts of a work-group are executed
+on the SIMDs of both CUs of the WGP. Therefore, explicit management of the per
+CU L0 caches is required for work-group synchronization. Also accesses to L1 at
+work-group scope need to be expicitly ordered as the accesses from different
+CUs are not ordered.</li>
+<li>In CU wavefront execution mode the wavefronts of a work-group are executed on
+the SIMDs of a single CU of the WGP. Therefore, all global memory access by
+the work-group access the same L0 which in turn ensures L1 accesses are
+ordered and so do not require explicit management of the caches for
+work-group synchronization.</li>
+</ul>
+<p>See <code class="docutils literal notranslate"><span class="pre">WGP_MODE</span></code> field in <a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX10</span></a>
+and <a class="reference internal" href="#amdgpu-target-features"><span class="std std-ref">Target Features</span></a>.</p>
+<p>On dGPU the kernarg backing memory is accessed as UC (uncached) to avoid needing
+to invalidate the L2 cache. For GFX6-GFX9, this also causes it to be treated as
+non-volatile and so is not invalidated by <code class="docutils literal notranslate"><span class="pre">*_vol</span></code>. On APU it is accessed as CC
+(cache coherent) and so the L2 cache will be coherent with the CPU and other
+agents.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx10-table">
+<caption><span class="caption-text">AMDHSA Memory Model Code Sequences GFX6-GFX10</span><a class="headerlink" href="#amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx10-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="9%" />
+<col width="9%" />
+<col width="11%" />
+<col width="8%" />
+<col width="24%" />
+<col width="39%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">LLVM Instr</th>
+<th class="head">LLVM Memory
+Ordering</th>
+<th class="head">LLVM Memory
+Sync Scope</th>
+<th class="head">AMDGPU
+Address
+Space</th>
+<th class="head">AMDGPU Machine Code
+GFX6-9</th>
+<th class="head">AMDGPU Machine Code
+GFX10</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td colspan="6"><strong>Non-Atomic</strong></td>
+</tr>
+<tr class="row-odd"><td>load</td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+<li>private</li>
+<li>constant</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>!volatile & !nontemporal<ol class="arabic">
+<li>buffer/global/flat_load</li>
+</ol>
+</li>
+<li>volatile & !nontemporal<ol class="arabic">
+<li>buffer/global/flat_load
+glc=1</li>
+</ol>
+</li>
+<li>nontemporal<ol class="arabic">
+<li>buffer/global/flat_load
+glc=1 slc=1</li>
+</ol>
+</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>!volatile & !nontemporal<ol class="arabic">
+<li>buffer/global/flat_load</li>
+</ol>
+</li>
+<li>volatile & !nontemporal<ol class="arabic">
+<li>buffer/global/flat_load
+glc=1 dlc=1</li>
+</ol>
+</li>
+<li>nontemporal<ol class="arabic">
+<li>buffer/global/flat_load
+slc=1</li>
+</ol>
+</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>load</td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_load</li>
+</ol>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_load</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>store</td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+<li>private</li>
+<li>constant</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>!nontemporal<ol class="arabic">
+<li>buffer/global/flat_store</li>
+</ol>
+</li>
+<li>nontemporal<ol class="arabic">
+<li>buffer/global/flat_stote
+glc=1 slc=1</li>
+</ol>
+</li>
+</ul>
+</td>
+<td><ul class="first last">
+<li><p class="first">!nontemporal</p>
+<ol class="arabic simple">
+<li>buffer/global/flat_store</li>
+</ol>
+</li>
+<li><p class="first">nontemporal</p>
+<blockquote>
+<div><ol class="arabic simple">
+<li>buffer/global/flat_store
+slc=1</li>
+</ol>
+</div></blockquote>
+</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>store</td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_store</li>
+</ol>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_store</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td colspan="6"><strong>Unordered Atomic</strong></td>
+</tr>
+<tr class="row-even"><td>load atomic</td>
+<td>unordered</td>
+<td><em>any</em></td>
+<td><em>any</em></td>
+<td><em>Same as non-atomic</em>.</td>
+<td><em>Same as non-atomic</em>.</td>
+</tr>
+<tr class="row-odd"><td>store atomic</td>
+<td>unordered</td>
+<td><em>any</em></td>
+<td><em>any</em></td>
+<td><em>Same as non-atomic</em>.</td>
+<td><em>Same as non-atomic</em>.</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>unordered</td>
+<td><em>any</em></td>
+<td><em>any</em></td>
+<td><em>Same as monotonic
+atomic</em>.</td>
+<td><em>Same as monotonic
+atomic</em>.</td>
+</tr>
+<tr class="row-odd"><td colspan="6"><strong>Monotonic Atomic</strong></td>
+</tr>
+<tr class="row-even"><td>load atomic</td>
+<td>monotonic</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/flat_load</li>
+</ol>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/flat_load</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>load atomic</td>
+<td>monotonic</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/flat_load</li>
+</ol>
+</td>
+<td><ol class="first arabic simple">
+<li>buffer/global/flat_load
+glc=1</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit glc=1.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>load atomic</td>
+<td>monotonic</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_load</li>
+</ol>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_load</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>load atomic</td>
+<td>monotonic</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/flat_load
+glc=1</li>
+</ol>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/flat_load
+glc=1 dlc=1</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>store atomic</td>
+<td>monotonic</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/flat_store</li>
+</ol>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/flat_store</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>store atomic</td>
+<td>monotonic</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_store</li>
+</ol>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_store</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>monotonic</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/flat_atomic</li>
+</ol>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/flat_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>monotonic</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_atomic</li>
+</ol>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td colspan="6"><strong>Acquire Atomic</strong></td>
+</tr>
+<tr class="row-odd"><td>load atomic</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>local</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/ds/flat_load</li>
+</ol>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/ds/flat_load</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>load atomic</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/flat_load</li>
+</ol>
+</td>
+<td><ol class="first arabic simple">
+<li>buffer/global_load glc=1</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit glc=1.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="2">
+<li>s_waitcnt vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit.</li>
+<li>Must happen before
+the following buffer_gl0_inv
+and before any following
+global/generic
+load/load
+atomic/stote/store
+atomic/atomicrmw.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_gl0_inv</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit.</li>
+<li>Ensures that
+following
+loads will not see
+stale data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td>load atomic</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>ds_load</li>
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures any
+following global
+data read is no
+older than the load
+atomic value being
+acquired.</li>
+</ul>
+</div></blockquote>
+</td>
+<td><ol class="first arabic simple">
+<li>ds_load</li>
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen before
+the following buffer_gl0_inv
+and before any following
+global/generic load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures any
+following global
+data read is no
+older than the load
+atomic value being
+acquired.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_gl0_inv</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit.</li>
+<li>If OpenCL, omit.</li>
+<li>Ensures that
+following
+loads will not see
+stale data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>load atomic</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>flat_load</li>
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures any
+following global
+data read is no
+older than the load
+atomic value being
+acquired.</li>
+</ul>
+</div></blockquote>
+</td>
+<td><ol class="first arabic simple">
+<li>flat_load glc=1</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit glc=1.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="2">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit vmcnt.</li>
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Must happen before
+the following
+buffer_gl0_inv and any
+following global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures any
+following global
+data read is no
+older than the load
+atomic value being
+acquired.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_gl0_inv</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit.</li>
+<li>Ensures that
+following
+loads will not see
+stale data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td>load atomic</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>buffer/global/flat_load
+glc=1</li>
+<li>s_waitcnt vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>Must happen before
+following
+buffer_wbinvl1_vol.</li>
+<li>Ensures the load
+has completed
+before invalidating
+the cache.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_wbinvl1_vol</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/atomicrmw.</li>
+<li>Ensures that
+following
+loads will not see
+stale global data.</li>
+</ul>
+</div></blockquote>
+</td>
+<td><ol class="first arabic simple">
+<li>buffer/global_load
+glc=1 dlc=1</li>
+<li>s_waitcnt vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>Must happen before
+following
+buffer_gl*_inv.</li>
+<li>Ensures the load
+has completed
+before invalidating
+the caches.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_gl0_inv;
+buffer_gl1_inv</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/atomicrmw.</li>
+<li>Ensures that
+following
+loads will not see
+stale global data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>load atomic</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>flat_load glc=1</li>
+<li>s_waitcnt vmcnt(0) &
+lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL omit
+lgkmcnt(0).</li>
+<li>Must happen before
+following
+buffer_wbinvl1_vol.</li>
+<li>Ensures the flat_load
+has completed
+before invalidating
+the cache.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_wbinvl1_vol</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data.</li>
+</ul>
+</div></blockquote>
+</td>
+<td><ol class="first arabic simple">
+<li>flat_load glc=1 dlc=1</li>
+<li>s_waitcnt vmcnt(0) &
+lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL omit
+lgkmcnt(0).</li>
+<li>Must happen before
+following
+buffer_gl*_invl.</li>
+<li>Ensures the flat_load
+has completed
+before invalidating
+the caches.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_gl0_inv;
+buffer_gl1_inv</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>local</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/ds/flat_atomic</li>
+</ol>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/ds/flat_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/flat_atomic</li>
+</ol>
+</td>
+<td><ol class="first arabic simple">
+<li>buffer/global_atomic</li>
+<li>s_waitcnt vm/vscnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit.</li>
+<li>Use vmcnt if atomic with
+return and vscnt if atomic
+with no-return.</li>
+<li>Must happen before
+the following buffer_gl0_inv
+and before any following
+global/generic
+load/load
+atomic/stote/store
+atomic/atomicrmw.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_gl0_inv</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit.</li>
+<li>Ensures that
+following
+loads will not see
+stale data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>ds_atomic</li>
+<li>waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures any
+following global
+data read is no
+older than the
+atomicrmw value
+being acquired.</li>
+</ul>
+</div></blockquote>
+</td>
+<td><ol class="first arabic simple">
+<li>ds_atomic</li>
+<li>waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen before
+the following
+buffer_gl0_inv.</li>
+<li>Ensures any
+following global
+data read is no
+older than the
+atomicrmw value
+being acquired.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_gl0_inv</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL omit.</li>
+<li>Ensures that
+following
+loads will not see
+stale data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>flat_atomic</li>
+<li>waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures any
+following global
+data read is no
+older than the
+atomicrmw value
+being acquired.</li>
+</ul>
+</div></blockquote>
+</td>
+<td><ol class="first arabic simple">
+<li>flat_atomic</li>
+<li>waitcnt lgkmcnt(0) &
+vm/vscnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit vm/vscnt.</li>
+<li>If OpenCL, omit
+waitcnt lgkmcnt(0)..</li>
+<li>Use vmcnt if atomic with
+return and vscnt if atomic
+with no-return.
+waitcnt lgkmcnt(0).</li>
+<li>Must happen before
+the following
+buffer_gl0_inv.</li>
+<li>Ensures any
+following global
+data read is no
+older than the
+atomicrmw value
+being acquired.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_gl0_inv</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit.</li>
+<li>Ensures that
+following
+loads will not see
+stale data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>buffer/global/flat_atomic</li>
+<li>s_waitcnt vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>Must happen before
+following
+buffer_wbinvl1_vol.</li>
+<li>Ensures the
+atomicrmw has
+completed before
+invalidating the
+cache.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_wbinvl1_vol</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data.</li>
+</ul>
+</div></blockquote>
+</td>
+<td><ol class="first arabic simple">
+<li>buffer/global_atomic</li>
+<li>s_waitcnt vm/vscnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>Use vmcnt if atomic with
+return and vscnt if atomic
+with no-return.
+waitcnt lgkmcnt(0).</li>
+<li>Must happen before
+following
+buffer_gl*_inv.</li>
+<li>Ensures the
+atomicrmw has
+completed before
+invalidating the
+caches.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_gl0_inv;
+buffer_gl1_inv</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>flat_atomic</li>
+<li>s_waitcnt vmcnt(0) &
+lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Must happen before
+following
+buffer_wbinvl1_vol.</li>
+<li>Ensures the
+atomicrmw has
+completed before
+invalidating the
+cache.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_wbinvl1_vol</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data.</li>
+</ul>
+</div></blockquote>
+</td>
+<td><ol class="first arabic simple">
+<li>flat_atomic</li>
+<li>s_waitcnt vm/vscnt(0) &
+lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Use vmcnt if atomic with
+return and vscnt if atomic
+with no-return.</li>
+<li>Must happen before
+following
+buffer_gl*_inv.</li>
+<li>Ensures the
+atomicrmw has
+completed before
+invalidating the
+caches.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_gl0_inv;
+buffer_gl1_inv</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td>fence</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-even"><td>fence</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL and
+address space is
+not generic, omit.</li>
+<li>However, since LLVM
+currently has no
+address space on
+the fence need to
+conservatively
+always generate. If
+fence had an
+address space then
+set to address
+space of OpenCL
+fence flag, or to
+generic if both
+local and global
+flags are
+specified.</li>
+<li>Must happen after
+any preceding
+local/generic load
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+fence-paired-atomic).</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures any
+following global
+data read is no
+older than the
+value read by the
+fence-paired-atomic.</li>
+</ul>
+</div></blockquote>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0) & vscnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit vmcnt and
+vscnt.</li>
+<li>If OpenCL and
+address space is
+not generic, omit
+lgkmcnt(0).</li>
+<li>If OpenCL and
+address space is
+local, omit
+vmcnt(0) and vscnt(0).</li>
+<li>However, since LLVM
+currently has no
+address space on
+the fence need to
+conservatively
+always generate. If
+fence had an
+address space then
+set to address
+space of OpenCL
+fence flag, or to
+generic if both
+local and global
+flags are
+specified.</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0), s_waitcnt
+vscnt(0) and s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic load
+atomic/
+atomicrmw-with-return-value
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+fence-paired-atomic).</li>
+<li>s_waitcnt vscnt(0)
+must happen after
+any preceding
+global/generic
+atomicrmw-no-return-value
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+fence-paired-atomic).</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic load
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+fence-paired-atomic).</li>
+<li>Must happen before
+the following
+buffer_gl0_inv.</li>
+<li>Ensures that the
+fence-paired atomic
+has completed
+before invalidating
+the
+cache. Therefore
+any following
+locations read must
+be no older than
+the value read by
+the
+fence-paired-atomic.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_gl0_inv</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit.</li>
+<li>Ensures that
+following
+loads will not see
+stale data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td>fence</td>
+<td>acquire</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL and
+address space is
+not generic, omit
+lgkmcnt(0).</li>
+<li>However, since LLVM
+currently has no
+address space on
+the fence need to
+conservatively
+always generate
+(see comment for
+previous fence).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and
+s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic load
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+fence-paired-atomic).</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic load
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+fence-paired-atomic).</li>
+<li>Must happen before
+the following
+buffer_wbinvl1_vol.</li>
+<li>Ensures that the
+fence-paired atomic
+has completed
+before invalidating
+the
+cache. Therefore
+any following
+locations read must
+be no older than
+the value read by
+the
+fence-paired-atomic.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="2">
+<li>buffer_wbinvl1_vol</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before any
+following global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data.</li>
+</ul>
+</div></blockquote>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0) & vscnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL and
+address space is
+not generic, omit
+lgkmcnt(0).</li>
+<li>If OpenCL and
+address space is
+local, omit
+vmcnt(0) and vscnt(0).</li>
+<li>However, since LLVM
+currently has no
+address space on
+the fence need to
+conservatively
+always generate
+(see comment for
+previous fence).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0), s_waitcnt
+vscnt(0) and s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic load
+atomic/
+atomicrmw-with-return-value
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+fence-paired-atomic).</li>
+<li>s_waitcnt vscnt(0)
+must happen after
+any preceding
+global/generic
+atomicrmw-no-return-value
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+fence-paired-atomic).</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic load
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+fence-paired-atomic).</li>
+<li>Must happen before
+the following
+buffer_gl*_inv.</li>
+<li>Ensures that the
+fence-paired atomic
+has completed
+before invalidating
+the
+caches. Therefore
+any following
+locations read must
+be no older than
+the value read by
+the
+fence-paired-atomic.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="2">
+<li>buffer_gl0_inv;
+buffer_gl1_inv</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before any
+following global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td colspan="6"><strong>Release Atomic</strong></td>
+</tr>
+<tr class="row-odd"><td>store atomic</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>local</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/ds/flat_store</li>
+</ol>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/ds/flat_store</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>store atomic</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+store.</li>
+<li>Ensures that all
+memory operations
+to local have
+completed before
+performing the
+store that is being
+released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>buffer/global/flat_store</li>
+</ol>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0) & vscnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit vmcnt and
+vscnt.</li>
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0), s_waitcnt
+vscnt(0) and s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic load/load
+atomic/
+atomicrmw-with-return-value.</li>
+<li>s_waitcnt vscnt(0)
+must happen after
+any preceding
+global/generic
+store/store
+atomic/
+atomicrmw-no-return-value.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+store.</li>
+<li>Ensures that all
+memory operations
+have
+completed before
+performing the
+store that is being
+released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>buffer/global_store</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>store atomic</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_store</li>
+</ol>
+</td>
+<td><ol class="first arabic simple">
+<li>waitcnt vmcnt(0) & vscnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit.</li>
+<li>If OpenCL, omit.</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and s_waitcnt
+vscnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic load/load
+atomic/
+atomicrmw-with-return-value.</li>
+<li>s_waitcnt vscnt(0)
+must happen after
+any preceding
+global/generic
+store/store atomic/
+atomicrmw-no-return-value.</li>
+<li>Must happen before
+the following
+store.</li>
+<li>Ensures that all
+global memory
+operations have
+completed before
+performing the
+store that is being
+released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>ds_store</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>store atomic</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+store.</li>
+<li>Ensures that all
+memory operations
+to local have
+completed before
+performing the
+store that is being
+released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>flat_store</li>
+</ol>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0) & vscnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit vmcnt and
+vscnt.</li>
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0), s_waitcnt
+vscnt(0) and s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic load/load
+atomic/
+atomicrmw-with-return-value.</li>
+<li>s_waitcnt vscnt(0)
+must happen after
+any preceding
+global/generic
+store/store
+atomic/
+atomicrmw-no-return-value.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic load/store/load
+atomic/store atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+store.</li>
+<li>Ensures that all
+memory operations
+have
+completed before
+performing the
+store that is being
+released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>flat_store</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>store atomic</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and
+s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+store.</li>
+<li>Ensures that all
+memory operations
+to memory have
+completed before
+performing the
+store that is being
+released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>buffer/global/ds/flat_store</li>
+</ol>
+</td>
+<td><blockquote class="first">
+<div><ol class="arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0) & vscnt(0)</li>
+</ol>
+<ul class="simple">
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0), s_waitcnt vscnt(0)
+and s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/load
+atomic/
+atomicrmw-with-return-value.</li>
+<li>s_waitcnt vscnt(0)
+must happen after
+any preceding
+global/generic
+store/store atomic/
+atomicrmw-no-return-value.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+store.</li>
+<li>Ensures that all
+memory operations
+to memory have
+completed before
+performing the
+store that is being
+released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>buffer/global/ds/flat_store</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>local</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/ds/flat_atomic</li>
+</ol>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/ds/flat_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to local have
+completed before
+performing the
+atomicrmw that is
+being released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>buffer/global/flat_atomic</li>
+</ol>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0) & vscnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit vmcnt and
+vscnt.</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0), s_waitcnt
+vscnt(0) and s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic load/load
+atomic/
+atomicrmw-with-return-value.</li>
+<li>s_waitcnt vscnt(0)
+must happen after
+any preceding
+global/generic
+store/store
+atomic/
+atomicrmw-no-return-value.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+have
+completed before
+performing the
+atomicrmw that is
+being released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>buffer/global_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>ds_atomic</li>
+</ol>
+</td>
+<td><ol class="first arabic simple">
+<li>waitcnt vmcnt(0) & vscnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit.</li>
+<li>If OpenCL, omit.</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and s_waitcnt
+vscnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic load/load
+atomic/
+atomicrmw-with-return-value.</li>
+<li>s_waitcnt vscnt(0)
+must happen after
+any preceding
+global/generic
+store/store atomic/
+atomicrmw-no-return-value.</li>
+<li>Must happen before
+the following
+store.</li>
+<li>Ensures that all
+global memory
+operations have
+completed before
+performing the
+store that is being
+released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>ds_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to local have
+completed before
+performing the
+atomicrmw that is
+being released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>flat_atomic</li>
+</ol>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0) & vscnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit vmcnt and
+vscnt.</li>
+<li>If OpenCL, omit
+waitcnt lgkmcnt(0).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0), s_waitcnt
+vscnt(0) and s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic load/load
+atomic/
+atomicrmw-with-return-value.</li>
+<li>s_waitcnt vscnt(0)
+must happen after
+any preceding
+global/generic
+store/store
+atomic/
+atomicrmw-no-return-value.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic load/store/load
+atomic/store atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+have
+completed before
+performing the
+atomicrmw that is
+being released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>flat_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and
+s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to global and local
+have completed
+before performing
+the atomicrmw that
+is being released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>buffer/global/ds/flat_atomic</li>
+</ol>
+</td>
+<td><ol class="first arabic simple">
+<li><dl class="first docutils">
+<dt>s_waitcnt lkkmcnt(0) &</dt>
+<dd>vmcnt(0) & vscnt(0)</dd>
+</dl>
+</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0), s_waitcnt
+vscnt(0) and s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/load atomic/
+atomicrmw-with-return-value.</li>
+<li>s_waitcnt vscnt(0)
+must happen after
+any preceding
+global/generic
+store/store atomic/
+atomicrmw-no-return-value.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to global and local
+have completed
+before performing
+the atomicrmw that
+is being released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>buffer/global/ds/flat_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>fence</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-even"><td>fence</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL and
+address space is
+not generic, omit.</li>
+<li>However, since LLVM
+currently has no
+address space on
+the fence need to
+conservatively
+always generate. If
+fence had an
+address space then
+set to address
+space of OpenCL
+fence flag, or to
+generic if both
+local and global
+flags are
+specified.</li>
+<li>Must happen after
+any preceding
+local/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+any following store
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+fence-paired-atomic).</li>
+<li>Ensures that all
+memory operations
+to local have
+completed before
+performing the
+following
+fence-paired-atomic.</li>
+</ul>
+</div></blockquote>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0) & vscnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit vmcnt and
+vscnt.</li>
+<li>If OpenCL and
+address space is
+not generic, omit
+lgkmcnt(0).</li>
+<li>If OpenCL and
+address space is
+local, omit
+vmcnt(0) and vscnt(0).</li>
+<li>However, since LLVM
+currently has no
+address space on
+the fence need to
+conservatively
+always generate. If
+fence had an
+address space then
+set to address
+space of OpenCL
+fence flag, or to
+generic if both
+local and global
+flags are
+specified.</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0), s_waitcnt
+vscnt(0) and s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/load
+atomic/
+atomicrmw-with-return-value.</li>
+<li>s_waitcnt vscnt(0)
+must happen after
+any preceding
+global/generic
+store/store atomic/
+atomicrmw-no-return-value.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store atomic/
+atomicrmw.</li>
+<li>Must happen before
+any following store
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+fence-paired-atomic).</li>
+<li>Ensures that all
+memory operations
+have
+completed before
+performing the
+following
+fence-paired-atomic.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td>fence</td>
+<td>release</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL and
+address space is
+not generic, omit
+lgkmcnt(0).</li>
+<li>If OpenCL and
+address space is
+local, omit
+vmcnt(0).</li>
+<li>However, since LLVM
+currently has no
+address space on
+the fence need to
+conservatively
+always generate. If
+fence had an
+address space then
+set to address
+space of OpenCL
+fence flag, or to
+generic if both
+local and global
+flags are
+specified.</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and
+s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+any following store
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+fence-paired-atomic).</li>
+<li>Ensures that all
+memory operations
+have
+completed before
+performing the
+following
+fence-paired-atomic.</li>
+</ul>
+</div></blockquote>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0) & vscnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL and
+address space is
+not generic, omit
+lgkmcnt(0).</li>
+<li>If OpenCL and
+address space is
+local, omit
+vmcnt(0) and vscnt(0).</li>
+<li>However, since LLVM
+currently has no
+address space on
+the fence need to
+conservatively
+always generate. If
+fence had an
+address space then
+set to address
+space of OpenCL
+fence flag, or to
+generic if both
+local and global
+flags are
+specified.</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0), s_waitcnt
+vscnt(0) and s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/load atomic/
+atomicrmw-with-return-value.</li>
+<li>s_waitcnt vscnt(0)
+must happen after
+any preceding
+global/generic
+store/store atomic/
+atomicrmw-no-return-value.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+any following store
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+fence-paired-atomic).</li>
+<li>Ensures that all
+memory operations
+have
+completed before
+performing the
+following
+fence-paired-atomic.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td colspan="6"><strong>Acquire-Release Atomic</strong></td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>local</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/ds/flat_atomic</li>
+</ol>
+</td>
+<td><ol class="first last arabic simple">
+<li>buffer/global/ds/flat_atomic</li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to local have
+completed before
+performing the
+atomicrmw that is
+being released.</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li>buffer/global/flat_atomic</li>
+</ol>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0) & vscnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit vmcnt and
+vscnt.</li>
+<li>If OpenCL, omit
+s_waitcnt lgkmcnt(0).</li>
+<li>Must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0), s_waitcnt
+vscnt(0) and s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic load/load
+atomic/
+atomicrmw-with-return-value.</li>
+<li>s_waitcnt vscnt(0)
+must happen after
+any preceding
+global/generic
+store/store
+atomic/
+atomicrmw-no-return-value.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic load/store/load
+atomic/store atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+have
+completed before
+performing the
+atomicrmw that is
+being released.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="2">
+<li>buffer/global_atomic</li>
+<li>s_waitcnt vm/vscnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit vm/vscnt.</li>
+<li>Use vmcnt if atomic with
+return and vscnt if atomic
+with no-return.
+waitcnt lgkmcnt(0).</li>
+<li>Must happen before
+the following
+buffer_gl0_inv.</li>
+<li>Ensures any
+following global
+data read is no
+older than the
+atomicrmw value
+being acquired.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="4">
+<li>buffer_gl0_inv</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit.</li>
+<li>Ensures that
+following
+loads will not see
+stale data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>ds_atomic</li>
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures any
+following global
+data read is no
+older than the load
+atomic value being
+acquired.</li>
+</ul>
+</div></blockquote>
+</td>
+<td><ol class="first arabic simple">
+<li>waitcnt vmcnt(0) & vscnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit.</li>
+<li>If OpenCL, omit.</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and s_waitcnt
+vscnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic load/load
+atomic/
+atomicrmw-with-return-value.</li>
+<li>s_waitcnt vscnt(0)
+must happen after
+any preceding
+global/generic
+store/store atomic/
+atomicrmw-no-return-value.</li>
+<li>Must happen before
+the following
+store.</li>
+<li>Ensures that all
+global memory
+operations have
+completed before
+performing the
+store that is being
+released.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="2">
+<li>ds_atomic</li>
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen before
+the following
+buffer_gl0_inv.</li>
+<li>Ensures any
+following global
+data read is no
+older than the load
+atomic value being
+acquired.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="4">
+<li>buffer_gl0_inv</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit.</li>
+<li>If OpenCL omit.</li>
+<li>Ensures that
+following
+loads will not see
+stale data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to local have
+completed before
+performing the
+atomicrmw that is
+being released.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="2">
+<li>flat_atomic</li>
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL, omit.</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures any
+following global
+data read is no
+older than the load
+atomic value being
+acquired.</li>
+</ul>
+</div></blockquote>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0) & vscnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit vmcnt and
+vscnt.</li>
+<li>If OpenCL, omit
+waitcnt lgkmcnt(0).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0), s_waitcnt
+vscnt(0) and s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic load/load
+atomic/
+atomicrmw-with-return-value.</li>
+<li>s_waitcnt vscnt(0)
+must happen after
+any preceding
+global/generic
+store/store
+atomic/
+atomicrmw-no-return-value.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic load/store/load
+atomic/store atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+have
+completed before
+performing the
+atomicrmw that is
+being released.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="2">
+<li>flat_atomic</li>
+<li>s_waitcnt lgkmcnt(0) &
+vm/vscnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit vm/vscnt.</li>
+<li>If OpenCL, omit
+waitcnt lgkmcnt(0).</li>
+<li>Must happen before
+the following
+buffer_gl0_inv.</li>
+<li>Ensures any
+following global
+data read is no
+older than the load
+atomic value being
+acquired.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_gl0_inv</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit.</li>
+<li>Ensures that
+following
+loads will not see
+stale data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and
+s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to global have
+completed before
+performing the
+atomicrmw that is
+being released.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="2">
+<li>buffer/global/flat_atomic</li>
+<li>s_waitcnt vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>Must happen before
+following
+buffer_wbinvl1_vol.</li>
+<li>Ensures the
+atomicrmw has
+completed before
+invalidating the
+cache.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="4">
+<li>buffer_wbinvl1_vol</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data.</li>
+</ul>
+</div></blockquote>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0) & vscnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0), s_waitcnt
+vscnt(0) and s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/load atomic/
+atomicrmw-with-return-value.</li>
+<li>s_waitcnt vscnt(0)
+must happen after
+any preceding
+global/generic
+store/store atomic/
+atomicrmw-no-return-value.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to global have
+completed before
+performing the
+atomicrmw that is
+being released.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="2">
+<li>buffer/global_atomic</li>
+<li>s_waitcnt vm/vscnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>Use vmcnt if atomic with
+return and vscnt if atomic
+with no-return.
+waitcnt lgkmcnt(0).</li>
+<li>Must happen before
+following
+buffer_gl*_inv.</li>
+<li>Ensures the
+atomicrmw has
+completed before
+invalidating the
+caches.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="4">
+<li>buffer_gl0_inv;
+buffer_gl1_inv</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and
+s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to global have
+completed before
+performing the
+atomicrmw that is
+being released.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="2">
+<li>flat_atomic</li>
+<li>s_waitcnt vmcnt(0) &
+lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Must happen before
+following
+buffer_wbinvl1_vol.</li>
+<li>Ensures the
+atomicrmw has
+completed before
+invalidating the
+cache.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="4">
+<li>buffer_wbinvl1_vol</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data.</li>
+</ul>
+</div></blockquote>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0) & vscnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0), s_waitcnt
+vscnt(0) and s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/load atomic
+atomicrmw-with-return-value.</li>
+<li>s_waitcnt vscnt(0)
+must happen after
+any preceding
+global/generic
+store/store atomic/
+atomicrmw-no-return-value.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+atomicrmw.</li>
+<li>Ensures that all
+memory operations
+have
+completed before
+performing the
+atomicrmw that is
+being released.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="2">
+<li>flat_atomic</li>
+<li>s_waitcnt vm/vscnt(0) &
+lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL, omit
+lgkmcnt(0).</li>
+<li>Use vmcnt if atomic with
+return and vscnt if atomic
+with no-return.</li>
+<li>Must happen before
+following
+buffer_gl*_inv.</li>
+<li>Ensures the
+atomicrmw has
+completed before
+invalidating the
+caches.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="4">
+<li>buffer_gl0_inv;
+buffer_gl1_inv</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td>fence</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-even"><td>fence</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If OpenCL and
+address space is
+not generic, omit.</li>
+<li>However,
+since LLVM
+currently has no
+address space on
+the fence need to
+conservatively
+always generate
+(see comment for
+previous fence).</li>
+<li>Must happen after
+any preceding
+local/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures that all
+memory operations
+to local have
+completed before
+performing any
+following global
+memory operations.</li>
+<li>Ensures that the
+preceding
+local/generic load
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+acquire-fence-paired-atomic
+) has completed
+before following
+global memory
+operations. This
+satisfies the
+requirements of
+acquire.</li>
+<li>Ensures that all
+previous memory
+operations have
+completed before a
+following
+local/generic store
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+release-fence-paired-atomic
+). This satisfies the
+requirements of
+release.</li>
+</ul>
+</div></blockquote>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0) & vscnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit vmcnt and
+vscnt.</li>
+<li>If OpenCL and
+address space is
+not generic, omit
+lgkmcnt(0).</li>
+<li>If OpenCL and
+address space is
+local, omit
+vmcnt(0) and vscnt(0).</li>
+<li>However,
+since LLVM
+currently has no
+address space on
+the fence need to
+conservatively
+always generate
+(see comment for
+previous fence).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0), s_waitcnt
+vscnt(0) and s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/load
+atomic/
+atomicrmw-with-return-value.</li>
+<li>s_waitcnt vscnt(0)
+must happen after
+any preceding
+global/generic
+store/store atomic/
+atomicrmw-no-return-value.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store atomic/
+atomicrmw.</li>
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures that all
+memory operations
+have
+completed before
+performing any
+following global
+memory operations.</li>
+<li>Ensures that the
+preceding
+local/generic load
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+acquire-fence-paired-atomic
+) has completed
+before following
+global memory
+operations. This
+satisfies the
+requirements of
+acquire.</li>
+<li>Ensures that all
+previous memory
+operations have
+completed before a
+following
+local/generic store
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+release-fence-paired-atomic
+). This satisfies the
+requirements of
+release.</li>
+<li>Must happen before
+the following
+buffer_gl0_inv.</li>
+<li>Ensures that the
+acquire-fence-paired
+atomic has completed
+before invalidating
+the
+cache. Therefore
+any following
+locations read must
+be no older than
+the value read by
+the
+acquire-fence-paired-atomic.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="3">
+<li>buffer_gl0_inv</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit.</li>
+<li>Ensures that
+following
+loads will not see
+stale data.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-odd"><td>fence</td>
+<td>acq_rel</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL and
+address space is
+not generic, omit
+lgkmcnt(0).</li>
+<li>However, since LLVM
+currently has no
+address space on
+the fence need to
+conservatively
+always generate
+(see comment for
+previous fence).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and
+s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+buffer_wbinvl1_vol.</li>
+<li>Ensures that the
+preceding
+global/local/generic
+load
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+acquire-fence-paired-atomic
+) has completed
+before invalidating
+the cache. This
+satisfies the
+requirements of
+acquire.</li>
+<li>Ensures that all
+previous memory
+operations have
+completed before a
+following
+global/local/generic
+store
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+release-fence-paired-atomic
+). This satisfies the
+requirements of
+release.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="2">
+<li>buffer_wbinvl1_vol</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data. This
+satisfies the
+requirements of
+acquire.</li>
+</ul>
+</div></blockquote>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0) & vscnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If OpenCL and
+address space is
+not generic, omit
+lgkmcnt(0).</li>
+<li>If OpenCL and
+address space is
+local, omit
+vmcnt(0) and vscnt(0).</li>
+<li>However, since LLVM
+currently has no
+address space on
+the fence need to
+conservatively
+always generate
+(see comment for
+previous fence).</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0), s_waitcnt
+vscnt(0) and s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>s_waitcnt vmcnt(0)
+must happen after
+any preceding
+global/generic
+load/load
+atomic/
+atomicrmw-with-return-value.</li>
+<li>s_waitcnt vscnt(0)
+must happen after
+any preceding
+global/generic
+store/store atomic/
+atomicrmw-no-return-value.</li>
+<li>s_waitcnt lgkmcnt(0)
+must happen after
+any preceding
+local/generic
+load/store/load
+atomic/store
+atomic/atomicrmw.</li>
+<li>Must happen before
+the following
+buffer_gl*_inv.</li>
+<li>Ensures that the
+preceding
+global/local/generic
+load
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+acquire-fence-paired-atomic
+) has completed
+before invalidating
+the caches. This
+satisfies the
+requirements of
+acquire.</li>
+<li>Ensures that all
+previous memory
+operations have
+completed before a
+following
+global/local/generic
+store
+atomic/atomicrmw
+with an equal or
+wider sync scope
+and memory ordering
+stronger than
+unordered (this is
+termed the
+release-fence-paired-atomic
+). This satisfies the
+requirements of
+release.</li>
+</ul>
+</div></blockquote>
+<ol class="arabic simple" start="2">
+<li>buffer_gl0_inv;
+buffer_gl1_inv</li>
+</ol>
+<blockquote class="last">
+<div><ul class="simple">
+<li>Must happen before
+any following
+global/generic
+load/load
+atomic/store/store
+atomic/atomicrmw.</li>
+<li>Ensures that
+following loads
+will not see stale
+global data. This
+satisfies the
+requirements of
+acquire.</li>
+</ul>
+</div></blockquote>
+</td>
+</tr>
+<tr class="row-even"><td colspan="6"><strong>Sequential Consistent Atomic</strong></td>
+</tr>
+<tr class="row-odd"><td>load atomic</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>local</li>
+<li>generic</li>
+</ul>
+</td>
+<td><em>Same as corresponding
+load atomic acquire,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+<td><em>Same as corresponding
+load atomic acquire,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+</tr>
+<tr class="row-even"><td>load atomic</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>Must
+happen after
+preceding
+global/generic load
+atomic/store
+atomic/atomicrmw
+with memory
+ordering of seq_cst
+and with equal or
+wider sync scope.
+(Note that seq_cst
+fences have their
+own s_waitcnt
+lgkmcnt(0) and so do
+not need to be
+considered.)</li>
+<li>Ensures any
+preceding
+sequential
+consistent local
+memory instructions
+have completed
+before executing
+this sequentially
+consistent
+instruction. This
+prevents reordering
+a seq_cst store
+followed by a
+seq_cst load. (Note
+that seq_cst is
+stronger than
+acquire/release as
+the reordering of
+load acquire
+followed by a store
+release is
+prevented by the
+waitcnt of
+the release, but
+there is nothing
+preventing a store
+release followed by
+load acquire from
+competing out of
+order.)</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li><em>Following
+instructions same as
+corresponding load
+atomic acquire,
+except must generated
+all instructions even
+for OpenCL.</em></li>
+</ol>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0) & vscnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit vmcnt and
+vscnt.</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0), s_waitcnt
+vscnt(0) and s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>waitcnt lgkmcnt(0) must
+happen after
+preceding
+local load
+atomic/store
+atomic/atomicrmw
+with memory
+ordering of seq_cst
+and with equal or
+wider sync scope.
+(Note that seq_cst
+fences have their
+own s_waitcnt
+lgkmcnt(0) and so do
+not need to be
+considered.)</li>
+<li>waitcnt vmcnt(0)
+Must happen after
+preceding
+global/generic load
+atomic/
+atomicrmw-with-return-value
+with memory
+ordering of seq_cst
+and with equal or
+wider sync scope.
+(Note that seq_cst
+fences have their
+own s_waitcnt
+vmcnt(0) and so do
+not need to be
+considered.)</li>
+<li>waitcnt vscnt(0)
+Must happen after
+preceding
+global/generic store
+atomic/
+atomicrmw-no-return-value
+with memory
+ordering of seq_cst
+and with equal or
+wider sync scope.
+(Note that seq_cst
+fences have their
+own s_waitcnt
+vscnt(0) and so do
+not need to be
+considered.)</li>
+<li>Ensures any
+preceding
+sequential
+consistent global/local
+memory instructions
+have completed
+before executing
+this sequentially
+consistent
+instruction. This
+prevents reordering
+a seq_cst store
+followed by a
+seq_cst load. (Note
+that seq_cst is
+stronger than
+acquire/release as
+the reordering of
+load acquire
+followed by a store
+release is
+prevented by the
+waitcnt of
+the release, but
+there is nothing
+preventing a store
+release followed by
+load acquire from
+competing out of
+order.)</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li><em>Following
+instructions same as
+corresponding load
+atomic acquire,
+except must generated
+all instructions even
+for OpenCL.</em></li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>load atomic</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>local</li>
+</ul>
+</td>
+<td><em>Same as corresponding
+load atomic acquire,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt vmcnt(0) & vscnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>If CU wavefront execution mode, omit.</li>
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0) and s_waitcnt
+vscnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>waitcnt vmcnt(0)
+Must happen after
+preceding
+global/generic load
+atomic/
+atomicrmw-with-return-value
+with memory
+ordering of seq_cst
+and with equal or
+wider sync scope.
+(Note that seq_cst
+fences have their
+own s_waitcnt
+vmcnt(0) and so do
+not need to be
+considered.)</li>
+<li>waitcnt vscnt(0)
+Must happen after
+preceding
+global/generic store
+atomic/
+atomicrmw-no-return-value
+with memory
+ordering of seq_cst
+and with equal or
+wider sync scope.
+(Note that seq_cst
+fences have their
+own s_waitcnt
+vscnt(0) and so do
+not need to be
+considered.)</li>
+<li>Ensures any
+preceding
+sequential
+consistent global
+memory instructions
+have completed
+before executing
+this sequentially
+consistent
+instruction. This
+prevents reordering
+a seq_cst store
+followed by a
+seq_cst load. (Note
+that seq_cst is
+stronger than
+acquire/release as
+the reordering of
+load acquire
+followed by a store
+release is
+prevented by the
+waitcnt of
+the release, but
+there is nothing
+preventing a store
+release followed by
+load acquire from
+competing out of
+order.)</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li><em>Following
+instructions same as
+corresponding load
+atomic acquire,
+except must generated
+all instructions even
+for OpenCL.</em></li>
+</ol>
+</td>
+</tr>
+<tr class="row-even"><td>load atomic</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0)
+and s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>waitcnt lgkmcnt(0)
+must happen after
+preceding
+global/generic load
+atomic/store
+atomic/atomicrmw
+with memory
+ordering of seq_cst
+and with equal or
+wider sync scope.
+(Note that seq_cst
+fences have their
+own s_waitcnt
+lgkmcnt(0) and so do
+not need to be
+considered.)</li>
+<li>waitcnt vmcnt(0)
+must happen after
+preceding
+global/generic load
+atomic/store
+atomic/atomicrmw
+with memory
+ordering of seq_cst
+and with equal or
+wider sync scope.
+(Note that seq_cst
+fences have their
+own s_waitcnt
+vmcnt(0) and so do
+not need to be
+considered.)</li>
+<li>Ensures any
+preceding
+sequential
+consistent global
+memory instructions
+have completed
+before executing
+this sequentially
+consistent
+instruction. This
+prevents reordering
+a seq_cst store
+followed by a
+seq_cst load. (Note
+that seq_cst is
+stronger than
+acquire/release as
+the reordering of
+load acquire
+followed by a store
+release is
+prevented by the
+waitcnt of
+the release, but
+there is nothing
+preventing a store
+release followed by
+load acquire from
+competing out of
+order.)</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li><em>Following
+instructions same as
+corresponding load
+atomic acquire,
+except must generated
+all instructions even
+for OpenCL.</em></li>
+</ol>
+</td>
+<td><ol class="first arabic simple">
+<li>s_waitcnt lgkmcnt(0) &
+vmcnt(0) & vscnt(0)</li>
+</ol>
+<blockquote>
+<div><ul class="simple">
+<li>Could be split into
+separate s_waitcnt
+vmcnt(0), s_waitcnt
+vscnt(0) and s_waitcnt
+lgkmcnt(0) to allow
+them to be
+independently moved
+according to the
+following rules.</li>
+<li>waitcnt lgkmcnt(0)
+must happen after
+preceding
+local load
+atomic/store
+atomic/atomicrmw
+with memory
+ordering of seq_cst
+and with equal or
+wider sync scope.
+(Note that seq_cst
+fences have their
+own s_waitcnt
+lgkmcnt(0) and so do
+not need to be
+considered.)</li>
+<li>waitcnt vmcnt(0)
+must happen after
+preceding
+global/generic load
+atomic/
+atomicrmw-with-return-value
+with memory
+ordering of seq_cst
+and with equal or
+wider sync scope.
+(Note that seq_cst
+fences have their
+own s_waitcnt
+vmcnt(0) and so do
+not need to be
+considered.)</li>
+<li>waitcnt vscnt(0)
+Must happen after
+preceding
+global/generic store
+atomic/
+atomicrmw-no-return-value
+with memory
+ordering of seq_cst
+and with equal or
+wider sync scope.
+(Note that seq_cst
+fences have their
+own s_waitcnt
+vscnt(0) and so do
+not need to be
+considered.)</li>
+<li>Ensures any
+preceding
+sequential
+consistent global
+memory instructions
+have completed
+before executing
+this sequentially
+consistent
+instruction. This
+prevents reordering
+a seq_cst store
+followed by a
+seq_cst load. (Note
+that seq_cst is
+stronger than
+acquire/release as
+the reordering of
+load acquire
+followed by a store
+release is
+prevented by the
+waitcnt of
+the release, but
+there is nothing
+preventing a store
+release followed by
+load acquire from
+competing out of
+order.)</li>
+</ul>
+</div></blockquote>
+<ol class="last arabic simple" start="2">
+<li><em>Following
+instructions same as
+corresponding load
+atomic acquire,
+except must generated
+all instructions even
+for OpenCL.</em></li>
+</ol>
+</td>
+</tr>
+<tr class="row-odd"><td>store atomic</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>local</li>
+<li>generic</li>
+</ul>
+</td>
+<td><em>Same as corresponding
+store atomic release,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+<td><em>Same as corresponding
+store atomic release,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+</tr>
+<tr class="row-even"><td>store atomic</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><em>Same as corresponding
+store atomic release,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+<td><em>Same as corresponding
+store atomic release,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+</tr>
+<tr class="row-odd"><td>atomicrmw</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>local</li>
+<li>generic</li>
+</ul>
+</td>
+<td><em>Same as corresponding
+atomicrmw acq_rel,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+<td><em>Same as corresponding
+atomicrmw acq_rel,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+</tr>
+<tr class="row-even"><td>atomicrmw</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><ul class="first last simple">
+<li>global</li>
+<li>generic</li>
+</ul>
+</td>
+<td><em>Same as corresponding
+atomicrmw acq_rel,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+<td><em>Same as corresponding
+atomicrmw acq_rel,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+</tr>
+<tr class="row-odd"><td>fence</td>
+<td>seq_cst</td>
+<td><ul class="first last simple">
+<li>singlethread</li>
+<li>wavefront</li>
+<li>workgroup</li>
+<li>agent</li>
+<li>system</li>
+</ul>
+</td>
+<td><em>none</em></td>
+<td><em>Same as corresponding
+fence acq_rel,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+<td><em>Same as corresponding
+fence acq_rel,
+except must generated
+all instructions even
+for OpenCL.</em></td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+<p>The memory order also adds the single thread optimization constrains defined in
+table
+<a class="reference internal" href="#amdgpu-amdhsa-memory-model-single-thread-optimization-constraints-gfx6-gfx10-table"><span class="std std-ref">AMDHSA Memory Model Single Thread Optimization Constraints GFX6-GFX10</span></a>.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-amdhsa-memory-model-single-thread-optimization-constraints-gfx6-gfx10-table">
+<caption><span class="caption-text">AMDHSA Memory Model Single Thread Optimization Constraints GFX6-GFX10</span><a class="headerlink" href="#amdgpu-amdhsa-memory-model-single-thread-optimization-constraints-gfx6-gfx10-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="16%" />
+<col width="84%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">LLVM Memory</th>
+<th class="head">Optimization Constraints</th>
+</tr>
+<tr class="row-even"><th class="head">Ordering</th>
+<th class="head"> </th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-odd"><td>unordered</td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-even"><td>monotonic</td>
+<td><em>none</em></td>
+</tr>
+<tr class="row-odd"><td>acquire</td>
+<td><ul class="first last simple">
+<li>If a load atomic/atomicrmw then no following load/load
+atomic/store/ store atomic/atomicrmw/fence instruction can
+be moved before the acquire.</li>
+<li>If a fence then same as load atomic, plus no preceding
+associated fence-paired-atomic can be moved after the fence.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>release</td>
+<td><ul class="first last simple">
+<li>If a store atomic/atomicrmw then no preceding load/load
+atomic/store/ store atomic/atomicrmw/fence instruction can
+be moved after the release.</li>
+<li>If a fence then same as store atomic, plus no following
+associated fence-paired-atomic can be moved before the
+fence.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-odd"><td>acq_rel</td>
+<td>Same constraints as both acquire and release.</td>
+</tr>
+<tr class="row-even"><td>seq_cst</td>
+<td><ul class="first last simple">
+<li>If a load atomic then same constraints as acquire, plus no
+preceding sequentially consistent load atomic/store
+atomic/atomicrmw/fence instruction can be moved after the
+seq_cst.</li>
+<li>If a store atomic then the same constraints as release, plus
+no following sequentially consistent load atomic/store
+atomic/atomicrmw/fence instruction can be moved before the
+seq_cst.</li>
+<li>If an atomicrmw/fence then same constraints as acq_rel.</li>
+</ul>
+</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="trap-handler-abi">
+<h4><a class="toc-backref" href="#id87">Trap Handler ABI</a><a class="headerlink" href="#trap-handler-abi" title="Permalink to this headline">¶</a></h4>
+<p>For code objects generated by AMDGPU backend for HSA <a class="reference internal" href="#hsa" id="id37">[HSA]</a> compatible runtimes
+(such as ROCm <a class="reference internal" href="#amd-rocm" id="id38">[AMD-ROCm]</a>), the runtime installs a trap handler that supports
+the <code class="docutils literal notranslate"><span class="pre">s_trap</span></code> instruction with the following usage:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-trap-handler-for-amdhsa-os-table">
+<caption><span class="caption-text">AMDGPU Trap Handler for AMDHSA OS</span><a class="headerlink" href="#amdgpu-trap-handler-for-amdhsa-os-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="26%" />
+<col width="21%" />
+<col width="21%" />
+<col width="32%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Usage</th>
+<th class="head">Code Sequence</th>
+<th class="head">Trap Handler
+Inputs</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>reserved</td>
+<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x00</span></code></td>
+<td> </td>
+<td>Reserved by hardware.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">debugtrap(arg)</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x01</span></code></td>
+<td><dl class="first last docutils">
+<dt><code class="docutils literal notranslate"><span class="pre">SGPR0-1</span></code>:</dt>
+<dd><code class="docutils literal notranslate"><span class="pre">queue_ptr</span></code></dd>
+<dt><code class="docutils literal notranslate"><span class="pre">VGPR0</span></code>:</dt>
+<dd><code class="docutils literal notranslate"><span class="pre">arg</span></code></dd>
+</dl>
+</td>
+<td>Reserved for HSA
+<code class="docutils literal notranslate"><span class="pre">debugtrap</span></code>
+intrinsic (not
+implemented).</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">llvm.trap</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x02</span></code></td>
+<td><dl class="first last docutils">
+<dt><code class="docutils literal notranslate"><span class="pre">SGPR0-1</span></code>:</dt>
+<dd><code class="docutils literal notranslate"><span class="pre">queue_ptr</span></code></dd>
+</dl>
+</td>
+<td>Causes dispatch to be
+terminated and its
+associated queue put
+into the error state.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">llvm.debugtrap</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x03</span></code></td>
+<td> </td>
+<td><ul class="first last simple">
+<li>If debugger not
+installed then
+behaves as a
+no-operation. The
+trap handler is
+entered and
+immediately returns
+to continue
+execution of the
+wavefront.</li>
+<li>If the debugger is
+installed, causes
+the debug trap to be
+reported by the
+debugger and the
+wavefront is put in
+the halt state until
+resumed by the
+debugger.</li>
+</ul>
+</td>
+</tr>
+<tr class="row-even"><td>reserved</td>
+<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x04</span></code></td>
+<td> </td>
+<td>Reserved.</td>
+</tr>
+<tr class="row-odd"><td>reserved</td>
+<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x05</span></code></td>
+<td> </td>
+<td>Reserved.</td>
+</tr>
+<tr class="row-even"><td>reserved</td>
+<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x06</span></code></td>
+<td> </td>
+<td>Reserved.</td>
+</tr>
+<tr class="row-odd"><td>debugger breakpoint</td>
+<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x07</span></code></td>
+<td> </td>
+<td>Reserved for debugger
+breakpoints.</td>
+</tr>
+<tr class="row-even"><td>reserved</td>
+<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0x08</span></code></td>
+<td> </td>
+<td>Reserved.</td>
+</tr>
+<tr class="row-odd"><td>reserved</td>
+<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0xfe</span></code></td>
+<td> </td>
+<td>Reserved.</td>
+</tr>
+<tr class="row-even"><td>reserved</td>
+<td><code class="docutils literal notranslate"><span class="pre">s_trap</span> <span class="pre">0xff</span></code></td>
+<td> </td>
+<td>Reserved.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="amdpal">
+<h3><a class="toc-backref" href="#id88">AMDPAL</a><a class="headerlink" href="#amdpal" title="Permalink to this headline">¶</a></h3>
+<p>This section provides code conventions used when the target triple OS is
+<code class="docutils literal notranslate"><span class="pre">amdpal</span></code> (see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>) for passing runtime parameters
+from the application/runtime to each invocation of a hardware shader. These
+parameters include both generic, application-controlled parameters called
+<em>user data</em> as well as system-generated parameters that are a product of the
+draw or dispatch execution.</p>
+<div class="section" id="user-data">
+<h4><a class="toc-backref" href="#id89">User Data</a><a class="headerlink" href="#user-data" title="Permalink to this headline">¶</a></h4>
+<p>Each hardware stage has a set of 32-bit <em>user data registers</em> which can be
+written from a command buffer and then loaded into SGPRs when waves are launched
+via a subsequent dispatch or draw operation. This is the way most arguments are
+passed from the application/runtime to a hardware shader.</p>
+</div>
+<div class="section" id="compute-user-data">
+<h4><a class="toc-backref" href="#id90">Compute User Data</a><a class="headerlink" href="#compute-user-data" title="Permalink to this headline">¶</a></h4>
+<p>Compute shader user data mappings are simpler than graphics shaders, and have a
+fixed mapping.</p>
+<p>Note that there are always 10 available <em>user data entries</em> in registers -
+entries beyond that limit must be fetched from memory (via the spill table
+pointer) by the shader.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="pal-compute-user-data-registers">
+<caption><span class="caption-text">PAL Compute Shader User Data Registers</span><a class="headerlink" href="#pal-compute-user-data-registers" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="20%" />
+<col width="80%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">User Register</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>0</td>
+<td>Global Internal Table (32-bit pointer)</td>
+</tr>
+<tr class="row-odd"><td>1</td>
+<td>Per-Shader Internal Table (32-bit pointer)</td>
+</tr>
+<tr class="row-even"><td>2 - 11</td>
+<td>Application-Controlled User Data (10 32-bit values)</td>
+</tr>
+<tr class="row-odd"><td>12</td>
+<td>Spill Table (32-bit pointer)</td>
+</tr>
+<tr class="row-even"><td>13 - 14</td>
+<td>Thread Group Count (64-bit pointer)</td>
+</tr>
+<tr class="row-odd"><td>15</td>
+<td>GDS Range</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="graphics-user-data">
+<h4><a class="toc-backref" href="#id91">Graphics User Data</a><a class="headerlink" href="#graphics-user-data" title="Permalink to this headline">¶</a></h4>
+<p>Graphics pipelines support a much more flexible user data mapping:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="pal-graphics-user-data-registers">
+<caption><span class="caption-text">PAL Graphics Shader User Data Registers</span><a class="headerlink" href="#pal-graphics-user-data-registers" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="23%" />
+<col width="77%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">User Register</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>0</td>
+<td>Global Internal Table (32-bit pointer)</td>
+</tr>
+<tr class="row-odd"><td><ul class="first last simple">
+<li></li>
+</ul>
+</td>
+<td>Per-Shader Internal Table (32-bit pointer)</td>
+</tr>
+<tr class="row-even"><td><ul class="first last simple">
+<li>1-15</li>
+</ul>
+</td>
+<td>Application Controlled User Data
+(1-15 Contiguous 32-bit Values in Registers)</td>
+</tr>
+<tr class="row-odd"><td><ul class="first last simple">
+<li></li>
+</ul>
+</td>
+<td>Spill Table (32-bit pointer)</td>
+</tr>
+<tr class="row-even"><td><ul class="first last simple">
+<li></li>
+</ul>
+</td>
+<td>Draw Index (First Stage Only)</td>
+</tr>
+<tr class="row-odd"><td><ul class="first last simple">
+<li></li>
+</ul>
+</td>
+<td>Vertex Offset (First Stage Only)</td>
+</tr>
+<tr class="row-even"><td><ul class="first last simple">
+<li></li>
+</ul>
+</td>
+<td>Instance Offset (First Stage Only)</td>
+</tr>
+</tbody>
+</table>
+<p>The placement of the global internal table remains fixed in the first <em>user
+data SGPR register</em>. Otherwise all parameters are optional, and can be mapped
+to any desired <em>user data SGPR register</em>, with the following regstrictions:</p>
+<ul class="simple">
+<li>Draw Index, Vertex Offset, and Instance Offset can only be used by the first
+activehardware stage in a graphics pipeline (i.e. where the API vertex
+shader runs).</li>
+<li>Application-controlled user data must be mapped into a contiguous range of
+user data registers.</li>
+<li>The application-controlled user data range supports compaction remapping, so
+only <em>entries</em> that are actually consumed by the shader must be assigned to
+corresponding <em>registers</em>. Note that in order to support an efficient runtime
+implementation, the remapping must pack <em>registers</em> in the same order as
+<em>entries</em>, with unused <em>entries</em> removed.</li>
+</ul>
+</div></blockquote>
+</div>
+<div class="section" id="global-internal-table">
+<span id="pal-global-internal-table"></span><h4><a class="toc-backref" href="#id92">Global Internal Table</a><a class="headerlink" href="#global-internal-table" title="Permalink to this headline">¶</a></h4>
+<p>The global internal table is a table of <em>shader resource descriptors</em> (SRDs) that
+define how certain engine-wide, runtime-managed resources should be accessed
+from a shader. The majority of these resources have HW-defined formats, and it
+is up to the compiler to write/read data as required by the target hardware.</p>
+<p>The following table illustrates the required format:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="pal-git-table">
+<caption><span class="caption-text">PAL Global Internal Table</span><a class="headerlink" href="#pal-git-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="25%" />
+<col width="75%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Offset</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>0-3</td>
+<td>Graphics Scratch SRD</td>
+</tr>
+<tr class="row-odd"><td>4-7</td>
+<td>Compute Scratch SRD</td>
+</tr>
+<tr class="row-even"><td>8-11</td>
+<td>ES/GS Ring Output SRD</td>
+</tr>
+<tr class="row-odd"><td>12-15</td>
+<td>ES/GS Ring Input SRD</td>
+</tr>
+<tr class="row-even"><td>16-19</td>
+<td>GS/VS Ring Output #0</td>
+</tr>
+<tr class="row-odd"><td>20-23</td>
+<td>GS/VS Ring Output #1</td>
+</tr>
+<tr class="row-even"><td>24-27</td>
+<td>GS/VS Ring Output #2</td>
+</tr>
+<tr class="row-odd"><td>28-31</td>
+<td>GS/VS Ring Output #3</td>
+</tr>
+<tr class="row-even"><td>32-35</td>
+<td>GS/VS Ring Input SRD</td>
+</tr>
+<tr class="row-odd"><td>36-39</td>
+<td>Tessellation Factor Buffer SRD</td>
+</tr>
+<tr class="row-even"><td>40-43</td>
+<td>Off-Chip LDS Buffer SRD</td>
+</tr>
+<tr class="row-odd"><td>44-47</td>
+<td>Off-Chip Param Cache Buffer SRD</td>
+</tr>
+<tr class="row-even"><td>48-51</td>
+<td>Sample Position Buffer SRD</td>
+</tr>
+<tr class="row-odd"><td>52</td>
+<td>vaRange::ShadowDescriptorTable High Bits</td>
+</tr>
+</tbody>
+</table>
+<p>The pointer to the global internal table passed to the shader as user data
+is a 32-bit pointer. The top 32 bits should be assumed to be the same as
+the top 32 bits of the pipeline, so the shader may use the program
+counterâs top 32 bits.</p>
+</div></blockquote>
+</div>
+</div>
+<div class="section" id="unspecified-os">
+<h3><a class="toc-backref" href="#id93">Unspecified OS</a><a class="headerlink" href="#unspecified-os" title="Permalink to this headline">¶</a></h3>
+<p>This section provides code conventions used when the target triple OS is
+empty (see <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a>).</p>
+<div class="section" id="id39">
+<h4><a class="toc-backref" href="#id94">Trap Handler ABI</a><a class="headerlink" href="#id39" title="Permalink to this headline">¶</a></h4>
+<p>For code objects generated by AMDGPU backend for non-amdhsa OS, the runtime does
+not install a trap handler. The <code class="docutils literal notranslate"><span class="pre">llvm.trap</span></code> and <code class="docutils literal notranslate"><span class="pre">llvm.debugtrap</span></code>
+instructions are handled as follows:</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdgpu-trap-handler-for-non-amdhsa-os-table">
+<caption><span class="caption-text">AMDGPU Trap Handler for Non-AMDHSA OS</span><a class="headerlink" href="#amdgpu-trap-handler-for-non-amdhsa-os-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="21%" />
+<col width="21%" />
+<col width="59%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Usage</th>
+<th class="head">Code Sequence</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>llvm.trap</td>
+<td>s_endpgm</td>
+<td>Causes wavefront to be terminated.</td>
+</tr>
+<tr class="row-odd"><td>llvm.debugtrap</td>
+<td><em>none</em></td>
+<td>Compiler warning given that there is no
+trap handler installed.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+</div>
+</div>
+<div class="section" id="source-languages">
+<h2><a class="toc-backref" href="#id95">Source Languages</a><a class="headerlink" href="#source-languages" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="opencl">
+<span id="amdgpu-opencl"></span><h3><a class="toc-backref" href="#id96">OpenCL</a><a class="headerlink" href="#opencl" title="Permalink to this headline">¶</a></h3>
+<p>When the language is OpenCL the following differences occur:</p>
+<ol class="arabic simple">
+<li>The OpenCL memory model is used (see <a class="reference internal" href="#amdgpu-amdhsa-memory-model"><span class="std std-ref">Memory Model</span></a>).</li>
+<li>The AMDGPU backend appends additional arguments to the kernelâs explicit
+arguments for the AMDHSA OS (see
+<a class="reference internal" href="#opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table"><span class="std std-ref">OpenCL kernel implicit arguments appended for AMDHSA OS</span></a>).</li>
+<li>Additional metadata is generated
+(see <a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata"><span class="std std-ref">Code Object Metadata</span></a>).</li>
+</ol>
+<blockquote>
+<div><table border="1" class="docutils" id="opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table">
+<caption><span class="caption-text">OpenCL kernel implicit arguments appended for AMDHSA OS</span><a class="headerlink" href="#opencl-kernel-implicit-arguments-appended-for-amdhsa-os-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="13%" />
+<col width="6%" />
+<col width="14%" />
+<col width="67%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Position</th>
+<th class="head">Byte
+Size</th>
+<th class="head">Byte
+Alignment</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>1</td>
+<td>8</td>
+<td>8</td>
+<td>OpenCL Global Offset X</td>
+</tr>
+<tr class="row-odd"><td>2</td>
+<td>8</td>
+<td>8</td>
+<td>OpenCL Global Offset Y</td>
+</tr>
+<tr class="row-even"><td>3</td>
+<td>8</td>
+<td>8</td>
+<td>OpenCL Global Offset Z</td>
+</tr>
+<tr class="row-odd"><td>4</td>
+<td>8</td>
+<td>8</td>
+<td>OpenCL address of printf buffer</td>
+</tr>
+<tr class="row-even"><td>5</td>
+<td>8</td>
+<td>8</td>
+<td>OpenCL address of virtual queue used by
+enqueue_kernel.</td>
+</tr>
+<tr class="row-odd"><td>6</td>
+<td>8</td>
+<td>8</td>
+<td>OpenCL address of AqlWrap struct used by
+enqueue_kernel.</td>
+</tr>
+<tr class="row-even"><td>7</td>
+<td>8</td>
+<td>8</td>
+<td>Pointer argument used for Multi-gird
+synchronization.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="hcc">
+<span id="amdgpu-hcc"></span><h3><a class="toc-backref" href="#id97">HCC</a><a class="headerlink" href="#hcc" title="Permalink to this headline">¶</a></h3>
+<p>When the language is HCC the following differences occur:</p>
+<ol class="arabic simple">
+<li>The HSA memory model is used (see <a class="reference internal" href="#amdgpu-amdhsa-memory-model"><span class="std std-ref">Memory Model</span></a>).</li>
+</ol>
+</div>
+<div class="section" id="assembler">
+<span id="amdgpu-assembler"></span><h3><a class="toc-backref" href="#id98">Assembler</a><a class="headerlink" href="#assembler" title="Permalink to this headline">¶</a></h3>
+<p>AMDGPU backend has LLVM-MC based assembler which is currently in development.
+It supports AMDGCN GFX6-GFX10.</p>
+<p>This section describes general syntax for instructions and operands.</p>
+<div class="section" id="instructions">
+<h4><a class="toc-backref" href="#id99">Instructions</a><a class="headerlink" href="#instructions" title="Permalink to this headline">¶</a></h4>
+<div class="toctree-wrapper compound">
+</div>
+<p>An instruction has the following <a class="reference internal" href="AMDGPUInstructionSyntax.html"><span class="doc">syntax</span></a>:</p>
+<blockquote>
+<div><code class="docutils literal notranslate"><span class="pre"><</span></code><em>opcode</em><code class="docutils literal notranslate"><span class="pre">></span> <span class="pre"><</span></code><em>operand0</em><code class="docutils literal notranslate"><span class="pre">>,</span> <span class="pre"><</span></code><em>operand1</em><code class="docutils literal notranslate"><span class="pre">>,...</span> <span class="pre"><</span></code><em>modifier0</em><code class="docutils literal notranslate"><span class="pre">></span> <span class="pre"><</span></code><em>modifier1</em><code class="docutils literal notranslate"><span class="pre">>...</span></code></div></blockquote>
+<p><a class="reference internal" href="AMDGPUOperandSyntax.html"><span class="doc">Operands</span></a> are normally comma-separated while
+<a class="reference internal" href="AMDGPUModifierSyntax.html"><span class="doc">modifiers</span></a> are space-separated.</p>
+<p>The order of <em>operands</em> and <em>modifiers</em> is fixed.
+Most <em>modifiers</em> are optional and may be omitted.</p>
+<p>See detailed instruction syntax description for <a class="reference internal" href="AMDGPU/AMDGPUAsmGFX7.html"><span class="doc">GFX7</span></a>,
+<a class="reference internal" href="AMDGPU/AMDGPUAsmGFX8.html"><span class="doc">GFX8</span></a>, <a class="reference internal" href="AMDGPU/AMDGPUAsmGFX9.html"><span class="doc">GFX9</span></a>
+and <a class="reference internal" href="AMDGPU/AMDGPUAsmGFX10.html"><span class="doc">GFX10</span></a>.</p>
+<p>Note that features under development are not included in this description.</p>
+<p>For more information about instructions, their semantics and supported combinations of
+operands, refer to one of instruction set architecture manuals
+<a class="reference internal" href="#amd-gcn-gfx6" id="id40">[AMD-GCN-GFX6]</a>, <a class="reference internal" href="#amd-gcn-gfx7" id="id41">[AMD-GCN-GFX7]</a>, <a class="reference internal" href="#amd-gcn-gfx8" id="id42">[AMD-GCN-GFX8]</a>, <a class="reference internal" href="#amd-gcn-gfx9" id="id43">[AMD-GCN-GFX9]</a> and
+<a class="reference internal" href="#amd-gcn-gfx10" id="id44">[AMD-GCN-GFX10]</a>.</p>
+</div>
+<div class="section" id="operands">
+<h4><a class="toc-backref" href="#id100">Operands</a><a class="headerlink" href="#operands" title="Permalink to this headline">¶</a></h4>
+<p>Detailed description of operands may be found <a class="reference internal" href="AMDGPUOperandSyntax.html"><span class="doc">here</span></a>.</p>
+</div>
+<div class="section" id="modifiers">
+<h4><a class="toc-backref" href="#id101">Modifiers</a><a class="headerlink" href="#modifiers" title="Permalink to this headline">¶</a></h4>
+<p>Detailed description of modifiers may be found <a class="reference internal" href="AMDGPUModifierSyntax.html"><span class="doc">here</span></a>.</p>
+</div>
+<div class="section" id="instruction-examples">
+<h4><a class="toc-backref" href="#id102">Instruction Examples</a><a class="headerlink" href="#instruction-examples" title="Permalink to this headline">¶</a></h4>
+<div class="section" id="ds">
+<h5><a class="toc-backref" href="#id103">DS</a><a class="headerlink" href="#ds" title="Permalink to this headline">¶</a></h5>
+<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">ds_add_u32</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v4</span> <span class="nv">offset</span><span class="p">:</span><span class="mi">16</span>
+<span class="nf">ds_write_src2_b64</span> <span class="nv">v2</span> <span class="nv">offset0</span><span class="p">:</span><span class="mi">4</span> <span class="nv">offset1</span><span class="p">:</span><span class="mi">8</span>
+<span class="nf">ds_cmpst_f32</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v4</span><span class="p">,</span> <span class="nv">v6</span>
+<span class="nf">ds_min_rtn_f64</span> <span class="nv">v</span><span class="p">[</span><span class="mi">8</span><span class="p">:</span><span class="mi">9</span><span class="p">],</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to âLDS/GDS instructionsâ in ISA Manual.</p>
+</div>
+<div class="section" id="flat">
+<h5><a class="toc-backref" href="#id104">FLAT</a><a class="headerlink" href="#flat" title="Permalink to this headline">¶</a></h5>
+<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">flat_load_dword</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v</span><span class="p">[</span><span class="mi">3</span><span class="p">:</span><span class="mi">4</span><span class="p">]</span>
+<span class="nf">flat_store_dwordx3</span> <span class="nv">v</span><span class="p">[</span><span class="mi">3</span><span class="p">:</span><span class="mi">4</span><span class="p">],</span> <span class="nv">v</span><span class="p">[</span><span class="mi">5</span><span class="p">:</span><span class="mi">7</span><span class="p">]</span>
+<span class="nf">flat_atomic_swap</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v</span><span class="p">[</span><span class="mi">3</span><span class="p">:</span><span class="mi">4</span><span class="p">],</span> <span class="nv">v5</span> <span class="nv">glc</span>
+<span class="nf">flat_atomic_cmpswap</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v</span><span class="p">[</span><span class="mi">3</span><span class="p">:</span><span class="mi">4</span><span class="p">],</span> <span class="nv">v</span><span class="p">[</span><span class="mi">5</span><span class="p">:</span><span class="mi">6</span><span class="p">]</span> <span class="nv">glc</span> <span class="nv">slc</span>
+<span class="nf">flat_atomic_fmax_x2</span> <span class="nv">v</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="p">],</span> <span class="nv">v</span><span class="p">[</span><span class="mi">3</span><span class="p">:</span><span class="mi">4</span><span class="p">],</span> <span class="nv">v</span><span class="p">[</span><span class="mi">5</span><span class="p">:</span><span class="mi">6</span><span class="p">]</span> <span class="nv">glc</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to âFLAT instructionsâ in ISA Manual.</p>
+</div>
+<div class="section" id="mubuf">
+<h5><a class="toc-backref" href="#id105">MUBUF</a><a class="headerlink" href="#mubuf" title="Permalink to this headline">¶</a></h5>
+<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">buffer_load_dword</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">off</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">7</span><span class="p">],</span> <span class="nv">s1</span>
+<span class="nf">buffer_store_dwordx4</span> <span class="nv">v</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">4</span><span class="p">],</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">ttmp</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">7</span><span class="p">],</span> <span class="nv">s1</span> <span class="nv">offen</span> <span class="nv">offset</span><span class="p">:</span><span class="mi">4</span> <span class="nv">glc</span> <span class="nv">tfe</span>
+<span class="nf">buffer_store_format_xy</span> <span class="nv">v</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="p">],</span> <span class="nv">off</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">7</span><span class="p">],</span> <span class="nv">s1</span>
+<span class="nf">buffer_wbinvl1</span>
+<span class="nf">buffer_atomic_inc</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">8</span><span class="p">:</span><span class="mi">11</span><span class="p">],</span> <span class="nv">s4</span> <span class="nv">idxen</span> <span class="nv">offset</span><span class="p">:</span><span class="mi">4</span> <span class="nv">slc</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to âMUBUF Instructionsâ in ISA Manual.</p>
+</div>
+<div class="section" id="smrd-smem">
+<h5><a class="toc-backref" href="#id106">SMRD/SMEM</a><a class="headerlink" href="#smrd-smem" title="Permalink to this headline">¶</a></h5>
+<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">s_load_dword</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="mh">0xfc</span>
+<span class="nf">s_load_dwordx8</span> <span class="nv">s</span><span class="p">[</span><span class="mi">8</span><span class="p">:</span><span class="mi">15</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s4</span>
+<span class="nf">s_load_dwordx16</span> <span class="nv">s</span><span class="p">[</span><span class="mi">88</span><span class="p">:</span><span class="mi">103</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s4</span>
+<span class="nf">s_dcache_inv_vol</span>
+<span class="nf">s_memtime</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to âScalar Memory Operationsâ in ISA Manual.</p>
+</div>
+<div class="section" id="sop1">
+<h5><a class="toc-backref" href="#id107">SOP1</a><a class="headerlink" href="#sop1" title="Permalink to this headline">¶</a></h5>
+<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">s_mov_b32</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s2</span>
+<span class="nf">s_mov_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">],</span> <span class="mh">0x80000000</span>
+<span class="nf">s_cmov_b32</span> <span class="nv">s1</span><span class="p">,</span> <span class="mi">200</span>
+<span class="nf">s_wqm_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
+<span class="nf">s_bcnt0_i32_b64</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">]</span>
+<span class="nf">s_swappc_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
+<span class="nf">s_cbranch_join</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">]</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to âSOP1 Instructionsâ in ISA Manual.</p>
+</div>
+<div class="section" id="sop2">
+<h5><a class="toc-backref" href="#id108">SOP2</a><a class="headerlink" href="#sop2" title="Permalink to this headline">¶</a></h5>
+<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">s_add_u32</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s2</span><span class="p">,</span> <span class="nv">s3</span>
+<span class="nf">s_and_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">6</span><span class="p">:</span><span class="mi">7</span><span class="p">]</span>
+<span class="nf">s_cselect_b32</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s2</span><span class="p">,</span> <span class="nv">s3</span>
+<span class="nf">s_andn2_b32</span> <span class="nv">s2</span><span class="p">,</span> <span class="nv">s4</span><span class="p">,</span> <span class="nv">s6</span>
+<span class="nf">s_lshr_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">],</span> <span class="nv">s6</span>
+<span class="nf">s_ashr_i32</span> <span class="nv">s2</span><span class="p">,</span> <span class="nv">s4</span><span class="p">,</span> <span class="nv">s6</span>
+<span class="nf">s_bfm_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s4</span><span class="p">,</span> <span class="nv">s6</span>
+<span class="nf">s_bfe_i64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">],</span> <span class="nv">s6</span>
+<span class="nf">s_cbranch_g_fork</span> <span class="nv">s</span><span class="p">[</span><span class="mi">4</span><span class="p">:</span><span class="mi">5</span><span class="p">],</span> <span class="nv">s</span><span class="p">[</span><span class="mi">6</span><span class="p">:</span><span class="mi">7</span><span class="p">]</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to âSOP2 Instructionsâ in ISA Manual.</p>
+</div>
+<div class="section" id="sopc">
+<h5><a class="toc-backref" href="#id109">SOPC</a><a class="headerlink" href="#sopc" title="Permalink to this headline">¶</a></h5>
+<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">s_cmp_eq_i32</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s2</span>
+<span class="nf">s_bitcmp1_b32</span> <span class="nv">s1</span><span class="p">,</span> <span class="nv">s2</span>
+<span class="nf">s_bitcmp0_b64</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">],</span> <span class="nv">s4</span>
+<span class="nf">s_setvskip</span> <span class="nv">s3</span><span class="p">,</span> <span class="nv">s5</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to âSOPC Instructionsâ in ISA Manual.</p>
+</div>
+<div class="section" id="sopp">
+<h5><a class="toc-backref" href="#id110">SOPP</a><a class="headerlink" href="#sopp" title="Permalink to this headline">¶</a></h5>
+<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">s_barrier</span>
+<span class="nf">s_nop</span> <span class="mi">2</span>
+<span class="nf">s_endpgm</span>
+<span class="nf">s_waitcnt</span> <span class="mi">0</span> <span class="c1">; Wait for all counters to be 0</span>
+<span class="nf">s_waitcnt</span> <span class="nv">vmcnt</span><span class="p">(</span><span class="mi">0</span><span class="p">)</span> <span class="o">&</span> <span class="nv">expcnt</span><span class="p">(</span><span class="mi">0</span><span class="p">)</span> <span class="o">&</span> <span class="nv">lgkmcnt</span><span class="p">(</span><span class="mi">0</span><span class="p">)</span> <span class="c1">; Equivalent to above</span>
+<span class="nf">s_waitcnt</span> <span class="nv">vmcnt</span><span class="p">(</span><span class="mi">1</span><span class="p">)</span> <span class="c1">; Wait for vmcnt counter to be 1.</span>
+<span class="nf">s_sethalt</span> <span class="mi">9</span>
+<span class="nf">s_sleep</span> <span class="mi">10</span>
+<span class="nf">s_sendmsg</span> <span class="mh">0x1</span>
+<span class="nf">s_sendmsg</span> <span class="nv">sendmsg</span><span class="p">(</span><span class="nv">MSG_INTERRUPT</span><span class="p">)</span>
+<span class="nf">s_trap</span> <span class="mi">1</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to âSOPP Instructionsâ in ISA Manual.</p>
+<p>Unless otherwise mentioned, little verification is performed on the operands
+of SOPP Instructions, so it is up to the programmer to be familiar with the
+range or acceptable values.</p>
+</div>
+<div class="section" id="valu">
+<h5><a class="toc-backref" href="#id111">VALU</a><a class="headerlink" href="#valu" title="Permalink to this headline">¶</a></h5>
+<p>For vector ALU instruction opcodes (VOP1, VOP2, VOP3, VOPC, VOP_DPP, VOP_SDWA),
+the assembler will automatically use optimal encoding based on its operands.
+To force specific encoding, one can add a suffix to the opcode of the instruction:</p>
+<ul class="simple">
+<li>_e32 for 32-bit VOP1/VOP2/VOPC</li>
+<li>_e64 for 64-bit VOP3</li>
+<li>_dpp for VOP_DPP</li>
+<li>_sdwa for VOP_SDWA</li>
+</ul>
+<p>VOP1/VOP2/VOP3/VOPC examples:</p>
+<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">v_mov_b32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span>
+<span class="nf">v_mov_b32_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span>
+<span class="nf">v_nop</span>
+<span class="nf">v_cvt_f64_i32_e32</span> <span class="nv">v</span><span class="p">[</span><span class="mi">1</span><span class="p">:</span><span class="mi">2</span><span class="p">],</span> <span class="nv">v2</span>
+<span class="nf">v_floor_f32_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span>
+<span class="nf">v_bfrev_b32_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span>
+<span class="nf">v_add_f32_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v3</span>
+<span class="nf">v_mul_i32_i24_e64</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span><span class="p">,</span> <span class="mi">3</span>
+<span class="nf">v_mul_i32_i24_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="o">-</span><span class="mi">3</span><span class="p">,</span> <span class="nv">v3</span>
+<span class="nf">v_mul_i32_i24_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="o">-</span><span class="mi">100</span><span class="p">,</span> <span class="nv">v3</span>
+<span class="nf">v_addc_u32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">0</span><span class="p">:</span><span class="mi">1</span><span class="p">],</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v3</span><span class="p">,</span> <span class="nv">s</span><span class="p">[</span><span class="mi">2</span><span class="p">:</span><span class="mi">3</span><span class="p">]</span>
+<span class="nf">v_max_f16_e32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v3</span>
+</pre></div>
+</div>
+<p>VOP_DPP examples:</p>
+<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">v_mov_b32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nv">quad_perm</span><span class="p">:[</span><span class="mi">0</span><span class="p">,</span><span class="mi">2</span><span class="p">,</span><span class="mi">1</span><span class="p">,</span><span class="mi">1</span><span class="p">]</span>
+<span class="nf">v_sin_f32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nv">row_shl</span><span class="p">:</span><span class="mi">1</span> <span class="nv">row_mask</span><span class="p">:</span><span class="mh">0xa</span> <span class="nv">bank_mask</span><span class="p">:</span><span class="mh">0x1</span> <span class="nv">bound_ctrl</span><span class="p">:</span><span class="mi">0</span>
+<span class="nf">v_mov_b32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nv">wave_shl</span><span class="p">:</span><span class="mi">1</span>
+<span class="nf">v_mov_b32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nv">row_mirror</span>
+<span class="nf">v_mov_b32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nv">row_bcast</span><span class="p">:</span><span class="mi">31</span>
+<span class="nf">v_mov_b32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nv">quad_perm</span><span class="p">:[</span><span class="mi">1</span><span class="p">,</span><span class="mi">3</span><span class="p">,</span><span class="mi">0</span><span class="p">,</span><span class="mi">1</span><span class="p">]</span> <span class="nv">row_mask</span><span class="p">:</span><span class="mh">0xa</span> <span class="nv">bank_mask</span><span class="p">:</span><span class="mh">0x1</span> <span class="nv">bound_ctrl</span><span class="p">:</span><span class="mi">0</span>
+<span class="nf">v_add_f32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span><span class="p">,</span> <span class="o">|</span><span class="nv">v0</span><span class="o">|</span> <span class="nv">row_shl</span><span class="p">:</span><span class="mi">1</span> <span class="nv">row_mask</span><span class="p">:</span><span class="mh">0xa</span> <span class="nv">bank_mask</span><span class="p">:</span><span class="mh">0x1</span> <span class="nv">bound_ctrl</span><span class="p">:</span><span class="mi">0</span>
+<span class="nf">v_max_f16</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span><span class="p">,</span> <span class="nv">v3</span> <span class="nv">row_shl</span><span class="p">:</span><span class="mi">1</span> <span class="nv">row_mask</span><span class="p">:</span><span class="mh">0xa</span> <span class="nv">bank_mask</span><span class="p">:</span><span class="mh">0x1</span> <span class="nv">bound_ctrl</span><span class="p">:</span><span class="mi">0</span>
+</pre></div>
+</div>
+<p>VOP_SDWA examples:</p>
+<div class="highlight-nasm notranslate"><div class="highlight"><pre><span></span><span class="nf">v_mov_b32</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span> <span class="nb">ds</span><span class="nv">t_sel</span><span class="p">:</span><span class="kt">BYTE</span><span class="nv">_0</span> <span class="nb">ds</span><span class="nv">t_unused</span><span class="p">:</span><span class="nv">UNUSED_PRESERVE</span> <span class="nv">src0_sel</span><span class="p">:</span><span class="kt">DWORD</span>
+<span class="nf">v_min_u32</span> <span class="nv">v200</span><span class="p">,</span> <span class="nv">v200</span><span class="p">,</span> <span class="nv">v1</span> <span class="nb">ds</span><span class="nv">t_sel</span><span class="p">:</span><span class="kt">WORD</span><span class="nv">_1</span> <span class="nb">ds</span><span class="nv">t_unused</span><span class="p">:</span><span class="nv">UNUSED_PAD</span> <span class="nv">src0_sel</span><span class="p">:</span><span class="kt">BYTE</span><span class="nv">_1</span> <span class="nv">src1_sel</span><span class="p">:</span><span class="kt">DWORD</span>
+<span class="nf">v_sin_f32</span> <span class="nv">v0</span><span class="p">,</span> <span class="nv">v0</span> <span class="nb">ds</span><span class="nv">t_unused</span><span class="p">:</span><span class="nv">UNUSED_PAD</span> <span class="nv">src0_sel</span><span class="p">:</span><span class="kt">WORD</span><span class="nv">_1</span>
+<span class="nf">v_fract_f32</span> <span class="nv">v0</span><span class="p">,</span> <span class="o">|</span><span class="nv">v0</span><span class="o">|</span> <span class="nb">ds</span><span class="nv">t_sel</span><span class="p">:</span><span class="kt">DWORD</span> <span class="nb">ds</span><span class="nv">t_unused</span><span class="p">:</span><span class="nv">UNUSED_PAD</span> <span class="nv">src0_sel</span><span class="p">:</span><span class="kt">WORD</span><span class="nv">_1</span>
+<span class="nf">v_cmpx_le_u32</span> <span class="nv">vcc</span><span class="p">,</span> <span class="nv">v1</span><span class="p">,</span> <span class="nv">v2</span> <span class="nv">src0_sel</span><span class="p">:</span><span class="kt">BYTE</span><span class="nv">_2</span> <span class="nv">src1_sel</span><span class="p">:</span><span class="kt">WORD</span><span class="nv">_0</span>
+</pre></div>
+</div>
+<p>For full list of supported instructions, refer to âVector ALU instructionsâ.</p>
+</div>
+</div>
+<div class="section" id="code-object-v2-predefined-symbols-mattr-code-object-v3">
+<span id="amdgpu-amdhsa-assembler-predefined-symbols-v2"></span><h4><a class="toc-backref" href="#id112">Code Object V2 Predefined Symbols (-mattr=-code-object-v3)</a><a class="headerlink" href="#code-object-v2-predefined-symbols-mattr-code-object-v3" title="Permalink to this headline">¶</a></h4>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">Code Object V2 is not the default code object version emitted by
+this version of LLVM. For a description of the predefined symbols available
+with the default configuration (Code Object V3) see
+<a class="reference internal" href="#amdgpu-amdhsa-assembler-predefined-symbols-v3"><span class="std std-ref">Code Object V3 Predefined Symbols (-mattr=+code-object-v3)</span></a>.</p>
+</div>
+<p>The AMDGPU assembler defines and updates some symbols automatically. These
+symbols do not affect code generation.</p>
+<div class="section" id="option-machine-version-major">
+<h5><a class="toc-backref" href="#id113">.option.machine_version_major</a><a class="headerlink" href="#option-machine-version-major" title="Permalink to this headline">¶</a></h5>
+<p>Set to the GFX major generation number of the target being assembled for. For
+example, when assembling for a âGFX9â target this will be set to the integer
+value â9â. The possible GFX major generation numbers are presented in
+<a class="reference internal" href="#amdgpu-processors"><span class="std std-ref">Processors</span></a>.</p>
+</div>
+<div class="section" id="option-machine-version-minor">
+<h5><a class="toc-backref" href="#id114">.option.machine_version_minor</a><a class="headerlink" href="#option-machine-version-minor" title="Permalink to this headline">¶</a></h5>
+<p>Set to the GFX minor generation number of the target being assembled for. For
+example, when assembling for a âGFX810â target this will be set to the integer
+value â1â. The possible GFX minor generation numbers are presented in
+<a class="reference internal" href="#amdgpu-processors"><span class="std std-ref">Processors</span></a>.</p>
+</div>
+<div class="section" id="option-machine-version-stepping">
+<h5><a class="toc-backref" href="#id115">.option.machine_version_stepping</a><a class="headerlink" href="#option-machine-version-stepping" title="Permalink to this headline">¶</a></h5>
+<p>Set to the GFX stepping generation number of the target being assembled for.
+For example, when assembling for a âGFX704â target this will be set to the
+integer value â4â. The possible GFX stepping generation numbers are presented
+in <a class="reference internal" href="#amdgpu-processors"><span class="std std-ref">Processors</span></a>.</p>
+</div>
+<div class="section" id="kernel-vgpr-count">
+<h5><a class="toc-backref" href="#id116">.kernel.vgpr_count</a><a class="headerlink" href="#kernel-vgpr-count" title="Permalink to this headline">¶</a></h5>
+<p>Set to zero each time a
+<a class="reference internal" href="#amdgpu-amdhsa-assembler-directive-amdgpu-hsa-kernel"><span class="std std-ref">.amdgpu_hsa_kernel (name)</span></a> directive is
+encountered. At each instruction, if the current value of this symbol is less
+than or equal to the maximum VPGR number explicitly referenced within that
+instruction then the symbol value is updated to equal that VGPR number plus
+one.</p>
+</div>
+<div class="section" id="kernel-sgpr-count">
+<h5><a class="toc-backref" href="#id117">.kernel.sgpr_count</a><a class="headerlink" href="#kernel-sgpr-count" title="Permalink to this headline">¶</a></h5>
+<p>Set to zero each time a
+<a class="reference internal" href="#amdgpu-amdhsa-assembler-directive-amdgpu-hsa-kernel"><span class="std std-ref">.amdgpu_hsa_kernel (name)</span></a> directive is
+encountered. At each instruction, if the current value of this symbol is less
+than or equal to the maximum VPGR number explicitly referenced within that
+instruction then the symbol value is updated to equal that SGPR number plus
+one.</p>
+</div>
+</div>
+<div class="section" id="code-object-v2-directives-mattr-code-object-v3">
+<span id="amdgpu-amdhsa-assembler-directives-v2"></span><h4><a class="toc-backref" href="#id118">Code Object V2 Directives (-mattr=-code-object-v3)</a><a class="headerlink" href="#code-object-v2-directives-mattr-code-object-v3" title="Permalink to this headline">¶</a></h4>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">Code Object V2 is not the default code object version emitted by
+this version of LLVM. For a description of the directives supported with
+the default configuration (Code Object V3) see
+<a class="reference internal" href="#amdgpu-amdhsa-assembler-directives-v3"><span class="std std-ref">Code Object V3 Directives (-mattr=+code-object-v3)</span></a>.</p>
+</div>
+<p>AMDGPU ABI defines auxiliary data in output code object. In assembly source,
+one can specify them with assembler directives.</p>
+<div class="section" id="hsa-code-object-version-major-minor">
+<h5><a class="toc-backref" href="#id119">.hsa_code_object_version major, minor</a><a class="headerlink" href="#hsa-code-object-version-major-minor" title="Permalink to this headline">¶</a></h5>
+<p><em>major</em> and <em>minor</em> are integers that specify the version of the HSA code
+object that will be generated by the assembler.</p>
+</div>
+<div class="section" id="hsa-code-object-isa-major-minor-stepping-vendor-arch">
+<h5><a class="toc-backref" href="#id120">.hsa_code_object_isa [major, minor, stepping, vendor, arch]</a><a class="headerlink" href="#hsa-code-object-isa-major-minor-stepping-vendor-arch" title="Permalink to this headline">¶</a></h5>
+<p><em>major</em>, <em>minor</em>, and <em>stepping</em> are all integers that describe the instruction
+set architecture (ISA) version of the assembly program.</p>
+<p><em>vendor</em> and <em>arch</em> are quoted strings. <em>vendor</em> should always be equal to
+âAMDâ and <em>arch</em> should always be equal to âAMDGPUâ.</p>
+<p>By default, the assembler will derive the ISA version, <em>vendor</em>, and <em>arch</em>
+from the value of the -mcpu option that is passed to the assembler.</p>
+</div>
+<div class="section" id="amdgpu-hsa-kernel-name">
+<span id="amdgpu-amdhsa-assembler-directive-amdgpu-hsa-kernel"></span><h5><a class="toc-backref" href="#id121">.amdgpu_hsa_kernel (name)</a><a class="headerlink" href="#amdgpu-hsa-kernel-name" title="Permalink to this headline">¶</a></h5>
+<p>This directives specifies that the symbol with given name is a kernel entry point
+(label) and the object should contain corresponding symbol of type STT_AMDGPU_HSA_KERNEL.</p>
+</div>
+<div class="section" id="amd-kernel-code-t">
+<h5><a class="toc-backref" href="#id122">.amd_kernel_code_t</a><a class="headerlink" href="#amd-kernel-code-t" title="Permalink to this headline">¶</a></h5>
+<p>This directive marks the beginning of a list of key / value pairs that are used
+to specify the amd_kernel_code_t object that will be emitted by the assembler.
+The list must be terminated by the <em>.end_amd_kernel_code_t</em> directive. For
+any amd_kernel_code_t values that are unspecified a default value will be
+used. The default value for all keys is 0, with the following exceptions:</p>
+<ul class="simple">
+<li><em>amd_code_version_major</em> defaults to 1.</li>
+<li><em>amd_kernel_code_version_minor</em> defaults to 2.</li>
+<li><em>amd_machine_kind</em> defaults to 1.</li>
+<li><em>amd_machine_version_major</em>, <em>machine_version_minor</em>, and
+<em>amd_machine_version_stepping</em> are derived from the value of the -mcpu option
+that is passed to the assembler.</li>
+<li><em>kernel_code_entry_byte_offset</em> defaults to 256.</li>
+<li><em>wavefront_size</em> defaults 6 for all targets before GFX10. For GFX10 onwards
+defaults to 6 if target feature <code class="docutils literal notranslate"><span class="pre">wavefrontsize64</span></code> is enabled, otherwise 5.
+Note that wavefront size is specified as a power of two, so a value of <strong>n</strong>
+means a size of 2^ <strong>n</strong>.</li>
+<li><em>call_convention</em> defaults to -1.</li>
+<li><em>kernarg_segment_alignment</em>, <em>group_segment_alignment</em>, and
+<em>private_segment_alignment</em> default to 4. Note that alignments are specified
+as a power of 2, so a value of <strong>n</strong> means an alignment of 2^ <strong>n</strong>.</li>
+<li><em>enable_wgp_mode</em> defaults to 1 if target feature <code class="docutils literal notranslate"><span class="pre">cumode</span></code> is disabled for
+GFX10 onwards.</li>
+<li><em>enable_mem_ordered</em> defaults to 1 for GFX10 onwards.</li>
+</ul>
+<p>The <em>.amd_kernel_code_t</em> directive must be placed immediately after the
+function label and before any instructions.</p>
+<p>For a full list of amd_kernel_code_t keys, refer to AMDGPU ABI document,
+comments in lib/Target/AMDGPU/AmdKernelCodeT.h and test/CodeGen/AMDGPU/hsa.s.</p>
+</div>
+</div>
+<div class="section" id="code-object-v2-example-source-code-mattr-code-object-v3">
+<span id="amdgpu-amdhsa-assembler-example-v2"></span><h4><a class="toc-backref" href="#id123">Code Object V2 Example Source Code (-mattr=-code-object-v3)</a><a class="headerlink" href="#code-object-v2-example-source-code-mattr-code-object-v3" title="Permalink to this headline">¶</a></h4>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">Code Object V2 is not the default code object version emitted by
+this version of LLVM. For a description of the directives supported with
+the default configuration (Code Object V3) see
+<a class="reference internal" href="#amdgpu-amdhsa-assembler-example-v3"><span class="std std-ref">Code Object V3 Example Source Code (-mattr=+code-object-v3)</span></a>.</p>
+</div>
+<p>Here is an example of a minimal assembly source file, defining one HSA kernel:</p>
+<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>.hsa_code_object_version 1,0
+.hsa_code_object_isa
+
+.hsatext
+.globl hello_world
+.p2align 8
+.amdgpu_hsa_kernel hello_world
+
+hello_world:
+
+ .amd_kernel_code_t
+ enable_sgpr_kernarg_segment_ptr = 1
+ is_ptr64 = 1
+ compute_pgm_rsrc1_vgprs = 0
+ compute_pgm_rsrc1_sgprs = 0
+ compute_pgm_rsrc2_user_sgpr = 2
+ compute_pgm_rsrc1_wgp_mode = 0
+ compute_pgm_rsrc1_mem_ordered = 0
+ compute_pgm_rsrc1_fwd_progress = 1
+ .end_amd_kernel_code_t
+
+ s_load_dwordx2 s[0:1], s[0:1] 0x0
+ v_mov_b32 v0, 3.14159
+ s_waitcnt lgkmcnt(0)
+ v_mov_b32 v1, s0
+ v_mov_b32 v2, s1
+ flat_store_dword v[1:2], v0
+ s_endpgm
+.Lfunc_end0:
+ .size hello_world, .Lfunc_end0-hello_world
+</pre></div>
+</div>
+</div>
+<div class="section" id="code-object-v3-predefined-symbols-mattr-code-object-v3">
+<span id="amdgpu-amdhsa-assembler-predefined-symbols-v3"></span><h4><a class="toc-backref" href="#id124">Code Object V3 Predefined Symbols (-mattr=+code-object-v3)</a><a class="headerlink" href="#code-object-v3-predefined-symbols-mattr-code-object-v3" title="Permalink to this headline">¶</a></h4>
+<p>The AMDGPU assembler defines and updates some symbols automatically. These
+symbols do not affect code generation.</p>
+<div class="section" id="amdgcn-gfx-generation-number">
+<h5><a class="toc-backref" href="#id125">.amdgcn.gfx_generation_number</a><a class="headerlink" href="#amdgcn-gfx-generation-number" title="Permalink to this headline">¶</a></h5>
+<p>Set to the GFX major generation number of the target being assembled for. For
+example, when assembling for a âGFX9â target this will be set to the integer
+value â9â. The possible GFX major generation numbers are presented in
+<a class="reference internal" href="#amdgpu-processors"><span class="std std-ref">Processors</span></a>.</p>
+</div>
+<div class="section" id="amdgcn-gfx-generation-minor">
+<h5><a class="toc-backref" href="#id126">.amdgcn.gfx_generation_minor</a><a class="headerlink" href="#amdgcn-gfx-generation-minor" title="Permalink to this headline">¶</a></h5>
+<p>Set to the GFX minor generation number of the target being assembled for. For
+example, when assembling for a âGFX810â target this will be set to the integer
+value â1â. The possible GFX minor generation numbers are presented in
+<a class="reference internal" href="#amdgpu-processors"><span class="std std-ref">Processors</span></a>.</p>
+</div>
+<div class="section" id="amdgcn-gfx-generation-stepping">
+<h5><a class="toc-backref" href="#id127">.amdgcn.gfx_generation_stepping</a><a class="headerlink" href="#amdgcn-gfx-generation-stepping" title="Permalink to this headline">¶</a></h5>
+<p>Set to the GFX stepping generation number of the target being assembled for.
+For example, when assembling for a âGFX704â target this will be set to the
+integer value â4â. The possible GFX stepping generation numbers are presented
+in <a class="reference internal" href="#amdgpu-processors"><span class="std std-ref">Processors</span></a>.</p>
+</div>
+<div class="section" id="amdgcn-next-free-vgpr">
+<span id="amdgpu-amdhsa-assembler-symbol-next-free-vgpr"></span><h5><a class="toc-backref" href="#id128">.amdgcn.next_free_vgpr</a><a class="headerlink" href="#amdgcn-next-free-vgpr" title="Permalink to this headline">¶</a></h5>
+<p>Set to zero before assembly begins. At each instruction, if the current value
+of this symbol is less than or equal to the maximum VGPR number explicitly
+referenced within that instruction then the symbol value is updated to equal
+that VGPR number plus one.</p>
+<p>May be used to set the <cite>.amdhsa_next_free_vpgr</cite> directive in
+<a class="reference internal" href="#amdhsa-kernel-directives-table"><span class="std std-ref">AMDHSA Kernel Assembler Directives</span></a>.</p>
+<p>May be set at any time, e.g. manually set to zero at the start of each kernel.</p>
+</div>
+<div class="section" id="amdgcn-next-free-sgpr">
+<span id="amdgpu-amdhsa-assembler-symbol-next-free-sgpr"></span><h5><a class="toc-backref" href="#id129">.amdgcn.next_free_sgpr</a><a class="headerlink" href="#amdgcn-next-free-sgpr" title="Permalink to this headline">¶</a></h5>
+<p>Set to zero before assembly begins. At each instruction, if the current value
+of this symbol is less than or equal the maximum SGPR number explicitly
+referenced within that instruction then the symbol value is updated to equal
+that SGPR number plus one.</p>
+<p>May be used to set the <cite>.amdhsa_next_free_spgr</cite> directive in
+<a class="reference internal" href="#amdhsa-kernel-directives-table"><span class="std std-ref">AMDHSA Kernel Assembler Directives</span></a>.</p>
+<p>May be set at any time, e.g. manually set to zero at the start of each kernel.</p>
+</div>
+</div>
+<div class="section" id="code-object-v3-directives-mattr-code-object-v3">
+<span id="amdgpu-amdhsa-assembler-directives-v3"></span><h4><a class="toc-backref" href="#id130">Code Object V3 Directives (-mattr=+code-object-v3)</a><a class="headerlink" href="#code-object-v3-directives-mattr-code-object-v3" title="Permalink to this headline">¶</a></h4>
+<p>Directives which begin with <code class="docutils literal notranslate"><span class="pre">.amdgcn</span></code> are valid for all <code class="docutils literal notranslate"><span class="pre">amdgcn</span></code>
+architecture processors, and are not OS-specific. Directives which begin with
+<code class="docutils literal notranslate"><span class="pre">.amdhsa</span></code> are specific to <code class="docutils literal notranslate"><span class="pre">amdgcn</span></code> architecture processors when the
+<code class="docutils literal notranslate"><span class="pre">amdhsa</span></code> OS is specified. See <a class="reference internal" href="#amdgpu-target-triples"><span class="std std-ref">Target Triples</span></a> and
+<a class="reference internal" href="#amdgpu-processors"><span class="std std-ref">Processors</span></a>.</p>
+<div class="section" id="amdgcn-target-target">
+<h5><a class="toc-backref" href="#id131">.amdgcn_target <target></a><a class="headerlink" href="#amdgcn-target-target" title="Permalink to this headline">¶</a></h5>
+<p>Optional directive which declares the target supported by the containing
+assembler source file. Valid values are described in
+<a class="reference internal" href="#amdgpu-amdhsa-code-object-target-identification"><span class="std std-ref">Code Object Target Identification</span></a>. Used by the assembler
+to validate command-line options such as <code class="docutils literal notranslate"><span class="pre">-triple</span></code>, <code class="docutils literal notranslate"><span class="pre">-mcpu</span></code>, and those
+which specify target features.</p>
+</div>
+<div class="section" id="amdhsa-kernel-name">
+<h5><a class="toc-backref" href="#id132">.amdhsa_kernel <name></a><a class="headerlink" href="#amdhsa-kernel-name" title="Permalink to this headline">¶</a></h5>
+<p>Creates a correctly aligned AMDHSA kernel descriptor and a symbol,
+<code class="docutils literal notranslate"><span class="pre"><name>.kd</span></code>, in the current location of the current section. Only valid when
+the OS is <code class="docutils literal notranslate"><span class="pre">amdhsa</span></code>. <code class="docutils literal notranslate"><span class="pre"><name></span></code> must be a symbol that labels the first
+instruction to execute, and does not need to be previously defined.</p>
+<p>Marks the beginning of a list of directives used to generate the bytes of a
+kernel descriptor, as described in <a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>.
+Directives which may appear in this list are described in
+<a class="reference internal" href="#amdhsa-kernel-directives-table"><span class="std std-ref">AMDHSA Kernel Assembler Directives</span></a>. Directives may appear in any order, must
+be valid for the target being assembled for, and cannot be repeated. Directives
+support the range of values specified by the field they reference in
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor"><span class="std std-ref">Kernel Descriptor</span></a>. If a directive is not specified, it is
+assumed to have its default value, unless it is marked as âRequiredâ, in which
+case it is an error to omit the directive. This list of directives is
+terminated by an <code class="docutils literal notranslate"><span class="pre">.end_amdhsa_kernel</span></code> directive.</p>
+<blockquote>
+<div><table border="1" class="docutils" id="amdhsa-kernel-directives-table">
+<caption><span class="caption-text">AMDHSA Kernel Assembler Directives</span><a class="headerlink" href="#amdhsa-kernel-directives-table" title="Permalink to this table">¶</a></caption>
+<colgroup>
+<col width="35%" />
+<col width="12%" />
+<col width="7%" />
+<col width="46%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head">Directive</th>
+<th class="head">Default</th>
+<th class="head">Supported On</th>
+<th class="head">Description</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_group_segment_fixed_size</span></code></td>
+<td>0</td>
+<td>GFX6-GFX10</td>
+<td>Controls GROUP_SEGMENT_FIXED_SIZE in
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_private_segment_fixed_size</span></code></td>
+<td>0</td>
+<td>GFX6-GFX10</td>
+<td>Controls PRIVATE_SEGMENT_FIXED_SIZE in
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_user_sgpr_private_segment_buffer</span></code></td>
+<td>0</td>
+<td>GFX6-GFX10</td>
+<td>Controls ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER in
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_user_sgpr_dispatch_ptr</span></code></td>
+<td>0</td>
+<td>GFX6-GFX10</td>
+<td>Controls ENABLE_SGPR_DISPATCH_PTR in
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_user_sgpr_queue_ptr</span></code></td>
+<td>0</td>
+<td>GFX6-GFX10</td>
+<td>Controls ENABLE_SGPR_QUEUE_PTR in
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_user_sgpr_kernarg_segment_ptr</span></code></td>
+<td>0</td>
+<td>GFX6-GFX10</td>
+<td>Controls ENABLE_SGPR_KERNARG_SEGMENT_PTR in
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_user_sgpr_dispatch_id</span></code></td>
+<td>0</td>
+<td>GFX6-GFX10</td>
+<td>Controls ENABLE_SGPR_DISPATCH_ID in
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_user_sgpr_flat_scratch_init</span></code></td>
+<td>0</td>
+<td>GFX6-GFX10</td>
+<td>Controls ENABLE_SGPR_FLAT_SCRATCH_INIT in
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_user_sgpr_private_segment_size</span></code></td>
+<td>0</td>
+<td>GFX6-GFX10</td>
+<td>Controls ENABLE_SGPR_PRIVATE_SEGMENT_SIZE in
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_wavefront_size32</span></code></td>
+<td>Target
+Feature
+Specific
+(-wavefrontsize64)</td>
+<td>GFX10</td>
+<td>Controls ENABLE_WAVEFRONT_SIZE32 in
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_system_sgpr_private_segment_wavefront_offset</span></code></td>
+<td>0</td>
+<td>GFX6-GFX10</td>
+<td>Controls ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_system_sgpr_workgroup_id_x</span></code></td>
+<td>1</td>
+<td>GFX6-GFX10</td>
+<td>Controls ENABLE_SGPR_WORKGROUP_ID_X in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_system_sgpr_workgroup_id_y</span></code></td>
+<td>0</td>
+<td>GFX6-GFX10</td>
+<td>Controls ENABLE_SGPR_WORKGROUP_ID_Y in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_system_sgpr_workgroup_id_z</span></code></td>
+<td>0</td>
+<td>GFX6-GFX10</td>
+<td>Controls ENABLE_SGPR_WORKGROUP_ID_Z in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_system_sgpr_workgroup_info</span></code></td>
+<td>0</td>
+<td>GFX6-GFX10</td>
+<td>Controls ENABLE_SGPR_WORKGROUP_INFO in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_system_vgpr_workitem_id</span></code></td>
+<td>0</td>
+<td>GFX6-GFX10</td>
+<td>Controls ENABLE_VGPR_WORKITEM_ID in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX10</span></a>.
+Possible values are defined in
+<a class="reference internal" href="#amdgpu-amdhsa-system-vgpr-work-item-id-enumeration-values-table"><span class="std std-ref">System VGPR Work-Item ID Enumeration Values</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_next_free_vgpr</span></code></td>
+<td>Required</td>
+<td>GFX6-GFX10</td>
+<td>Maximum VGPR number explicitly referenced, plus one.
+Used to calculate GRANULATED_WORKITEM_VGPR_COUNT in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_next_free_sgpr</span></code></td>
+<td>Required</td>
+<td>GFX6-GFX10</td>
+<td>Maximum SGPR number explicitly referenced, plus one.
+Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_reserve_vcc</span></code></td>
+<td>1</td>
+<td>GFX6-GFX10</td>
+<td>Whether the kernel may use the special VCC SGPR.
+Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_reserve_flat_scratch</span></code></td>
+<td>1</td>
+<td>GFX7-GFX10</td>
+<td>Whether the kernel may use flat instructions to access
+scratch memory. Used to calculate
+GRANULATED_WAVEFRONT_SGPR_COUNT in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_reserve_xnack_mask</span></code></td>
+<td>Target
+Feature
+Specific
+(+xnack)</td>
+<td>GFX8-GFX10</td>
+<td>Whether the kernel may trigger XNACK replay.
+Used to calculate GRANULATED_WAVEFRONT_SGPR_COUNT in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_float_round_mode_32</span></code></td>
+<td>0</td>
+<td>GFX6-GFX10</td>
+<td>Controls FLOAT_ROUND_MODE_32 in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX10</span></a>.
+Possible values are defined in
+<a class="reference internal" href="#amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table"><span class="std std-ref">Floating Point Rounding Mode Enumeration Values</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_float_round_mode_16_64</span></code></td>
+<td>0</td>
+<td>GFX6-GFX10</td>
+<td>Controls FLOAT_ROUND_MODE_16_64 in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX10</span></a>.
+Possible values are defined in
+<a class="reference internal" href="#amdgpu-amdhsa-floating-point-rounding-mode-enumeration-values-table"><span class="std std-ref">Floating Point Rounding Mode Enumeration Values</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_float_denorm_mode_32</span></code></td>
+<td>0</td>
+<td>GFX6-GFX10</td>
+<td>Controls FLOAT_DENORM_MODE_32 in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX10</span></a>.
+Possible values are defined in
+<a class="reference internal" href="#amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table"><span class="std std-ref">Floating Point Denorm Mode Enumeration Values</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_float_denorm_mode_16_64</span></code></td>
+<td>3</td>
+<td>GFX6-GFX10</td>
+<td>Controls FLOAT_DENORM_MODE_16_64 in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX10</span></a>.
+Possible values are defined in
+<a class="reference internal" href="#amdgpu-amdhsa-floating-point-denorm-mode-enumeration-values-table"><span class="std std-ref">Floating Point Denorm Mode Enumeration Values</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_dx10_clamp</span></code></td>
+<td>1</td>
+<td>GFX6-GFX10</td>
+<td>Controls ENABLE_DX10_CLAMP in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_ieee_mode</span></code></td>
+<td>1</td>
+<td>GFX6-GFX10</td>
+<td>Controls ENABLE_IEEE_MODE in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_fp16_overflow</span></code></td>
+<td>0</td>
+<td>GFX9-GFX10</td>
+<td>Controls FP16_OVFL in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_workgroup_processor_mode</span></code></td>
+<td>Target
+Feature
+Specific
+(-cumode)</td>
+<td>GFX10</td>
+<td>Controls ENABLE_WGP_MODE in
+<a class="reference internal" href="#amdgpu-amdhsa-kernel-descriptor-gfx6-gfx10-table"><span class="std std-ref">Kernel Descriptor for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_memory_ordered</span></code></td>
+<td>1</td>
+<td>GFX10</td>
+<td>Controls MEM_ORDERED in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_forward_progress</span></code></td>
+<td>0</td>
+<td>GFX10</td>
+<td>Controls FWD_PROGRESS in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc1-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc1 for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_exception_fp_ieee_invalid_op</span></code></td>
+<td>0</td>
+<td>GFX6-GFX10</td>
+<td>Controls ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_exception_fp_denorm_src</span></code></td>
+<td>0</td>
+<td>GFX6-GFX10</td>
+<td>Controls ENABLE_EXCEPTION_FP_DENORMAL_SOURCE in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_exception_fp_ieee_div_zero</span></code></td>
+<td>0</td>
+<td>GFX6-GFX10</td>
+<td>Controls ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_exception_fp_ieee_overflow</span></code></td>
+<td>0</td>
+<td>GFX6-GFX10</td>
+<td>Controls ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_exception_fp_ieee_underflow</span></code></td>
+<td>0</td>
+<td>GFX6-GFX10</td>
+<td>Controls ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-even"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_exception_fp_ieee_inexact</span></code></td>
+<td>0</td>
+<td>GFX6-GFX10</td>
+<td>Controls ENABLE_EXCEPTION_IEEE_754_FP_INEXACT in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX10</span></a>.</td>
+</tr>
+<tr class="row-odd"><td><code class="docutils literal notranslate"><span class="pre">.amdhsa_exception_int_div_zero</span></code></td>
+<td>0</td>
+<td>GFX6-GFX10</td>
+<td>Controls ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO in
+<a class="reference internal" href="#amdgpu-amdhsa-compute-pgm-rsrc2-gfx6-gfx10-table"><span class="std std-ref">compute_pgm_rsrc2 for GFX6-GFX10</span></a>.</td>
+</tr>
+</tbody>
+</table>
+</div></blockquote>
+</div>
+<div class="section" id="amdgpu-metadata">
+<h5><a class="toc-backref" href="#id133">.amdgpu_metadata</a><a class="headerlink" href="#amdgpu-metadata" title="Permalink to this headline">¶</a></h5>
+<p>Optional directive which declares the contents of the <code class="docutils literal notranslate"><span class="pre">NT_AMDGPU_METADATA</span></code>
+note record (see <a class="reference internal" href="#amdgpu-elf-note-records-table-v3"><span class="std std-ref">AMDGPU Code Object V3 ELF Note Records</span></a>).</p>
+<p>The contents must be in the <a class="reference internal" href="#yaml" id="id45">[YAML]</a> markup format, with the same structure and
+semantics described in <a class="reference internal" href="#amdgpu-amdhsa-code-object-metadata-v3"><span class="std std-ref">Code Object V3 Metadata (-mattr=+code-object-v3)</span></a>.</p>
+<p>This directive is terminated by an <code class="docutils literal notranslate"><span class="pre">.end_amdgpu_metadata</span></code> directive.</p>
+</div>
+</div>
+<div class="section" id="code-object-v3-example-source-code-mattr-code-object-v3">
+<span id="amdgpu-amdhsa-assembler-example-v3"></span><h4><a class="toc-backref" href="#id134">Code Object V3 Example Source Code (-mattr=+code-object-v3)</a><a class="headerlink" href="#code-object-v3-example-source-code-mattr-code-object-v3" title="Permalink to this headline">¶</a></h4>
+<p>Here is an example of a minimal assembly source file, defining one HSA kernel:</p>
+<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>.amdgcn_target "amdgcn-amd-amdhsa--gfx900+xnack" // optional
+
+.text
+.globl hello_world
+.p2align 8
+.type hello_world, at function
+hello_world:
+ s_load_dwordx2 s[0:1], s[0:1] 0x0
+ v_mov_b32 v0, 3.14159
+ s_waitcnt lgkmcnt(0)
+ v_mov_b32 v1, s0
+ v_mov_b32 v2, s1
+ flat_store_dword v[1:2], v0
+ s_endpgm
+.Lfunc_end0:
+ .size hello_world, .Lfunc_end0-hello_world
+
+.rodata
+.p2align 6
+.amdhsa_kernel hello_world
+ .amdhsa_user_sgpr_kernarg_segment_ptr 1
+ .amdhsa_next_free_vgpr .amdgcn.next_free_vgpr
+ .amdhsa_next_free_sgpr .amdgcn.next_free_sgpr
+.end_amdhsa_kernel
+
+.amdgpu_metadata
+---
+amdhsa.version:
+ - 1
+ - 0
+amdhsa.kernels:
+ - .name: hello_world
+ .symbol: hello_world.kd
+ .kernarg_segment_size: 48
+ .group_segment_fixed_size: 0
+ .private_segment_fixed_size: 0
+ .kernarg_segment_align: 4
+ .wavefront_size: 64
+ .sgpr_count: 2
+ .vgpr_count: 3
+ .max_flat_workgroup_size: 256
+...
+.end_amdgpu_metadata
+</pre></div>
+</div>
+<p>If an assembly source file contains multiple kernels and/or functions, the
+<a class="reference internal" href="#amdgpu-amdhsa-assembler-symbol-next-free-vgpr"><span class="std std-ref">.amdgcn.next_free_vgpr</span></a> and
+<a class="reference internal" href="#amdgpu-amdhsa-assembler-symbol-next-free-sgpr"><span class="std std-ref">.amdgcn.next_free_sgpr</span></a> symbols may be reset using
+the <code class="docutils literal notranslate"><span class="pre">.set</span> <span class="pre"><symbol>,</span> <span class="pre"><expression></span></code> directive. For example, in the case of two
+kernels, where <code class="docutils literal notranslate"><span class="pre">function1</span></code> is only called from <code class="docutils literal notranslate"><span class="pre">kernel1</span></code> it is sufficient
+to group the function with the kernel that calls it and reset the symbols
+between the two connected components:</p>
+<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>.amdgcn_target "amdgcn-amd-amdhsa--gfx900+xnack" // optional
+
+// gpr tracking symbols are implicitly set to zero
+
+.text
+.globl kern0
+.p2align 8
+.type kern0, at function
+kern0:
+ // ...
+ s_endpgm
+.Lkern0_end:
+ .size kern0, .Lkern0_end-kern0
+
+.rodata
+.p2align 6
+.amdhsa_kernel kern0
+ // ...
+ .amdhsa_next_free_vgpr .amdgcn.next_free_vgpr
+ .amdhsa_next_free_sgpr .amdgcn.next_free_sgpr
+.end_amdhsa_kernel
+
+// reset symbols to begin tracking usage in func1 and kern1
+.set .amdgcn.next_free_vgpr, 0
+.set .amdgcn.next_free_sgpr, 0
+
+.text
+.hidden func1
+.global func1
+.p2align 2
+.type func1, at function
+func1:
+ // ...
+ s_setpc_b64 s[30:31]
+.Lfunc1_end:
+.size func1, .Lfunc1_end-func1
+
+.globl kern1
+.p2align 8
+.type kern1, at function
+kern1:
+ // ...
+ s_getpc_b64 s[4:5]
+ s_add_u32 s4, s4, func1 at rel32@lo+4
+ s_addc_u32 s5, s5, func1 at rel32@lo+4
+ s_swappc_b64 s[30:31], s[4:5]
+ // ...
+ s_endpgm
+.Lkern1_end:
+ .size kern1, .Lkern1_end-kern1
+
+.rodata
+.p2align 6
+.amdhsa_kernel kern1
+ // ...
+ .amdhsa_next_free_vgpr .amdgcn.next_free_vgpr
+ .amdhsa_next_free_sgpr .amdgcn.next_free_sgpr
+.end_amdhsa_kernel
+</pre></div>
+</div>
+<p>These symbols cannot identify connected components in order to automatically
+track the usage for each kernel. However, in some cases careful organization of
+the kernels and functions in the source file means there is minimal additional
+effort required to accurately calculate GPR usage.</p>
+</div>
+</div>
+</div>
+<div class="section" id="additional-documentation">
+<h2><a class="toc-backref" href="#id135">Additional Documentation</a><a class="headerlink" href="#additional-documentation" title="Permalink to this headline">¶</a></h2>
+<table class="docutils citation" frame="void" id="amd-radeon-hd-2000-3000" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label"><a class="fn-backref" href="#id3">[AMD-RADEON-HD-2000-3000]</a></td><td><a class="reference external" href="http://developer.amd.com/wordpress/media/2012/10/R600_Instruction_Set_Architecture.pdf">AMD R6xx shader ISA</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-radeon-hd-4000" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label"><a class="fn-backref" href="#id4">[AMD-RADEON-HD-4000]</a></td><td><a class="reference external" href="http://developer.amd.com/wordpress/media/2012/10/R700-Family_Instruction_Set_Architecture.pdf">AMD R7xx shader ISA</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-radeon-hd-5000" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label"><a class="fn-backref" href="#id5">[AMD-RADEON-HD-5000]</a></td><td><a class="reference external" href="http://developer.amd.com/wordpress/media/2012/10/AMD_Evergreen-Family_Instruction_Set_Architecture.pdf">AMD Evergreen shader ISA</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-radeon-hd-6000" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label"><a class="fn-backref" href="#id6">[AMD-RADEON-HD-6000]</a></td><td><a class="reference external" href="http://developer.amd.com/wordpress/media/2012/10/AMD_HD_6900_Series_Instruction_Set_Architecture.pdf">AMD Cayman/Trinity shader ISA</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-gcn-gfx6" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[AMD-GCN-GFX6]</td><td><em>(<a class="fn-backref" href="#id7">1</a>, <a class="fn-backref" href="#id40">2</a>)</em> <a class="reference external" href="http://developer.amd.com/wordpress/media/2012/12/AMD_Southern_Islands_Instruction_Set_Architecture.pdf">AMD Southern Islands Series ISA</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-gcn-gfx7" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[AMD-GCN-GFX7]</td><td><em>(<a class="fn-backref" href="#id8">1</a>, <a class="fn-backref" href="#id41">2</a>)</em> <a class="reference external" href="http://developer.amd.com/wordpress/media/2013/07/AMD_Sea_Islands_Instruction_Set_Architecture.pdf">AMD Sea Islands Series ISA</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-gcn-gfx8" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[AMD-GCN-GFX8]</td><td><em>(<a class="fn-backref" href="#id9">1</a>, <a class="fn-backref" href="#id42">2</a>)</em> <a class="reference external" href="http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2013/12/AMD_GCN3_Instruction_Set_Architecture_rev1.1.pdf">AMD GCN3 Instruction Set Architecture</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-gcn-gfx9" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[AMD-GCN-GFX9]</td><td><em>(<a class="fn-backref" href="#id10">1</a>, <a class="fn-backref" href="#id43">2</a>)</em> <a class="reference external" href="http://developer.amd.com/wordpress/media/2013/12/Vega_Shader_ISA_28July2017.pdf">AMD âVegaâ Instruction Set Architecture</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-gcn-gfx10" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[AMD-GCN-GFX10]</td><td><em>(<a class="fn-backref" href="#id11">1</a>, <a class="fn-backref" href="#id44">2</a>)</em> AMD âNaviâ Instruction Set Architecture <em>TBA</em></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-rocm" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[AMD-ROCm]</td><td><em>(<a class="fn-backref" href="#id2">1</a>, <a class="fn-backref" href="#id22">2</a>, <a class="fn-backref" href="#id27">3</a>, <a class="fn-backref" href="#id38">4</a>)</em> <a class="reference external" href="http://gpuopen.com/compute-product/rocm/">ROCm: Open Platform for Development, Discovery and Education Around GPU Computing</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="amd-rocm-github" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[AMD-ROCm-github]</td><td><em>(<a class="fn-backref" href="#id33">1</a>, <a class="fn-backref" href="#id34">2</a>)</em> <a class="reference external" href="http://github.com/RadeonOpenCompute">ROCm github</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="hsa" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[HSA]</td><td><em>(<a class="fn-backref" href="#id1">1</a>, <a class="fn-backref" href="#id12">2</a>, <a class="fn-backref" href="#id21">3</a>, <a class="fn-backref" href="#id26">4</a>, <a class="fn-backref" href="#id30">5</a>, <a class="fn-backref" href="#id31">6</a>, <a class="fn-backref" href="#id32">7</a>, <a class="fn-backref" href="#id35">8</a>, <a class="fn-backref" href="#id37">9</a>)</em> <a class="reference external" href="http://www.hsafoundation.com/">Heterogeneous System Architecture (HSA) Foundation</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="elf" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[ELF]</td><td><em>(<a class="fn-backref" href="#id19">1</a>, <a class="fn-backref" href="#id20">2</a>)</em> <a class="reference external" href="http://www.sco.com/developers/gabi/">Executable and Linkable Format (ELF)</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="id46" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label"><a class="fn-backref" href="#id25">[DWARF]</a></td><td><a class="reference external" href="http://dwarfstd.org/">DWARF Debugging Information Format</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="yaml" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[YAML]</td><td><em>(<a class="fn-backref" href="#id28">1</a>, <a class="fn-backref" href="#id45">2</a>)</em> <a class="reference external" href="http://www.yaml.org/spec/1.2/spec.html">YAML Ainât Markup Language (YAMLâ¢) Version 1.2</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="msgpack" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[MsgPack]</td><td><em>(<a class="fn-backref" href="#id23">1</a>, <a class="fn-backref" href="#id24">2</a>, <a class="fn-backref" href="#id29">3</a>)</em> <a class="reference external" href="http://www.msgpack.org/">Message Pack</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="id47" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[OpenCL]</td><td><em>(<a class="fn-backref" href="#id14">1</a>, <a class="fn-backref" href="#id36">2</a>)</em> <a class="reference external" href="http://www.khronos.org/registry/cl/specs/opencl-2.0.pdf">The OpenCL Specification Version 2.0</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="hrf" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label"><a class="fn-backref" href="#id13">[HRF]</a></td><td><a class="reference external" href="http://benedictgaster.org/wp-content/uploads/2014/01/asplos269-FINAL.pdf">Heterogeneous-race-free Memory Models</a></td></tr>
+</tbody>
+</table>
+<table class="docutils citation" frame="void" id="clang-attr" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label">[CLANG-ATTR]</td><td><em>(<a class="fn-backref" href="#id15">1</a>, <a class="fn-backref" href="#id16">2</a>, <a class="fn-backref" href="#id17">3</a>, <a class="fn-backref" href="#id18">4</a>)</em> <a class="reference external" href="http://clang.llvm.org/docs/AttributeReference.html">Attributes in Clang</a></td></tr>
+</tbody>
+</table>
+</div>
+</div>
+
+
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+
+ <div class="section" id="how-to-add-a-constrained-floating-point-intrinsic">
+<h1>How To Add A Constrained Floating-Point Intrinsic<a class="headerlink" href="#how-to-add-a-constrained-floating-point-intrinsic" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#add-the-intrinsic" id="id1">Add the intrinsic</a></li>
+<li><a class="reference internal" href="#add-selectiondag-node-types" id="id2">Add SelectionDAG node types</a><ul>
+<li><a class="reference internal" href="#building-the-selectiondag" id="id3">Building the SelectionDAG</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#add-documentation-and-tests" id="id4">Add documentation and tests</a></li>
+</ul>
+</div>
+<div class="admonition warning">
+<p class="first admonition-title">Warning</p>
+<p class="last">This is a work in progress.</p>
+</div>
+<div class="section" id="add-the-intrinsic">
+<h2><a class="toc-backref" href="#id1">Add the intrinsic</a><a class="headerlink" href="#add-the-intrinsic" title="Permalink to this headline">¶</a></h2>
+<p>Multiple files need to be updated when adding a new constrained intrinsic.</p>
+<p>Add the new intrinsic to the table of intrinsics.:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">include</span><span class="o">/</span><span class="n">llvm</span><span class="o">/</span><span class="n">IR</span><span class="o">/</span><span class="n">Intrinsics</span><span class="o">.</span><span class="n">td</span>
+</pre></div>
+</div>
+<p>Update class ConstrainedFPIntrinsic to know about the intrinsics.:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">include</span><span class="o">/</span><span class="n">llvm</span><span class="o">/</span><span class="n">IR</span><span class="o">/</span><span class="n">IntrinsicInst</span><span class="o">.</span><span class="n">h</span>
+</pre></div>
+</div>
+<p>Functions like ConstrainedFPIntrinsic::isUnaryOp() or
+ConstrainedFPIntrinsic::isTernaryOp() may need to know about the new
+intrinsic.:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">lib</span><span class="o">/</span><span class="n">IR</span><span class="o">/</span><span class="n">IntrinsicInst</span><span class="o">.</span><span class="n">cpp</span>
+</pre></div>
+</div>
+<p>Update the IR verifier:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">lib</span><span class="o">/</span><span class="n">IR</span><span class="o">/</span><span class="n">Verifier</span><span class="o">.</span><span class="n">cpp</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="add-selectiondag-node-types">
+<h2><a class="toc-backref" href="#id2">Add SelectionDAG node types</a><a class="headerlink" href="#add-selectiondag-node-types" title="Permalink to this headline">¶</a></h2>
+<p>Add the new STRICT version of the node type to the ISD::NodeType enum.:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">include</span><span class="o">/</span><span class="n">llvm</span><span class="o">/</span><span class="n">CodeGen</span><span class="o">/</span><span class="n">ISDOpcodes</span><span class="o">.</span><span class="n">h</span>
+</pre></div>
+</div>
+<p>In class SDNode update isStrictFPOpcode():</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">include</span><span class="o">/</span><span class="n">llvm</span><span class="o">/</span><span class="n">CodeGen</span><span class="o">/</span><span class="n">SelectionDAGNodes</span><span class="o">.</span><span class="n">h</span>
+</pre></div>
+</div>
+<p>A mapping from the STRICT SDnode type to the non-STRICT is done in
+TargetLoweringBase::getStrictFPOperationAction(). This allows STRICT
+nodes to be legalized similarly to the non-STRICT node type.:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">include</span><span class="o">/</span><span class="n">llvm</span><span class="o">/</span><span class="n">CodeGen</span><span class="o">/</span><span class="n">TargetLowering</span><span class="o">.</span><span class="n">h</span>
+</pre></div>
+</div>
+<div class="section" id="building-the-selectiondag">
+<h3><a class="toc-backref" href="#id3">Building the SelectionDAG</a><a class="headerlink" href="#building-the-selectiondag" title="Permalink to this headline">¶</a></h3>
+<p>The switch statement in SelectionDAGBuilder::visitIntrinsicCall() needs
+to be updated to call SelectionDAGBuilder::visitConstrainedFPIntrinsic().
+That function, in turn, needs to be updated to know how to create the
+SDNode for the intrinsic. The new STRICT node will eventually be converted
+to the matching non-STRICT node. For this reason it should have the same
+operands and values as the non-STRICT version but should also use the chain.
+This makes subsequent sharing of code for STRICT and non-STRICT code paths
+easier.:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">lib</span><span class="o">/</span><span class="n">CodeGen</span><span class="o">/</span><span class="n">SelectionDAG</span><span class="o">/</span><span class="n">SelectionDAGBuilder</span><span class="o">.</span><span class="n">cpp</span>
+</pre></div>
+</div>
+<p>Most of the STRICT nodes get legalized the same as their matching non-STRICT
+counterparts. A new STRICT node with this property must get added to the
+switch in SelectionDAGLegalize::LegalizeOp().:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">lib</span><span class="o">/</span><span class="n">CodeGen</span><span class="o">/</span><span class="n">SelectionDAG</span><span class="o">/</span><span class="n">LegalizeDAG</span><span class="o">.</span><span class="n">cpp</span>
+</pre></div>
+</div>
+<p>Other parts of the legalizer may need to be updated as well. Look for
+places where the non-STRICT counterpart is legalized and update as needed.
+Be careful of the chain since STRICT nodes use it but their counterparts
+often donât.</p>
+<p>The code to do the conversion or mutation of the STRICT node to a non-STRICT
+version of the node happens in SelectionDAG::mutateStrictFPToFP(). Be
+careful updating this function since some nodes have the same return type
+as their input operand, but some are different. Both of these cases must
+be properly handled.:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">lib</span><span class="o">/</span><span class="n">CodeGen</span><span class="o">/</span><span class="n">SelectionDAG</span><span class="o">/</span><span class="n">SelectionDAG</span><span class="o">.</span><span class="n">cpp</span>
+</pre></div>
+</div>
+<p>However, the mutation may not happen if the new node has not been registered
+in TargetLoweringBase::initActions(). If the corresponding non-STRICT node
+is Legal but a target does not know about STRICT nodes then the STRICT
+node will default to Legal and mutation will be bypassed with a âCannot
+selectâ error. Register the new STRICT node as Expand to avoid this bug.:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">lib</span><span class="o">/</span><span class="n">CodeGen</span><span class="o">/</span><span class="n">TargetLoweringBase</span><span class="o">.</span><span class="n">cpp</span>
+</pre></div>
+</div>
+<p>To make debug logs readable it is helpful to update the SelectionDAGâs
+debug logger::</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">lib</span><span class="o">/</span><span class="n">CodeGen</span><span class="o">/</span><span class="n">SelectionDAG</span><span class="o">/</span><span class="n">SelectionDAGDumper</span><span class="o">.</span><span class="n">cpp</span>
+</pre></div>
+</div>
+</div>
+</div>
+<div class="section" id="add-documentation-and-tests">
+<h2><a class="toc-backref" href="#id4">Add documentation and tests</a><a class="headerlink" href="#add-documentation-and-tests" title="Permalink to this headline">¶</a></h2>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">docs</span><span class="o">/</span><span class="n">LangRef</span><span class="o">.</span><span class="n">rst</span>
+</pre></div>
+</div>
+</div>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
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+ <div class="section" id="advanced-build-configurations">
+<h1>Advanced Build Configurations<a class="headerlink" href="#advanced-build-configurations" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#introduction" id="id1">Introduction</a></li>
+<li><a class="reference internal" href="#bootstrap-builds" id="id2">Bootstrap Builds</a></li>
+<li><a class="reference internal" href="#apple-clang-builds-a-more-complex-bootstrap" id="id3">Apple Clang Builds (A More Complex Bootstrap)</a></li>
+<li><a class="reference internal" href="#multi-stage-pgo" id="id4">Multi-stage PGO</a></li>
+<li><a class="reference internal" href="#stage-non-determinism" id="id5">3-Stage Non-Determinism</a></li>
+</ul>
+</div>
+<div class="section" id="introduction">
+<h2><a class="toc-backref" href="#id1">Introduction</a><a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
+<p><a class="reference external" href="http://www.cmake.org/">CMake</a> is a cross-platform build-generator tool. CMake
+does not build the project, it generates the files needed by your build tool
+(GNU make, Visual Studio, etc.) for building LLVM.</p>
+<p>If <strong>you are a new contributor</strong>, please start with the <a class="reference internal" href="GettingStarted.html"><span class="doc">Getting Started with the LLVM System</span></a> or
+<a class="reference internal" href="CMake.html"><span class="doc">Building LLVM with CMake</span></a> pages. This page is intended for users doing more complex builds.</p>
+<p>Many of the examples below are written assuming specific CMake Generators.
+Unless otherwise explicitly called out these commands should work with any CMake
+generator.</p>
+</div>
+<div class="section" id="bootstrap-builds">
+<h2><a class="toc-backref" href="#id2">Bootstrap Builds</a><a class="headerlink" href="#bootstrap-builds" title="Permalink to this headline">¶</a></h2>
+<p>The Clang CMake build system supports bootstrap (aka multi-stage) builds. At a
+high level a multi-stage build is a chain of builds that pass data from one
+stage into the next. The most common and simple version of this is a traditional
+bootstrap build.</p>
+<p>In a simple two-stage bootstrap build, we build clang using the system compiler,
+then use that just-built clang to build clang again. In CMake this simplest form
+of a bootstrap build can be configured with a single option,
+CLANG_ENABLE_BOOTSTRAP.</p>
+<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake -G Ninja -DCLANG_ENABLE_BOOTSTRAP<span class="o">=</span>On <path to source>
+<span class="gp">$</span> ninja stage2
+</pre></div>
+</div>
+<p>This command itself isnât terribly useful because it assumes default
+configurations for each stage. The next series of examples utilize CMake cache
+scripts to provide more complex options.</p>
+<p>By default, only a few CMake options will be passed between stages.
+The list, called _BOOTSTRAP_DEFAULT_PASSTHROUGH, is defined in clang/CMakeLists.txt.
+To force the passing of the variables between stages, use the -DCLANG_BOOTSTRAP_PASSTHROUGH
+CMake option, each variable separated by a â;â. As example:</p>
+<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake -G Ninja -DCLANG_ENABLE_BOOTSTRAP<span class="o">=</span>On -DCLANG_BOOTSTRAP_PASSTHROUGH<span class="o">=</span><span class="s2">"CMAKE_INSTALL_PREFIX;CMAKE_VERBOSE_MAKEFILE"</span> <path to source>
+<span class="gp">$</span> ninja stage2
+</pre></div>
+</div>
+<p>CMake options starting by <code class="docutils literal notranslate"><span class="pre">BOOTSTRAP_</span></code> will be passed only to the stage2 build.
+This gives the opportunity to use Clang specific build flags.
+For example, the following CMake call will enabled â-fno-addrsigâ only during
+the stage2 build for C and C++.</p>
+<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake <span class="o">[</span>..<span class="o">]</span> -DBOOTSTRAP_CMAKE_CXX_FLAGS<span class="o">=</span><span class="s1">'-fno-addrsig'</span> -DBOOTSTRAP_CMAKE_C_FLAGS<span class="o">=</span><span class="s1">'-fno-addrsig'</span> <span class="o">[</span>..<span class="o">]</span>
+</pre></div>
+</div>
+<p>The clang build system refers to builds as stages. A stage1 build is a standard
+build using the compiler installed on the host, and a stage2 build is built
+using the stage1 compiler. This nomenclature holds up to more stages too. In
+general a stage*n* build is built using the output from stage*n-1*.</p>
+</div>
+<div class="section" id="apple-clang-builds-a-more-complex-bootstrap">
+<h2><a class="toc-backref" href="#id3">Apple Clang Builds (A More Complex Bootstrap)</a><a class="headerlink" href="#apple-clang-builds-a-more-complex-bootstrap" title="Permalink to this headline">¶</a></h2>
+<p>Appleâs Clang builds are a slightly more complicated example of the simple
+bootstrapping scenario. Apple Clang is built using a 2-stage build.</p>
+<p>The stage1 compiler is a host-only compiler with some options set. The stage1
+compiler is a balance of optimization vs build time because it is a throwaway.
+The stage2 compiler is the fully optimized compiler intended to ship to users.</p>
+<p>Setting up these compilers requires a lot of options. To simplify the
+configuration the Apple Clang build settings are contained in CMake Cache files.
+You can build an Apple Clang compiler using the following commands:</p>
+<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake -G Ninja -C <path to clang>/cmake/caches/Apple-stage1.cmake <path to source>
+<span class="gp">$</span> ninja stage2-distribution
+</pre></div>
+</div>
+<p>This CMake invocation configures the stage1 host compiler, and sets
+CLANG_BOOTSTRAP_CMAKE_ARGS to pass the Apple-stage2.cmake cache script to the
+stage2 configuration step.</p>
+<p>When you build the stage2-distribution target it builds the minimal stage1
+compiler and required tools, then configures and builds the stage2 compiler
+based on the settings in Apple-stage2.cmake.</p>
+<p>This pattern of using cache scripts to set complex settings, and specifically to
+make later stage builds include cache scripts is common in our more advanced
+build configurations.</p>
+</div>
+<div class="section" id="multi-stage-pgo">
+<h2><a class="toc-backref" href="#id4">Multi-stage PGO</a><a class="headerlink" href="#multi-stage-pgo" title="Permalink to this headline">¶</a></h2>
+<p>Profile-Guided Optimizations (PGO) is a really great way to optimize the code
+clang generates. Our multi-stage PGO builds are a workflow for generating PGO
+profiles that can be used to optimize clang.</p>
+<p>At a high level, the way PGO works is that you build an instrumented compiler,
+then you run the instrumented compiler against sample source files. While the
+instrumented compiler runs it will output a bunch of files containing
+performance counters (.profraw files). After generating all the profraw files
+you use llvm-profdata to merge the files into a single profdata file that you
+can feed into the LLVM_PROFDATA_FILE option.</p>
+<p>Our PGO.cmake cache script automates that whole process. You can use it by
+running:</p>
+<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake -G Ninja -C <path_to_clang>/cmake/caches/PGO.cmake <<span class="nb">source</span> dir>
+<span class="gp">$</span> ninja stage2-instrumented-generate-profdata
+</pre></div>
+</div>
+<p>If you let that run for a few hours or so, it will place a profdata file in your
+build directory. This takes a really long time because it builds clang twice,
+and you <em>must</em> have compiler-rt in your build tree.</p>
+<p>This process uses any source files under the perf-training directory as training
+data as long as the source files are marked up with LIT-style RUN lines.</p>
+<p>After it finishes you can use âfind . -name clang.profdataâ to find it, but it
+should be at a path something like:</p>
+<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span class="go"><build dir>/tools/clang/stage2-instrumented-bins/utils/perf-training/clang.profdata</span>
+</pre></div>
+</div>
+<p>You can feed that file into the LLVM_PROFDATA_FILE option when you build your
+optimized compiler.</p>
+<p>The PGO came cache has a slightly different stage naming scheme than other
+multi-stage builds. It generates three stages; stage1, stage2-instrumented, and
+stage2. Both of the stage2 builds are built using the stage1 compiler.</p>
+<p>The PGO came cache generates the following additional targets:</p>
+<dl class="docutils">
+<dt><strong>stage2-instrumented</strong></dt>
+<dd>Builds a stage1 x86 compiler, runtime, and required tools (llvm-config,
+llvm-profdata) then uses that compiler to build an instrumented stage2 compiler.</dd>
+<dt><strong>stage2-instrumented-generate-profdata</strong></dt>
+<dd>Depends on âstage2-instrumentedâ and will use the instrumented compiler to
+generate profdata based on the training files in <clang>/utils/perf-training</dd>
+<dt><strong>stage2</strong></dt>
+<dd>Depends of âstage2-instrumented-generate-profdataâ and will use the stage1
+compiler with the stage2 profdata to build a PGO-optimized compiler.</dd>
+<dt><strong>stage2-check-llvm</strong></dt>
+<dd>Depends on stage2 and runs check-llvm using the stage2 compiler.</dd>
+<dt><strong>stage2-check-clang</strong></dt>
+<dd>Depends on stage2 and runs check-clang using the stage2 compiler.</dd>
+<dt><strong>stage2-check-all</strong></dt>
+<dd>Depends on stage2 and runs check-all using the stage2 compiler.</dd>
+<dt><strong>stage2-test-suite</strong></dt>
+<dd>Depends on stage2 and runs the test-suite using the stage3 compiler (requires
+in-tree test-suite).</dd>
+</dl>
+</div>
+<div class="section" id="stage-non-determinism">
+<h2><a class="toc-backref" href="#id5">3-Stage Non-Determinism</a><a class="headerlink" href="#stage-non-determinism" title="Permalink to this headline">¶</a></h2>
+<p>In the ancient lore of compilers non-determinism is like the multi-headed hydra.
+Whenever its head pops up, terror and chaos ensue.</p>
+<p>Historically one of the tests to verify that a compiler was deterministic would
+be a three stage build. The idea of a three stage build is you take your sources
+and build a compiler (stage1), then use that compiler to rebuild the sources
+(stage2), then you use that compiler to rebuild the sources a third time
+(stage3) with an identical configuration to the stage2 build. At the end of
+this, you have a stage2 and stage3 compiler that should be bit-for-bit
+identical.</p>
+<p>You can perform one of these 3-stage builds with LLVM & clang using the
+following commands:</p>
+<div class="highlight-console notranslate"><div class="highlight"><pre><span></span><span class="gp">$</span> cmake -G Ninja -C <path_to_clang>/cmake/caches/3-stage.cmake <<span class="nb">source</span> dir>
+<span class="gp">$</span> ninja stage3
+</pre></div>
+</div>
+<p>After the build you can compare the stage2 & stage3 compilers. We have a bot
+setup <a class="reference external" href="http://lab.llvm.org:8011/builders/clang-3stage-ubuntu">here</a> that runs
+this build and compare configuration.</p>
+</div>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
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--- www-releases/trunk/9.0.0/docs/AliasAnalysis.html (added)
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+ <div class="body" role="main">
+
+ <div class="section" id="llvm-alias-analysis-infrastructure">
+<h1>LLVM Alias Analysis Infrastructure<a class="headerlink" href="#llvm-alias-analysis-infrastructure" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#introduction" id="id1">Introduction</a></li>
+<li><a class="reference internal" href="#aliasanalysis-class-overview" id="id2"><code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> Class Overview</a><ul>
+<li><a class="reference internal" href="#representation-of-pointers" id="id3">Representation of Pointers</a></li>
+<li><a class="reference internal" href="#the-alias-method" id="id4">The <code class="docutils literal notranslate"><span class="pre">alias</span></code> method</a><ul>
+<li><a class="reference internal" href="#must-may-and-no-alias-responses" id="id5">Must, May, and No Alias Responses</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#the-getmodrefinfo-methods" id="id6">The <code class="docutils literal notranslate"><span class="pre">getModRefInfo</span></code> methods</a></li>
+<li><a class="reference internal" href="#other-useful-aliasanalysis-methods" id="id7">Other useful <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> methods</a><ul>
+<li><a class="reference internal" href="#the-pointstoconstantmemory-method" id="id8">The <code class="docutils literal notranslate"><span class="pre">pointsToConstantMemory</span></code> method</a></li>
+<li><a class="reference internal" href="#the-doesnotaccessmemory-and-onlyreadsmemory-methods" id="id9">The <code class="docutils literal notranslate"><span class="pre">doesNotAccessMemory</span></code> and <code class="docutils literal notranslate"><span class="pre">onlyReadsMemory</span></code> methods</a></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><a class="reference internal" href="#writing-a-new-aliasanalysis-implementation" id="id10">Writing a new <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> Implementation</a><ul>
+<li><a class="reference internal" href="#different-pass-styles" id="id11">Different Pass styles</a></li>
+<li><a class="reference internal" href="#required-initialization-calls" id="id12">Required initialization calls</a></li>
+<li><a class="reference internal" href="#required-methods-to-override" id="id13">Required methods to override</a></li>
+<li><a class="reference internal" href="#interfaces-which-may-be-specified" id="id14">Interfaces which may be specified</a></li>
+<li><a class="reference internal" href="#aliasanalysis-chaining-behavior" id="id15"><code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> chaining behavior</a></li>
+<li><a class="reference internal" href="#updating-analysis-results-for-transformations" id="id16">Updating analysis results for transformations</a><ul>
+<li><a class="reference internal" href="#the-deletevalue-method" id="id17">The <code class="docutils literal notranslate"><span class="pre">deleteValue</span></code> method</a></li>
+<li><a class="reference internal" href="#the-copyvalue-method" id="id18">The <code class="docutils literal notranslate"><span class="pre">copyValue</span></code> method</a></li>
+<li><a class="reference internal" href="#the-replacewithnewvalue-method" id="id19">The <code class="docutils literal notranslate"><span class="pre">replaceWithNewValue</span></code> method</a></li>
+<li><a class="reference internal" href="#the-addescapinguse-method" id="id20">The <code class="docutils literal notranslate"><span class="pre">addEscapingUse</span></code> method</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#efficiency-issues" id="id21">Efficiency Issues</a></li>
+<li><a class="reference internal" href="#limitations" id="id22">Limitations</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#using-alias-analysis-results" id="id23">Using alias analysis results</a><ul>
+<li><a class="reference internal" href="#using-the-memorydependenceanalysis-pass" id="id24">Using the <code class="docutils literal notranslate"><span class="pre">MemoryDependenceAnalysis</span></code> Pass</a></li>
+<li><a class="reference internal" href="#using-the-aliassettracker-class" id="id25">Using the <code class="docutils literal notranslate"><span class="pre">AliasSetTracker</span></code> class</a><ul>
+<li><a class="reference internal" href="#the-aliassettracker-implementation" id="id26">The AliasSetTracker implementation</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#using-the-aliasanalysis-interface-directly" id="id27">Using the <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> interface directly</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#existing-alias-analysis-implementations-and-clients" id="id28">Existing alias analysis implementations and clients</a><ul>
+<li><a class="reference internal" href="#available-aliasanalysis-implementations" id="id29">Available <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> implementations</a><ul>
+<li><a class="reference internal" href="#the-no-aa-pass" id="id30">The <code class="docutils literal notranslate"><span class="pre">-no-aa</span></code> pass</a></li>
+<li><a class="reference internal" href="#the-basicaa-pass" id="id31">The <code class="docutils literal notranslate"><span class="pre">-basicaa</span></code> pass</a></li>
+<li><a class="reference internal" href="#the-globalsmodref-aa-pass" id="id32">The <code class="docutils literal notranslate"><span class="pre">-globalsmodref-aa</span></code> pass</a></li>
+<li><a class="reference internal" href="#the-steens-aa-pass" id="id33">The <code class="docutils literal notranslate"><span class="pre">-steens-aa</span></code> pass</a></li>
+<li><a class="reference internal" href="#the-ds-aa-pass" id="id34">The <code class="docutils literal notranslate"><span class="pre">-ds-aa</span></code> pass</a></li>
+<li><a class="reference internal" href="#the-scev-aa-pass" id="id35">The <code class="docutils literal notranslate"><span class="pre">-scev-aa</span></code> pass</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#alias-analysis-driven-transformations" id="id36">Alias analysis driven transformations</a><ul>
+<li><a class="reference internal" href="#the-adce-pass" id="id37">The <code class="docutils literal notranslate"><span class="pre">-adce</span></code> pass</a></li>
+<li><a class="reference internal" href="#the-licm-pass" id="id38">The <code class="docutils literal notranslate"><span class="pre">-licm</span></code> pass</a></li>
+<li><a class="reference internal" href="#the-argpromotion-pass" id="id39">The <code class="docutils literal notranslate"><span class="pre">-argpromotion</span></code> pass</a></li>
+<li><a class="reference internal" href="#the-gvn-memcpyopt-and-dse-passes" id="id40">The <code class="docutils literal notranslate"><span class="pre">-gvn</span></code>, <code class="docutils literal notranslate"><span class="pre">-memcpyopt</span></code>, and <code class="docutils literal notranslate"><span class="pre">-dse</span></code> passes</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#clients-for-debugging-and-evaluation-of-implementations" id="id41">Clients for debugging and evaluation of implementations</a><ul>
+<li><a class="reference internal" href="#the-print-alias-sets-pass" id="id42">The <code class="docutils literal notranslate"><span class="pre">-print-alias-sets</span></code> pass</a></li>
+<li><a class="reference internal" href="#the-aa-eval-pass" id="id43">The <code class="docutils literal notranslate"><span class="pre">-aa-eval</span></code> pass</a></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><a class="reference internal" href="#memory-dependence-analysis" id="id44">Memory Dependence Analysis</a></li>
+</ul>
+</div>
+<div class="section" id="introduction">
+<h2><a class="toc-backref" href="#id1">Introduction</a><a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
+<p>Alias Analysis (aka Pointer Analysis) is a class of techniques which attempt to
+determine whether or not two pointers ever can point to the same object in
+memory. There are many different algorithms for alias analysis and many
+different ways of classifying them: flow-sensitive vs. flow-insensitive,
+context-sensitive vs. context-insensitive, field-sensitive
+vs. field-insensitive, unification-based vs. subset-based, etc. Traditionally,
+alias analyses respond to a query with a <a class="reference internal" href="#must-may-or-no">Must, May, or No</a> alias response,
+indicating that two pointers always point to the same object, might point to the
+same object, or are known to never point to the same object.</p>
+<p>The LLVM <a class="reference external" href="http://llvm.org/doxygen/classllvm_1_1AliasAnalysis.html">AliasAnalysis</a> class is the
+primary interface used by clients and implementations of alias analyses in the
+LLVM system. This class is the common interface between clients of alias
+analysis information and the implementations providing it, and is designed to
+support a wide range of implementations and clients (but currently all clients
+are assumed to be flow-insensitive). In addition to simple alias analysis
+information, this class exposes Mod/Ref information from those implementations
+which can provide it, allowing for powerful analyses and transformations to work
+well together.</p>
+<p>This document contains information necessary to successfully implement this
+interface, use it, and to test both sides. It also explains some of the finer
+points about what exactly results mean.</p>
+</div>
+<div class="section" id="aliasanalysis-class-overview">
+<h2><a class="toc-backref" href="#id2"><code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> Class Overview</a><a class="headerlink" href="#aliasanalysis-class-overview" title="Permalink to this headline">¶</a></h2>
+<p>The <a class="reference external" href="http://llvm.org/doxygen/classllvm_1_1AliasAnalysis.html">AliasAnalysis</a>
+class defines the interface that the various alias analysis implementations
+should support. This class exports two important enums: <code class="docutils literal notranslate"><span class="pre">AliasResult</span></code> and
+<code class="docutils literal notranslate"><span class="pre">ModRefResult</span></code> which represent the result of an alias query or a mod/ref
+query, respectively.</p>
+<p>The <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> interface exposes information about memory, represented in
+several different ways. In particular, memory objects are represented as a
+starting address and size, and function calls are represented as the actual
+<code class="docutils literal notranslate"><span class="pre">call</span></code> or <code class="docutils literal notranslate"><span class="pre">invoke</span></code> instructions that performs the call. The
+<code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> interface also exposes some helper methods which allow you to
+get mod/ref information for arbitrary instructions.</p>
+<p>All <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> interfaces require that in queries involving multiple
+values, values which are not <a class="reference internal" href="LangRef.html#constants"><span class="std std-ref">constants</span></a> are all
+defined within the same function.</p>
+<div class="section" id="representation-of-pointers">
+<h3><a class="toc-backref" href="#id3">Representation of Pointers</a><a class="headerlink" href="#representation-of-pointers" title="Permalink to this headline">¶</a></h3>
+<p>Most importantly, the <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> class provides several methods which are
+used to query whether or not two memory objects alias, whether function calls
+can modify or read a memory object, etc. For all of these queries, memory
+objects are represented as a pair of their starting address (a symbolic LLVM
+<code class="docutils literal notranslate"><span class="pre">Value*</span></code>) and a static size.</p>
+<p>Representing memory objects as a starting address and a size is critically
+important for correct Alias Analyses. For example, consider this (silly, but
+possible) C code:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="kt">int</span> <span class="n">i</span><span class="p">;</span>
+<span class="kt">char</span> <span class="n">C</span><span class="p">[</span><span class="mi">2</span><span class="p">];</span>
+<span class="kt">char</span> <span class="n">A</span><span class="p">[</span><span class="mi">10</span><span class="p">];</span>
+<span class="cm">/* ... */</span>
+<span class="k">for</span> <span class="p">(</span><span class="n">i</span> <span class="o">=</span> <span class="mi">0</span><span class="p">;</span> <span class="n">i</span> <span class="o">!=</span> <span class="mi">10</span><span class="p">;</span> <span class="o">++</span><span class="n">i</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">C</span><span class="p">[</span><span class="mi">0</span><span class="p">]</span> <span class="o">=</span> <span class="n">A</span><span class="p">[</span><span class="n">i</span><span class="p">];</span> <span class="cm">/* One byte store */</span>
+ <span class="n">C</span><span class="p">[</span><span class="mi">1</span><span class="p">]</span> <span class="o">=</span> <span class="n">A</span><span class="p">[</span><span class="mi">9</span><span class="o">-</span><span class="n">i</span><span class="p">];</span> <span class="cm">/* One byte store */</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+<p>In this case, the <code class="docutils literal notranslate"><span class="pre">basicaa</span></code> pass will disambiguate the stores to <code class="docutils literal notranslate"><span class="pre">C[0]</span></code> and
+<code class="docutils literal notranslate"><span class="pre">C[1]</span></code> because they are accesses to two distinct locations one byte apart, and
+the accesses are each one byte. In this case, the Loop Invariant Code Motion
+(LICM) pass can use store motion to remove the stores from the loop. In
+constrast, the following code:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="kt">int</span> <span class="n">i</span><span class="p">;</span>
+<span class="kt">char</span> <span class="n">C</span><span class="p">[</span><span class="mi">2</span><span class="p">];</span>
+<span class="kt">char</span> <span class="n">A</span><span class="p">[</span><span class="mi">10</span><span class="p">];</span>
+<span class="cm">/* ... */</span>
+<span class="k">for</span> <span class="p">(</span><span class="n">i</span> <span class="o">=</span> <span class="mi">0</span><span class="p">;</span> <span class="n">i</span> <span class="o">!=</span> <span class="mi">10</span><span class="p">;</span> <span class="o">++</span><span class="n">i</span><span class="p">)</span> <span class="p">{</span>
+ <span class="p">((</span><span class="kt">short</span><span class="o">*</span><span class="p">)</span><span class="n">C</span><span class="p">)[</span><span class="mi">0</span><span class="p">]</span> <span class="o">=</span> <span class="n">A</span><span class="p">[</span><span class="n">i</span><span class="p">];</span> <span class="cm">/* Two byte store! */</span>
+ <span class="n">C</span><span class="p">[</span><span class="mi">1</span><span class="p">]</span> <span class="o">=</span> <span class="n">A</span><span class="p">[</span><span class="mi">9</span><span class="o">-</span><span class="n">i</span><span class="p">];</span> <span class="cm">/* One byte store */</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+<p>In this case, the two stores to C do alias each other, because the access to the
+<code class="docutils literal notranslate"><span class="pre">&C[0]</span></code> element is a two byte access. If size information wasnât available in
+the query, even the first case would have to conservatively assume that the
+accesses alias.</p>
+</div>
+<div class="section" id="the-alias-method">
+<span id="alias"></span><h3><a class="toc-backref" href="#id4">The <code class="docutils literal notranslate"><span class="pre">alias</span></code> method</a><a class="headerlink" href="#the-alias-method" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal notranslate"><span class="pre">alias</span></code> method is the primary interface used to determine whether or not
+two memory objects alias each other. It takes two memory objects as input and
+returns MustAlias, PartialAlias, MayAlias, or NoAlias as appropriate.</p>
+<p>Like all <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> interfaces, the <code class="docutils literal notranslate"><span class="pre">alias</span></code> method requires that either
+the two pointer values be defined within the same function, or at least one of
+the values is a <a class="reference internal" href="LangRef.html#constants"><span class="std std-ref">constant</span></a>.</p>
+<div class="section" id="must-may-and-no-alias-responses">
+<span id="must-may-or-no"></span><h4><a class="toc-backref" href="#id5">Must, May, and No Alias Responses</a><a class="headerlink" href="#must-may-and-no-alias-responses" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal notranslate"><span class="pre">NoAlias</span></code> response may be used when there is never an immediate dependence
+between any memory reference <em>based</em> on one pointer and any memory reference
+<em>based</em> the other. The most obvious example is when the two pointers point to
+non-overlapping memory ranges. Another is when the two pointers are only ever
+used for reading memory. Another is when the memory is freed and reallocated
+between accesses through one pointer and accesses through the other â in this
+case, there is a dependence, but itâs mediated by the free and reallocation.</p>
+<p>As an exception to this is with the <a class="reference internal" href="LangRef.html#noalias"><span class="std std-ref">noalias</span></a> keyword;
+the âirrelevantâ dependencies are ignored.</p>
+<p>The <code class="docutils literal notranslate"><span class="pre">MayAlias</span></code> response is used whenever the two pointers might refer to the
+same object.</p>
+<p>The <code class="docutils literal notranslate"><span class="pre">PartialAlias</span></code> response is used when the two memory objects are known to
+be overlapping in some way, regardless whether they start at the same address
+or not.</p>
+<p>The <code class="docutils literal notranslate"><span class="pre">MustAlias</span></code> response may only be returned if the two memory objects are
+guaranteed to always start at exactly the same location. A <code class="docutils literal notranslate"><span class="pre">MustAlias</span></code>
+response does not imply that the pointers compare equal.</p>
+</div>
+</div>
+<div class="section" id="the-getmodrefinfo-methods">
+<h3><a class="toc-backref" href="#id6">The <code class="docutils literal notranslate"><span class="pre">getModRefInfo</span></code> methods</a><a class="headerlink" href="#the-getmodrefinfo-methods" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal notranslate"><span class="pre">getModRefInfo</span></code> methods return information about whether the execution of
+an instruction can read or modify a memory location. Mod/Ref information is
+always conservative: if an instruction <strong>might</strong> read or write a location,
+<code class="docutils literal notranslate"><span class="pre">ModRef</span></code> is returned.</p>
+<p>The <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> class also provides a <code class="docutils literal notranslate"><span class="pre">getModRefInfo</span></code> method for testing
+dependencies between function calls. This method takes two call sites (<code class="docutils literal notranslate"><span class="pre">CS1</span></code>
+& <code class="docutils literal notranslate"><span class="pre">CS2</span></code>), returns <code class="docutils literal notranslate"><span class="pre">NoModRef</span></code> if neither call writes to memory read or
+written by the other, <code class="docutils literal notranslate"><span class="pre">Ref</span></code> if <code class="docutils literal notranslate"><span class="pre">CS1</span></code> reads memory written by <code class="docutils literal notranslate"><span class="pre">CS2</span></code>,
+<code class="docutils literal notranslate"><span class="pre">Mod</span></code> if <code class="docutils literal notranslate"><span class="pre">CS1</span></code> writes to memory read or written by <code class="docutils literal notranslate"><span class="pre">CS2</span></code>, or <code class="docutils literal notranslate"><span class="pre">ModRef</span></code> if
+<code class="docutils literal notranslate"><span class="pre">CS1</span></code> might read or write memory written to by <code class="docutils literal notranslate"><span class="pre">CS2</span></code>. Note that this
+relation is not commutative.</p>
+</div>
+<div class="section" id="other-useful-aliasanalysis-methods">
+<h3><a class="toc-backref" href="#id7">Other useful <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> methods</a><a class="headerlink" href="#other-useful-aliasanalysis-methods" title="Permalink to this headline">¶</a></h3>
+<p>Several other tidbits of information are often collected by various alias
+analysis implementations and can be put to good use by various clients.</p>
+<div class="section" id="the-pointstoconstantmemory-method">
+<h4><a class="toc-backref" href="#id8">The <code class="docutils literal notranslate"><span class="pre">pointsToConstantMemory</span></code> method</a><a class="headerlink" href="#the-pointstoconstantmemory-method" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal notranslate"><span class="pre">pointsToConstantMemory</span></code> method returns true if and only if the analysis
+can prove that the pointer only points to unchanging memory locations
+(functions, constant global variables, and the null pointer). This information
+can be used to refine mod/ref information: it is impossible for an unchanging
+memory location to be modified.</p>
+</div>
+<div class="section" id="the-doesnotaccessmemory-and-onlyreadsmemory-methods">
+<span id="never-access-memory-or-only-read-memory"></span><h4><a class="toc-backref" href="#id9">The <code class="docutils literal notranslate"><span class="pre">doesNotAccessMemory</span></code> and <code class="docutils literal notranslate"><span class="pre">onlyReadsMemory</span></code> methods</a><a class="headerlink" href="#the-doesnotaccessmemory-and-onlyreadsmemory-methods" title="Permalink to this headline">¶</a></h4>
+<p>These methods are used to provide very simple mod/ref information for function
+calls. The <code class="docutils literal notranslate"><span class="pre">doesNotAccessMemory</span></code> method returns true for a function if the
+analysis can prove that the function never reads or writes to memory, or if the
+function only reads from constant memory. Functions with this property are
+side-effect free and only depend on their input arguments, allowing them to be
+eliminated if they form common subexpressions or be hoisted out of loops. Many
+common functions behave this way (e.g., <code class="docutils literal notranslate"><span class="pre">sin</span></code> and <code class="docutils literal notranslate"><span class="pre">cos</span></code>) but many others do
+not (e.g., <code class="docutils literal notranslate"><span class="pre">acos</span></code>, which modifies the <code class="docutils literal notranslate"><span class="pre">errno</span></code> variable).</p>
+<p>The <code class="docutils literal notranslate"><span class="pre">onlyReadsMemory</span></code> method returns true for a function if analysis can prove
+that (at most) the function only reads from non-volatile memory. Functions with
+this property are side-effect free, only depending on their input arguments and
+the state of memory when they are called. This property allows calls to these
+functions to be eliminated and moved around, as long as there is no store
+instruction that changes the contents of memory. Note that all functions that
+satisfy the <code class="docutils literal notranslate"><span class="pre">doesNotAccessMemory</span></code> method also satisfy <code class="docutils literal notranslate"><span class="pre">onlyReadsMemory</span></code>.</p>
+</div>
+</div>
+</div>
+<div class="section" id="writing-a-new-aliasanalysis-implementation">
+<h2><a class="toc-backref" href="#id10">Writing a new <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> Implementation</a><a class="headerlink" href="#writing-a-new-aliasanalysis-implementation" title="Permalink to this headline">¶</a></h2>
+<p>Writing a new alias analysis implementation for LLVM is quite straight-forward.
+There are already several implementations that you can use for examples, and the
+following information should help fill in any details. For a examples, take a
+look at the <a class="reference internal" href="#various-alias-analysis-implementations">various alias analysis implementations</a> included with LLVM.</p>
+<div class="section" id="different-pass-styles">
+<h3><a class="toc-backref" href="#id11">Different Pass styles</a><a class="headerlink" href="#different-pass-styles" title="Permalink to this headline">¶</a></h3>
+<p>The first step to determining what type of <a class="reference internal" href="WritingAnLLVMPass.html"><span class="doc">LLVM pass</span></a>
+you need to use for your Alias Analysis. As is the case with most other
+analyses and transformations, the answer should be fairly obvious from what type
+of problem you are trying to solve:</p>
+<ol class="arabic simple">
+<li>If you require interprocedural analysis, it should be a <code class="docutils literal notranslate"><span class="pre">Pass</span></code>.</li>
+<li>If you are a function-local analysis, subclass <code class="docutils literal notranslate"><span class="pre">FunctionPass</span></code>.</li>
+<li>If you donât need to look at the program at all, subclass <code class="docutils literal notranslate"><span class="pre">ImmutablePass</span></code>.</li>
+</ol>
+<p>In addition to the pass that you subclass, you should also inherit from the
+<code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> interface, of course, and use the <code class="docutils literal notranslate"><span class="pre">RegisterAnalysisGroup</span></code>
+template to register as an implementation of <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code>.</p>
+</div>
+<div class="section" id="required-initialization-calls">
+<h3><a class="toc-backref" href="#id12">Required initialization calls</a><a class="headerlink" href="#required-initialization-calls" title="Permalink to this headline">¶</a></h3>
+<p>Your subclass of <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> is required to invoke two methods on the
+<code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> base class: <code class="docutils literal notranslate"><span class="pre">getAnalysisUsage</span></code> and
+<code class="docutils literal notranslate"><span class="pre">InitializeAliasAnalysis</span></code>. In particular, your implementation of
+<code class="docutils literal notranslate"><span class="pre">getAnalysisUsage</span></code> should explicitly call into the
+<code class="docutils literal notranslate"><span class="pre">AliasAnalysis::getAnalysisUsage</span></code> method in addition to doing any declaring
+any pass dependencies your pass has. Thus you should have something like this:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="kt">void</span> <span class="nf">getAnalysisUsage</span><span class="p">(</span><span class="n">AnalysisUsage</span> <span class="o">&</span><span class="n">AU</span><span class="p">)</span> <span class="k">const</span> <span class="p">{</span>
+ <span class="n">AliasAnalysis</span><span class="o">::</span><span class="n">getAnalysisUsage</span><span class="p">(</span><span class="n">AU</span><span class="p">);</span>
+ <span class="c1">// declare your dependencies here.</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+<p>Additionally, your must invoke the <code class="docutils literal notranslate"><span class="pre">InitializeAliasAnalysis</span></code> method from your
+analysis run method (<code class="docutils literal notranslate"><span class="pre">run</span></code> for a <code class="docutils literal notranslate"><span class="pre">Pass</span></code>, <code class="docutils literal notranslate"><span class="pre">runOnFunction</span></code> for a
+<code class="docutils literal notranslate"><span class="pre">FunctionPass</span></code>, or <code class="docutils literal notranslate"><span class="pre">InitializePass</span></code> for an <code class="docutils literal notranslate"><span class="pre">ImmutablePass</span></code>). For example
+(as part of a <code class="docutils literal notranslate"><span class="pre">Pass</span></code>):</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="kt">bool</span> <span class="nf">run</span><span class="p">(</span><span class="n">Module</span> <span class="o">&</span><span class="n">M</span><span class="p">)</span> <span class="p">{</span>
+ <span class="n">InitializeAliasAnalysis</span><span class="p">(</span><span class="k">this</span><span class="p">);</span>
+ <span class="c1">// Perform analysis here...</span>
+ <span class="k">return</span> <span class="nb">false</span><span class="p">;</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="required-methods-to-override">
+<h3><a class="toc-backref" href="#id13">Required methods to override</a><a class="headerlink" href="#required-methods-to-override" title="Permalink to this headline">¶</a></h3>
+<p>You must override the <code class="docutils literal notranslate"><span class="pre">getAdjustedAnalysisPointer</span></code> method on all subclasses
+of <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code>. An example implementation of this method would look like:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="kt">void</span> <span class="o">*</span><span class="nf">getAdjustedAnalysisPointer</span><span class="p">(</span><span class="k">const</span> <span class="kt">void</span><span class="o">*</span> <span class="n">ID</span><span class="p">)</span> <span class="k">override</span> <span class="p">{</span>
+ <span class="k">if</span> <span class="p">(</span><span class="n">ID</span> <span class="o">==</span> <span class="o">&</span><span class="n">AliasAnalysis</span><span class="o">::</span><span class="n">ID</span><span class="p">)</span>
+ <span class="k">return</span> <span class="p">(</span><span class="n">AliasAnalysis</span><span class="o">*</span><span class="p">)</span><span class="k">this</span><span class="p">;</span>
+ <span class="k">return</span> <span class="k">this</span><span class="p">;</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="interfaces-which-may-be-specified">
+<h3><a class="toc-backref" href="#id14">Interfaces which may be specified</a><a class="headerlink" href="#interfaces-which-may-be-specified" title="Permalink to this headline">¶</a></h3>
+<p>All of the <a class="reference external" href="http://llvm.org/doxygen/classllvm_1_1AliasAnalysis.html">AliasAnalysis</a> virtual methods
+default to providing <a class="reference internal" href="#aliasanalysis-chaining"><span class="std std-ref">chaining</span></a> to another alias
+analysis implementation, which ends up returning conservatively correct
+information (returning âMayâ Alias and âMod/Refâ for alias and mod/ref queries
+respectively). Depending on the capabilities of the analysis you are
+implementing, you just override the interfaces you can improve.</p>
+</div>
+<div class="section" id="aliasanalysis-chaining-behavior">
+<span id="aliasanalysis-chaining"></span><h3><a class="toc-backref" href="#id15"><code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> chaining behavior</a><a class="headerlink" href="#aliasanalysis-chaining-behavior" title="Permalink to this headline">¶</a></h3>
+<p>With only one special exception (the <a class="reference internal" href="#aliasanalysis-no-aa"><span class="std std-ref">-no-aa</span></a> pass)
+every alias analysis pass chains to another alias analysis implementation (for
+example, the user can specify â<code class="docutils literal notranslate"><span class="pre">-basicaa</span> <span class="pre">-ds-aa</span> <span class="pre">-licm</span></code>â to get the maximum
+benefit from both alias analyses). The alias analysis class automatically
+takes care of most of this for methods that you donât override. For methods
+that you do override, in code paths that return a conservative MayAlias or
+Mod/Ref result, simply return whatever the superclass computes. For example:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="n">AliasResult</span> <span class="nf">alias</span><span class="p">(</span><span class="k">const</span> <span class="n">Value</span> <span class="o">*</span><span class="n">V1</span><span class="p">,</span> <span class="kt">unsigned</span> <span class="n">V1Size</span><span class="p">,</span>
+ <span class="k">const</span> <span class="n">Value</span> <span class="o">*</span><span class="n">V2</span><span class="p">,</span> <span class="kt">unsigned</span> <span class="n">V2Size</span><span class="p">)</span> <span class="p">{</span>
+ <span class="k">if</span> <span class="p">(...)</span>
+ <span class="k">return</span> <span class="n">NoAlias</span><span class="p">;</span>
+ <span class="p">...</span>
+
+ <span class="c1">// Couldn't determine a must or no-alias result.</span>
+ <span class="k">return</span> <span class="n">AliasAnalysis</span><span class="o">::</span><span class="n">alias</span><span class="p">(</span><span class="n">V1</span><span class="p">,</span> <span class="n">V1Size</span><span class="p">,</span> <span class="n">V2</span><span class="p">,</span> <span class="n">V2Size</span><span class="p">);</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+<p>In addition to analysis queries, you must make sure to unconditionally pass LLVM
+<a class="reference internal" href="#update-notification">update notification</a> methods to the superclass as well if you override them,
+which allows all alias analyses in a change to be updated.</p>
+</div>
+<div class="section" id="updating-analysis-results-for-transformations">
+<span id="update-notification"></span><h3><a class="toc-backref" href="#id16">Updating analysis results for transformations</a><a class="headerlink" href="#updating-analysis-results-for-transformations" title="Permalink to this headline">¶</a></h3>
+<p>Alias analysis information is initially computed for a static snapshot of the
+program, but clients will use this information to make transformations to the
+code. All but the most trivial forms of alias analysis will need to have their
+analysis results updated to reflect the changes made by these transformations.</p>
+<p>The <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> interface exposes four methods which are used to
+communicate program changes from the clients to the analysis implementations.
+Various alias analysis implementations should use these methods to ensure that
+their internal data structures are kept up-to-date as the program changes (for
+example, when an instruction is deleted), and clients of alias analysis must be
+sure to call these interfaces appropriately.</p>
+<div class="section" id="the-deletevalue-method">
+<h4><a class="toc-backref" href="#id17">The <code class="docutils literal notranslate"><span class="pre">deleteValue</span></code> method</a><a class="headerlink" href="#the-deletevalue-method" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal notranslate"><span class="pre">deleteValue</span></code> method is called by transformations when they remove an
+instruction or any other value from the program (including values that do not
+use pointers). Typically alias analyses keep data structures that have entries
+for each value in the program. When this method is called, they should remove
+any entries for the specified value, if they exist.</p>
+</div>
+<div class="section" id="the-copyvalue-method">
+<h4><a class="toc-backref" href="#id18">The <code class="docutils literal notranslate"><span class="pre">copyValue</span></code> method</a><a class="headerlink" href="#the-copyvalue-method" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal notranslate"><span class="pre">copyValue</span></code> method is used when a new value is introduced into the
+program. There is no way to introduce a value into the program that did not
+exist before (this doesnât make sense for a safe compiler transformation), so
+this is the only way to introduce a new value. This method indicates that the
+new value has exactly the same properties as the value being copied.</p>
+</div>
+<div class="section" id="the-replacewithnewvalue-method">
+<h4><a class="toc-backref" href="#id19">The <code class="docutils literal notranslate"><span class="pre">replaceWithNewValue</span></code> method</a><a class="headerlink" href="#the-replacewithnewvalue-method" title="Permalink to this headline">¶</a></h4>
+<p>This method is a simple helper method that is provided to make clients easier to
+use. It is implemented by copying the old analysis information to the new
+value, then deleting the old value. This method cannot be overridden by alias
+analysis implementations.</p>
+</div>
+<div class="section" id="the-addescapinguse-method">
+<h4><a class="toc-backref" href="#id20">The <code class="docutils literal notranslate"><span class="pre">addEscapingUse</span></code> method</a><a class="headerlink" href="#the-addescapinguse-method" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal notranslate"><span class="pre">addEscapingUse</span></code> method is used when the uses of a pointer value have
+changed in ways that may invalidate precomputed analysis information.
+Implementations may either use this callback to provide conservative responses
+for points whose uses have change since analysis time, or may recompute some or
+all of their internal state to continue providing accurate responses.</p>
+<p>In general, any new use of a pointer value is considered an escaping use, and
+must be reported through this callback, <em>except</em> for the uses below:</p>
+<ul class="simple">
+<li>A <code class="docutils literal notranslate"><span class="pre">bitcast</span></code> or <code class="docutils literal notranslate"><span class="pre">getelementptr</span></code> of the pointer</li>
+<li>A <code class="docutils literal notranslate"><span class="pre">store</span></code> through the pointer (but not a <code class="docutils literal notranslate"><span class="pre">store</span></code> <em>of</em> the pointer)</li>
+<li>A <code class="docutils literal notranslate"><span class="pre">load</span></code> through the pointer</li>
+</ul>
+</div>
+</div>
+<div class="section" id="efficiency-issues">
+<h3><a class="toc-backref" href="#id21">Efficiency Issues</a><a class="headerlink" href="#efficiency-issues" title="Permalink to this headline">¶</a></h3>
+<p>From the LLVM perspective, the only thing you need to do to provide an efficient
+alias analysis is to make sure that alias analysis <strong>queries</strong> are serviced
+quickly. The actual calculation of the alias analysis results (the ârunâ
+method) is only performed once, but many (perhaps duplicate) queries may be
+performed. Because of this, try to move as much computation to the run method
+as possible (within reason).</p>
+</div>
+<div class="section" id="limitations">
+<h3><a class="toc-backref" href="#id22">Limitations</a><a class="headerlink" href="#limitations" title="Permalink to this headline">¶</a></h3>
+<p>The AliasAnalysis infrastructure has several limitations which make writing a
+new <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> implementation difficult.</p>
+<p>There is no way to override the default alias analysis. It would be very useful
+to be able to do something like â<code class="docutils literal notranslate"><span class="pre">opt</span> <span class="pre">-my-aa</span> <span class="pre">-O2</span></code>â and have it use <code class="docutils literal notranslate"><span class="pre">-my-aa</span></code>
+for all passes which need AliasAnalysis, but there is currently no support for
+that, short of changing the source code and recompiling. Similarly, there is
+also no way of setting a chain of analyses as the default.</p>
+<p>There is no way for transform passes to declare that they preserve
+<code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> implementations. The <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> interface includes
+<code class="docutils literal notranslate"><span class="pre">deleteValue</span></code> and <code class="docutils literal notranslate"><span class="pre">copyValue</span></code> methods which are intended to allow a pass to
+keep an AliasAnalysis consistent, however thereâs no way for a pass to declare
+in its <code class="docutils literal notranslate"><span class="pre">getAnalysisUsage</span></code> that it does so. Some passes attempt to use
+<code class="docutils literal notranslate"><span class="pre">AU.addPreserved<AliasAnalysis></span></code>, however this doesnât actually have any
+effect.</p>
+<p>Similarly, the <code class="docutils literal notranslate"><span class="pre">opt</span> <span class="pre">-p</span></code> option introduces <code class="docutils literal notranslate"><span class="pre">ModulePass</span></code> passes between each
+pass, which prevents the use of <code class="docutils literal notranslate"><span class="pre">FunctionPass</span></code> alias analysis passes.</p>
+<p>The <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> API does have functions for notifying implementations when
+values are deleted or copied, however these arenât sufficient. There are many
+other ways that LLVM IR can be modified which could be relevant to
+<code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> implementations which can not be expressed.</p>
+<p>The <code class="docutils literal notranslate"><span class="pre">AliasAnalysisDebugger</span></code> utility seems to suggest that <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code>
+implementations can expect that they will be informed of any relevant <code class="docutils literal notranslate"><span class="pre">Value</span></code>
+before it appears in an alias query. However, popular clients such as <code class="docutils literal notranslate"><span class="pre">GVN</span></code>
+donât support this, and are known to trigger errors when run with the
+<code class="docutils literal notranslate"><span class="pre">AliasAnalysisDebugger</span></code>.</p>
+<p>The <code class="docutils literal notranslate"><span class="pre">AliasSetTracker</span></code> class (which is used by <code class="docutils literal notranslate"><span class="pre">LICM</span></code>) makes a
+non-deterministic number of alias queries. This can cause debugging techniques
+involving pausing execution after a predetermined number of queries to be
+unreliable.</p>
+<p>Many alias queries can be reformulated in terms of other alias queries. When
+multiple <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> queries are chained together, it would make sense to
+start those queries from the beginning of the chain, with care taken to avoid
+infinite looping, however currently an implementation which wants to do this can
+only start such queries from itself.</p>
+</div>
+</div>
+<div class="section" id="using-alias-analysis-results">
+<h2><a class="toc-backref" href="#id23">Using alias analysis results</a><a class="headerlink" href="#using-alias-analysis-results" title="Permalink to this headline">¶</a></h2>
+<p>There are several different ways to use alias analysis results. In order of
+preference, these are:</p>
+<div class="section" id="using-the-memorydependenceanalysis-pass">
+<h3><a class="toc-backref" href="#id24">Using the <code class="docutils literal notranslate"><span class="pre">MemoryDependenceAnalysis</span></code> Pass</a><a class="headerlink" href="#using-the-memorydependenceanalysis-pass" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal notranslate"><span class="pre">memdep</span></code> pass uses alias analysis to provide high-level dependence
+information about memory-using instructions. This will tell you which store
+feeds into a load, for example. It uses caching and other techniques to be
+efficient, and is used by Dead Store Elimination, GVN, and memcpy optimizations.</p>
+</div>
+<div class="section" id="using-the-aliassettracker-class">
+<span id="aliassettracker"></span><h3><a class="toc-backref" href="#id25">Using the <code class="docutils literal notranslate"><span class="pre">AliasSetTracker</span></code> class</a><a class="headerlink" href="#using-the-aliassettracker-class" title="Permalink to this headline">¶</a></h3>
+<p>Many transformations need information about alias <strong>sets</strong> that are active in
+some scope, rather than information about pairwise aliasing. The
+<a class="reference external" href="http://llvm.org/doxygen/classllvm_1_1AliasSetTracker.html">AliasSetTracker</a>
+class is used to efficiently build these Alias Sets from the pairwise alias
+analysis information provided by the <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> interface.</p>
+<p>First you initialize the AliasSetTracker by using the â<code class="docutils literal notranslate"><span class="pre">add</span></code>â methods to add
+information about various potentially aliasing instructions in the scope you are
+interested in. Once all of the alias sets are completed, your pass should
+simply iterate through the constructed alias sets, using the <code class="docutils literal notranslate"><span class="pre">AliasSetTracker</span></code>
+<code class="docutils literal notranslate"><span class="pre">begin()</span></code>/<code class="docutils literal notranslate"><span class="pre">end()</span></code> methods.</p>
+<p>The <code class="docutils literal notranslate"><span class="pre">AliasSet</span></code>s formed by the <code class="docutils literal notranslate"><span class="pre">AliasSetTracker</span></code> are guaranteed to be
+disjoint, calculate mod/ref information and volatility for the set, and keep
+track of whether or not all of the pointers in the set are Must aliases. The
+AliasSetTracker also makes sure that sets are properly folded due to call
+instructions, and can provide a list of pointers in each set.</p>
+<p>As an example user of this, the <a class="reference external" href="doxygen/structLICM.html">Loop Invariant Code Motion</a> pass uses <code class="docutils literal notranslate"><span class="pre">AliasSetTracker</span></code>s to calculate alias
+sets for each loop nest. If an <code class="docutils literal notranslate"><span class="pre">AliasSet</span></code> in a loop is not modified, then all
+load instructions from that set may be hoisted out of the loop. If any alias
+sets are stored to <strong>and</strong> are must alias sets, then the stores may be sunk
+to outside of the loop, promoting the memory location to a register for the
+duration of the loop nest. Both of these transformations only apply if the
+pointer argument is loop-invariant.</p>
+<div class="section" id="the-aliassettracker-implementation">
+<h4><a class="toc-backref" href="#id26">The AliasSetTracker implementation</a><a class="headerlink" href="#the-aliassettracker-implementation" title="Permalink to this headline">¶</a></h4>
+<p>The AliasSetTracker class is implemented to be as efficient as possible. It
+uses the union-find algorithm to efficiently merge AliasSets when a pointer is
+inserted into the AliasSetTracker that aliases multiple sets. The primary data
+structure is a hash table mapping pointers to the AliasSet they are in.</p>
+<p>The AliasSetTracker class must maintain a list of all of the LLVM <code class="docutils literal notranslate"><span class="pre">Value*</span></code>s
+that are in each AliasSet. Since the hash table already has entries for each
+LLVM <code class="docutils literal notranslate"><span class="pre">Value*</span></code> of interest, the AliasesSets thread the linked list through
+these hash-table nodes to avoid having to allocate memory unnecessarily, and to
+make merging alias sets extremely efficient (the linked list merge is constant
+time).</p>
+<p>You shouldnât need to understand these details if you are just a client of the
+AliasSetTracker, but if you look at the code, hopefully this brief description
+will help make sense of why things are designed the way they are.</p>
+</div>
+</div>
+<div class="section" id="using-the-aliasanalysis-interface-directly">
+<h3><a class="toc-backref" href="#id27">Using the <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> interface directly</a><a class="headerlink" href="#using-the-aliasanalysis-interface-directly" title="Permalink to this headline">¶</a></h3>
+<p>If neither of these utility class are what your pass needs, you should use the
+interfaces exposed by the <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> class directly. Try to use the
+higher-level methods when possible (e.g., use mod/ref information instead of the
+<a class="reference internal" href="#alias">alias</a> method directly if possible) to get the best precision and efficiency.</p>
+</div>
+</div>
+<div class="section" id="existing-alias-analysis-implementations-and-clients">
+<h2><a class="toc-backref" href="#id28">Existing alias analysis implementations and clients</a><a class="headerlink" href="#existing-alias-analysis-implementations-and-clients" title="Permalink to this headline">¶</a></h2>
+<p>If youâre going to be working with the LLVM alias analysis infrastructure, you
+should know what clients and implementations of alias analysis are available.
+In particular, if you are implementing an alias analysis, you should be aware of
+the <a class="reference internal" href="#the-clients">the clients</a> that are useful for monitoring and evaluating different
+implementations.</p>
+<div class="section" id="available-aliasanalysis-implementations">
+<span id="various-alias-analysis-implementations"></span><h3><a class="toc-backref" href="#id29">Available <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> implementations</a><a class="headerlink" href="#available-aliasanalysis-implementations" title="Permalink to this headline">¶</a></h3>
+<p>This section lists the various implementations of the <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code>
+interface. With the exception of the <a class="reference internal" href="#aliasanalysis-no-aa"><span class="std std-ref">-no-aa</span></a>
+implementation, all of these <a class="reference internal" href="#aliasanalysis-chaining"><span class="std std-ref">chain</span></a> to other
+alias analysis implementations.</p>
+<div class="section" id="the-no-aa-pass">
+<span id="aliasanalysis-no-aa"></span><h4><a class="toc-backref" href="#id30">The <code class="docutils literal notranslate"><span class="pre">-no-aa</span></code> pass</a><a class="headerlink" href="#the-no-aa-pass" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal notranslate"><span class="pre">-no-aa</span></code> pass is just like what it sounds: an alias analysis that never
+returns any useful information. This pass can be useful if you think that alias
+analysis is doing something wrong and are trying to narrow down a problem.</p>
+</div>
+<div class="section" id="the-basicaa-pass">
+<h4><a class="toc-backref" href="#id31">The <code class="docutils literal notranslate"><span class="pre">-basicaa</span></code> pass</a><a class="headerlink" href="#the-basicaa-pass" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal notranslate"><span class="pre">-basicaa</span></code> pass is an aggressive local analysis that <em>knows</em> many
+important facts:</p>
+<ul class="simple">
+<li>Distinct globals, stack allocations, and heap allocations can never alias.</li>
+<li>Globals, stack allocations, and heap allocations never alias the null pointer.</li>
+<li>Different fields of a structure do not alias.</li>
+<li>Indexes into arrays with statically differing subscripts cannot alias.</li>
+<li>Many common standard C library functions <a class="reference internal" href="#never-access-memory-or-only-read-memory">never access memory or only read
+memory</a>.</li>
+<li>Pointers that obviously point to constant globals â<code class="docutils literal notranslate"><span class="pre">pointToConstantMemory</span></code>â.</li>
+<li>Function calls can not modify or references stack allocations if they never
+escape from the function that allocates them (a common case for automatic
+arrays).</li>
+</ul>
+</div>
+<div class="section" id="the-globalsmodref-aa-pass">
+<h4><a class="toc-backref" href="#id32">The <code class="docutils literal notranslate"><span class="pre">-globalsmodref-aa</span></code> pass</a><a class="headerlink" href="#the-globalsmodref-aa-pass" title="Permalink to this headline">¶</a></h4>
+<p>This pass implements a simple context-sensitive mod/ref and alias analysis for
+internal global variables that donât âhave their address takenâ. If a global
+does not have its address taken, the pass knows that no pointers alias the
+global. This pass also keeps track of functions that it knows never access
+memory or never read memory. This allows certain optimizations (e.g. GVN) to
+eliminate call instructions entirely.</p>
+<p>The real power of this pass is that it provides context-sensitive mod/ref
+information for call instructions. This allows the optimizer to know that calls
+to a function do not clobber or read the value of the global, allowing loads and
+stores to be eliminated.</p>
+<div class="admonition note">
+<p class="first admonition-title">Note</p>
+<p class="last">This pass is somewhat limited in its scope (only support non-address taken
+globals), but is very quick analysis.</p>
+</div>
+</div>
+<div class="section" id="the-steens-aa-pass">
+<h4><a class="toc-backref" href="#id33">The <code class="docutils literal notranslate"><span class="pre">-steens-aa</span></code> pass</a><a class="headerlink" href="#the-steens-aa-pass" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal notranslate"><span class="pre">-steens-aa</span></code> pass implements a variation on the well-known âSteensgaardâs
+algorithmâ for interprocedural alias analysis. Steensgaardâs algorithm is a
+unification-based, flow-insensitive, context-insensitive, and field-insensitive
+alias analysis that is also very scalable (effectively linear time).</p>
+<p>The LLVM <code class="docutils literal notranslate"><span class="pre">-steens-aa</span></code> pass implements a âspeculatively field-<strong>sensitive</strong>â
+version of Steensgaardâs algorithm using the Data Structure Analysis framework.
+This gives it substantially more precision than the standard algorithm while
+maintaining excellent analysis scalability.</p>
+<div class="admonition note">
+<p class="first admonition-title">Note</p>
+<p class="last"><code class="docutils literal notranslate"><span class="pre">-steens-aa</span></code> is available in the optional âpoolallocâ module. It is not part
+of the LLVM core.</p>
+</div>
+</div>
+<div class="section" id="the-ds-aa-pass">
+<h4><a class="toc-backref" href="#id34">The <code class="docutils literal notranslate"><span class="pre">-ds-aa</span></code> pass</a><a class="headerlink" href="#the-ds-aa-pass" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal notranslate"><span class="pre">-ds-aa</span></code> pass implements the full Data Structure Analysis algorithm. Data
+Structure Analysis is a modular unification-based, flow-insensitive,
+context-<strong>sensitive</strong>, and speculatively field-<strong>sensitive</strong> alias
+analysis that is also quite scalable, usually at <code class="docutils literal notranslate"><span class="pre">O(n</span> <span class="pre">*</span> <span class="pre">log(n))</span></code>.</p>
+<p>This algorithm is capable of responding to a full variety of alias analysis
+queries, and can provide context-sensitive mod/ref information as well. The
+only major facility not implemented so far is support for must-alias
+information.</p>
+<div class="admonition note">
+<p class="first admonition-title">Note</p>
+<p class="last"><code class="docutils literal notranslate"><span class="pre">-ds-aa</span></code> is available in the optional âpoolallocâ module. It is not part of
+the LLVM core.</p>
+</div>
+</div>
+<div class="section" id="the-scev-aa-pass">
+<h4><a class="toc-backref" href="#id35">The <code class="docutils literal notranslate"><span class="pre">-scev-aa</span></code> pass</a><a class="headerlink" href="#the-scev-aa-pass" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal notranslate"><span class="pre">-scev-aa</span></code> pass implements AliasAnalysis queries by translating them into
+ScalarEvolution queries. This gives it a more complete understanding of
+<code class="docutils literal notranslate"><span class="pre">getelementptr</span></code> instructions and loop induction variables than other alias
+analyses have.</p>
+</div>
+</div>
+<div class="section" id="alias-analysis-driven-transformations">
+<h3><a class="toc-backref" href="#id36">Alias analysis driven transformations</a><a class="headerlink" href="#alias-analysis-driven-transformations" title="Permalink to this headline">¶</a></h3>
+<p>LLVM includes several alias-analysis driven transformations which can be used
+with any of the implementations above.</p>
+<div class="section" id="the-adce-pass">
+<h4><a class="toc-backref" href="#id37">The <code class="docutils literal notranslate"><span class="pre">-adce</span></code> pass</a><a class="headerlink" href="#the-adce-pass" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal notranslate"><span class="pre">-adce</span></code> pass, which implements Aggressive Dead Code Elimination uses the
+<code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> interface to delete calls to functions that do not have
+side-effects and are not used.</p>
+</div>
+<div class="section" id="the-licm-pass">
+<h4><a class="toc-backref" href="#id38">The <code class="docutils literal notranslate"><span class="pre">-licm</span></code> pass</a><a class="headerlink" href="#the-licm-pass" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal notranslate"><span class="pre">-licm</span></code> pass implements various Loop Invariant Code Motion related
+transformations. It uses the <code class="docutils literal notranslate"><span class="pre">AliasAnalysis</span></code> interface for several different
+transformations:</p>
+<ul class="simple">
+<li>It uses mod/ref information to hoist or sink load instructions out of loops if
+there are no instructions in the loop that modifies the memory loaded.</li>
+<li>It uses mod/ref information to hoist function calls out of loops that do not
+write to memory and are loop-invariant.</li>
+<li>It uses alias information to promote memory objects that are loaded and stored
+to in loops to live in a register instead. It can do this if there are no may
+aliases to the loaded/stored memory location.</li>
+</ul>
+</div>
+<div class="section" id="the-argpromotion-pass">
+<h4><a class="toc-backref" href="#id39">The <code class="docutils literal notranslate"><span class="pre">-argpromotion</span></code> pass</a><a class="headerlink" href="#the-argpromotion-pass" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal notranslate"><span class="pre">-argpromotion</span></code> pass promotes by-reference arguments to be passed in
+by-value instead. In particular, if pointer arguments are only loaded from it
+passes in the value loaded instead of the address to the function. This pass
+uses alias information to make sure that the value loaded from the argument
+pointer is not modified between the entry of the function and any load of the
+pointer.</p>
+</div>
+<div class="section" id="the-gvn-memcpyopt-and-dse-passes">
+<h4><a class="toc-backref" href="#id40">The <code class="docutils literal notranslate"><span class="pre">-gvn</span></code>, <code class="docutils literal notranslate"><span class="pre">-memcpyopt</span></code>, and <code class="docutils literal notranslate"><span class="pre">-dse</span></code> passes</a><a class="headerlink" href="#the-gvn-memcpyopt-and-dse-passes" title="Permalink to this headline">¶</a></h4>
+<p>These passes use AliasAnalysis information to reason about loads and stores.</p>
+</div>
+</div>
+<div class="section" id="clients-for-debugging-and-evaluation-of-implementations">
+<span id="the-clients"></span><h3><a class="toc-backref" href="#id41">Clients for debugging and evaluation of implementations</a><a class="headerlink" href="#clients-for-debugging-and-evaluation-of-implementations" title="Permalink to this headline">¶</a></h3>
+<p>These passes are useful for evaluating the various alias analysis
+implementations. You can use them with commands like:</p>
+<div class="highlight-bash notranslate"><div class="highlight"><pre><span></span>% opt -ds-aa -aa-eval foo.bc -disable-output -stats
+</pre></div>
+</div>
+<div class="section" id="the-print-alias-sets-pass">
+<h4><a class="toc-backref" href="#id42">The <code class="docutils literal notranslate"><span class="pre">-print-alias-sets</span></code> pass</a><a class="headerlink" href="#the-print-alias-sets-pass" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal notranslate"><span class="pre">-print-alias-sets</span></code> pass is exposed as part of the <code class="docutils literal notranslate"><span class="pre">opt</span></code> tool to print
+out the Alias Sets formed by the <a class="reference internal" href="#aliassettracker">AliasSetTracker</a> class. This is useful if
+youâre using the <code class="docutils literal notranslate"><span class="pre">AliasSetTracker</span></code> class. To use it, use something like:</p>
+<div class="highlight-bash notranslate"><div class="highlight"><pre><span></span>% opt -ds-aa -print-alias-sets -disable-output
+</pre></div>
+</div>
+</div>
+<div class="section" id="the-aa-eval-pass">
+<h4><a class="toc-backref" href="#id43">The <code class="docutils literal notranslate"><span class="pre">-aa-eval</span></code> pass</a><a class="headerlink" href="#the-aa-eval-pass" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal notranslate"><span class="pre">-aa-eval</span></code> pass simply iterates through all pairs of pointers in a
+function and asks an alias analysis whether or not the pointers alias. This
+gives an indication of the precision of the alias analysis. Statistics are
+printed indicating the percent of no/may/must aliases found (a more precise
+algorithm will have a lower number of may aliases).</p>
+</div>
+</div>
+</div>
+<div class="section" id="memory-dependence-analysis">
+<h2><a class="toc-backref" href="#id44">Memory Dependence Analysis</a><a class="headerlink" href="#memory-dependence-analysis" title="Permalink to this headline">¶</a></h2>
+<div class="admonition note">
+<p class="first admonition-title">Note</p>
+<p class="last">We are currently in the process of migrating things from
+<code class="docutils literal notranslate"><span class="pre">MemoryDependenceAnalysis</span></code> to <a class="reference internal" href="MemorySSA.html"><span class="doc">MemorySSA</span></a>. Please try to use
+that instead.</p>
+</div>
+<p>If youâre just looking to be a client of alias analysis information, consider
+using the Memory Dependence Analysis interface instead. MemDep is a lazy,
+caching layer on top of alias analysis that is able to answer the question of
+what preceding memory operations a given instruction depends on, either at an
+intra- or inter-block level. Because of its laziness and caching policy, using
+MemDep can be a significant performance win over accessing alias analysis
+directly.</p>
+</div>
+</div>
+
+
+ </div>
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+
+ <div class="section" id="llvm-atomic-instructions-and-concurrency-guide">
+<h1>LLVM Atomic Instructions and Concurrency Guide<a class="headerlink" href="#llvm-atomic-instructions-and-concurrency-guide" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#introduction" id="id4">Introduction</a></li>
+<li><a class="reference internal" href="#optimization-outside-atomic" id="id5">Optimization outside atomic</a></li>
+<li><a class="reference internal" href="#atomic-instructions" id="id6">Atomic instructions</a></li>
+<li><a class="reference internal" href="#atomic-orderings" id="id7">Atomic orderings</a><ul>
+<li><a class="reference internal" href="#notatomic" id="id8">NotAtomic</a></li>
+<li><a class="reference internal" href="#unordered" id="id9">Unordered</a></li>
+<li><a class="reference internal" href="#monotonic" id="id10">Monotonic</a></li>
+<li><a class="reference internal" href="#acquire" id="id11">Acquire</a></li>
+<li><a class="reference internal" href="#release" id="id12">Release</a></li>
+<li><a class="reference internal" href="#acquirerelease" id="id13">AcquireRelease</a></li>
+<li><a class="reference internal" href="#sequentiallyconsistent" id="id14">SequentiallyConsistent</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#atomics-and-ir-optimization" id="id15">Atomics and IR optimization</a></li>
+<li><a class="reference internal" href="#atomics-and-codegen" id="id16">Atomics and Codegen</a></li>
+<li><a class="reference internal" href="#libcalls-atomic" id="id17">Libcalls: __atomic_*</a></li>
+<li><a class="reference internal" href="#libcalls-sync" id="id18">Libcalls: __sync_*</a></li>
+</ul>
+</div>
+<div class="section" id="introduction">
+<h2><a class="toc-backref" href="#id4">Introduction</a><a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
+<p>LLVM supports instructions which are well-defined in the presence of threads and
+asynchronous signals.</p>
+<p>The atomic instructions are designed specifically to provide readable IR and
+optimized code generation for the following:</p>
+<ul class="simple">
+<li>The C++11 <code class="docutils literal notranslate"><span class="pre"><atomic></span></code> header. (<a class="reference external" href="http://www.open-std.org/jtc1/sc22/wg21/">C++11 draft available here</a>.) (<a class="reference external" href="http://www.open-std.org/jtc1/sc22/wg14/">C11 draft available here</a>.)</li>
+<li>Proper semantics for Java-style memory, for both <code class="docutils literal notranslate"><span class="pre">volatile</span></code> and regular
+shared variables. (<a class="reference external" href="http://docs.oracle.com/javase/specs/jls/se8/html/jls-17.html">Java Specification</a>)</li>
+<li>gcc-compatible <code class="docutils literal notranslate"><span class="pre">__sync_*</span></code> builtins. (<a class="reference external" href="https://gcc.gnu.org/onlinedocs/gcc/_005f_005fsync-Builtins.html">Description</a>)</li>
+<li>Other scenarios with atomic semantics, including <code class="docutils literal notranslate"><span class="pre">static</span></code> variables with
+non-trivial constructors in C++.</li>
+</ul>
+<p>Atomic and volatile in the IR are orthogonal; âvolatileâ is the C/C++ volatile,
+which ensures that every volatile load and store happens and is performed in the
+stated order. A couple examples: if a SequentiallyConsistent store is
+immediately followed by another SequentiallyConsistent store to the same
+address, the first store can be erased. This transformation is not allowed for a
+pair of volatile stores. On the other hand, a non-volatile non-atomic load can
+be moved across a volatile load freely, but not an Acquire load.</p>
+<p>This document is intended to provide a guide to anyone either writing a frontend
+for LLVM or working on optimization passes for LLVM with a guide for how to deal
+with instructions with special semantics in the presence of concurrency. This
+is not intended to be a precise guide to the semantics; the details can get
+extremely complicated and unreadable, and are not usually necessary.</p>
+</div>
+<div class="section" id="optimization-outside-atomic">
+<span id="id1"></span><h2><a class="toc-backref" href="#id5">Optimization outside atomic</a><a class="headerlink" href="#optimization-outside-atomic" title="Permalink to this headline">¶</a></h2>
+<p>The basic <code class="docutils literal notranslate"><span class="pre">'load'</span></code> and <code class="docutils literal notranslate"><span class="pre">'store'</span></code> allow a variety of optimizations, but can
+lead to undefined results in a concurrent environment; see <a class="reference internal" href="#notatomic">NotAtomic</a>. This
+section specifically goes into the one optimizer restriction which applies in
+concurrent environments, which gets a bit more of an extended description
+because any optimization dealing with stores needs to be aware of it.</p>
+<p>From the optimizerâs point of view, the rule is that if there are not any
+instructions with atomic ordering involved, concurrency does not matter, with
+one exception: if a variable might be visible to another thread or signal
+handler, a store cannot be inserted along a path where it might not execute
+otherwise. Take the following example:</p>
+<div class="highlight-c notranslate"><div class="highlight"><pre><span></span><span class="cm">/* C code, for readability; run through clang -O2 -S -emit-llvm to get</span>
+<span class="cm"> equivalent IR */</span>
+ <span class="kt">int</span> <span class="n">x</span><span class="p">;</span>
+ <span class="kt">void</span> <span class="nf">f</span><span class="p">(</span><span class="kt">int</span><span class="o">*</span> <span class="n">a</span><span class="p">)</span> <span class="p">{</span>
+ <span class="k">for</span> <span class="p">(</span><span class="kt">int</span> <span class="n">i</span> <span class="o">=</span> <span class="mi">0</span><span class="p">;</span> <span class="n">i</span> <span class="o"><</span> <span class="mi">100</span><span class="p">;</span> <span class="n">i</span><span class="o">++</span><span class="p">)</span> <span class="p">{</span>
+ <span class="k">if</span> <span class="p">(</span><span class="n">a</span><span class="p">[</span><span class="n">i</span><span class="p">])</span>
+ <span class="n">x</span> <span class="o">+=</span> <span class="mi">1</span><span class="p">;</span>
+ <span class="p">}</span>
+ <span class="p">}</span>
+</pre></div>
+</div>
+<p>The following is equivalent in non-concurrent situations:</p>
+<div class="highlight-c notranslate"><div class="highlight"><pre><span></span><span class="kt">int</span> <span class="n">x</span><span class="p">;</span>
+<span class="kt">void</span> <span class="nf">f</span><span class="p">(</span><span class="kt">int</span><span class="o">*</span> <span class="n">a</span><span class="p">)</span> <span class="p">{</span>
+ <span class="kt">int</span> <span class="n">xtemp</span> <span class="o">=</span> <span class="n">x</span><span class="p">;</span>
+ <span class="k">for</span> <span class="p">(</span><span class="kt">int</span> <span class="n">i</span> <span class="o">=</span> <span class="mi">0</span><span class="p">;</span> <span class="n">i</span> <span class="o"><</span> <span class="mi">100</span><span class="p">;</span> <span class="n">i</span><span class="o">++</span><span class="p">)</span> <span class="p">{</span>
+ <span class="k">if</span> <span class="p">(</span><span class="n">a</span><span class="p">[</span><span class="n">i</span><span class="p">])</span>
+ <span class="n">xtemp</span> <span class="o">+=</span> <span class="mi">1</span><span class="p">;</span>
+ <span class="p">}</span>
+ <span class="n">x</span> <span class="o">=</span> <span class="n">xtemp</span><span class="p">;</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+<p>However, LLVM is not allowed to transform the former to the latter: it could
+indirectly introduce undefined behavior if another thread can access <code class="docutils literal notranslate"><span class="pre">x</span></code> at
+the same time. (This example is particularly of interest because before the
+concurrency model was implemented, LLVM would perform this transformation.)</p>
+<p>Note that speculative loads are allowed; a load which is part of a race returns
+<code class="docutils literal notranslate"><span class="pre">undef</span></code>, but does not have undefined behavior.</p>
+</div>
+<div class="section" id="atomic-instructions">
+<h2><a class="toc-backref" href="#id6">Atomic instructions</a><a class="headerlink" href="#atomic-instructions" title="Permalink to this headline">¶</a></h2>
+<p>For cases where simple loads and stores are not sufficient, LLVM provides
+various atomic instructions. The exact guarantees provided depend on the
+ordering; see <a class="reference internal" href="#atomic-orderings">Atomic orderings</a>.</p>
+<p><code class="docutils literal notranslate"><span class="pre">load</span> <span class="pre">atomic</span></code> and <code class="docutils literal notranslate"><span class="pre">store</span> <span class="pre">atomic</span></code> provide the same basic functionality as
+non-atomic loads and stores, but provide additional guarantees in situations
+where threads and signals are involved.</p>
+<p><code class="docutils literal notranslate"><span class="pre">cmpxchg</span></code> and <code class="docutils literal notranslate"><span class="pre">atomicrmw</span></code> are essentially like an atomic load followed by an
+atomic store (where the store is conditional for <code class="docutils literal notranslate"><span class="pre">cmpxchg</span></code>), but no other
+memory operation can happen on any thread between the load and store.</p>
+<p>A <code class="docutils literal notranslate"><span class="pre">fence</span></code> provides Acquire and/or Release ordering which is not part of
+another operation; it is normally used along with Monotonic memory operations.
+A Monotonic load followed by an Acquire fence is roughly equivalent to an
+Acquire load, and a Monotonic store following a Release fence is roughly
+equivalent to a Release store. SequentiallyConsistent fences behave as both
+an Acquire and a Release fence, and offer some additional complicated
+guarantees, see the C++11 standard for details.</p>
+<p>Frontends generating atomic instructions generally need to be aware of the
+target to some degree; atomic instructions are guaranteed to be lock-free, and
+therefore an instruction which is wider than the target natively supports can be
+impossible to generate.</p>
+</div>
+<div class="section" id="atomic-orderings">
+<span id="id2"></span><h2><a class="toc-backref" href="#id7">Atomic orderings</a><a class="headerlink" href="#atomic-orderings" title="Permalink to this headline">¶</a></h2>
+<p>In order to achieve a balance between performance and necessary guarantees,
+there are six levels of atomicity. They are listed in order of strength; each
+level includes all the guarantees of the previous level except for
+Acquire/Release. (See also <a class="reference external" href="LangRef.html#ordering">LangRef Ordering</a>.)</p>
+<div class="section" id="notatomic">
+<span id="id3"></span><h3><a class="toc-backref" href="#id8">NotAtomic</a><a class="headerlink" href="#notatomic" title="Permalink to this headline">¶</a></h3>
+<p>NotAtomic is the obvious, a load or store which is not atomic. (This isnât
+really a level of atomicity, but is listed here for comparison.) This is
+essentially a regular load or store. If there is a race on a given memory
+location, loads from that location return undef.</p>
+<dl class="docutils">
+<dt>Relevant standard</dt>
+<dd>This is intended to match shared variables in C/C++, and to be used in any
+other context where memory access is necessary, and a race is impossible. (The
+precise definition is in <a class="reference external" href="LangRef.html#memmodel">LangRef Memory Model</a>.)</dd>
+<dt>Notes for frontends</dt>
+<dd>The rule is essentially that all memory accessed with basic loads and stores
+by multiple threads should be protected by a lock or other synchronization;
+otherwise, you are likely to run into undefined behavior. If your frontend is
+for a âsafeâ language like Java, use Unordered to load and store any shared
+variable. Note that NotAtomic volatile loads and stores are not properly
+atomic; do not try to use them as a substitute. (Per the C/C++ standards,
+volatile does provide some limited guarantees around asynchronous signals, but
+atomics are generally a better solution.)</dd>
+<dt>Notes for optimizers</dt>
+<dd>Introducing loads to shared variables along a codepath where they would not
+otherwise exist is allowed; introducing stores to shared variables is not. See
+<a class="reference internal" href="#optimization-outside-atomic">Optimization outside atomic</a>.</dd>
+<dt>Notes for code generation</dt>
+<dd>The one interesting restriction here is that it is not allowed to write to
+bytes outside of the bytes relevant to a store. This is mostly relevant to
+unaligned stores: it is not allowed in general to convert an unaligned store
+into two aligned stores of the same width as the unaligned store. Backends are
+also expected to generate an i8 store as an i8 store, and not an instruction
+which writes to surrounding bytes. (If you are writing a backend for an
+architecture which cannot satisfy these restrictions and cares about
+concurrency, please send an email to llvm-dev.)</dd>
+</dl>
+</div>
+<div class="section" id="unordered">
+<h3><a class="toc-backref" href="#id9">Unordered</a><a class="headerlink" href="#unordered" title="Permalink to this headline">¶</a></h3>
+<p>Unordered is the lowest level of atomicity. It essentially guarantees that races
+produce somewhat sane results instead of having undefined behavior. It also
+guarantees the operation to be lock-free, so it does not depend on the data
+being part of a special atomic structure or depend on a separate per-process
+global lock. Note that code generation will fail for unsupported atomic
+operations; if you need such an operation, use explicit locking.</p>
+<dl class="docutils">
+<dt>Relevant standard</dt>
+<dd>This is intended to match the Java memory model for shared variables.</dd>
+<dt>Notes for frontends</dt>
+<dd>This cannot be used for synchronization, but is useful for Java and other
+âsafeâ languages which need to guarantee that the generated code never
+exhibits undefined behavior. Note that this guarantee is cheap on common
+platforms for loads of a native width, but can be expensive or unavailable for
+wider loads, like a 64-bit store on ARM. (A frontend for Java or other âsafeâ
+languages would normally split a 64-bit store on ARM into two 32-bit unordered
+stores.)</dd>
+<dt>Notes for optimizers</dt>
+<dd>In terms of the optimizer, this prohibits any transformation that transforms a
+single load into multiple loads, transforms a store into multiple stores,
+narrows a store, or stores a value which would not be stored otherwise. Some
+examples of unsafe optimizations are narrowing an assignment into a bitfield,
+rematerializing a load, and turning loads and stores into a memcpy
+call. Reordering unordered operations is safe, though, and optimizers should
+take advantage of that because unordered operations are common in languages
+that need them.</dd>
+<dt>Notes for code generation</dt>
+<dd>These operations are required to be atomic in the sense that if you use
+unordered loads and unordered stores, a load cannot see a value which was
+never stored. A normal load or store instruction is usually sufficient, but
+note that an unordered load or store cannot be split into multiple
+instructions (or an instruction which does multiple memory operations, like
+<code class="docutils literal notranslate"><span class="pre">LDRD</span></code> on ARM without LPAE, or not naturally-aligned <code class="docutils literal notranslate"><span class="pre">LDRD</span></code> on LPAE ARM).</dd>
+</dl>
+</div>
+<div class="section" id="monotonic">
+<h3><a class="toc-backref" href="#id10">Monotonic</a><a class="headerlink" href="#monotonic" title="Permalink to this headline">¶</a></h3>
+<p>Monotonic is the weakest level of atomicity that can be used in synchronization
+primitives, although it does not provide any general synchronization. It
+essentially guarantees that if you take all the operations affecting a specific
+address, a consistent ordering exists.</p>
+<dl class="docutils">
+<dt>Relevant standard</dt>
+<dd>This corresponds to the C++11/C11 <code class="docutils literal notranslate"><span class="pre">memory_order_relaxed</span></code>; see those
+standards for the exact definition.</dd>
+<dt>Notes for frontends</dt>
+<dd>If you are writing a frontend which uses this directly, use with caution. The
+guarantees in terms of synchronization are very weak, so make sure these are
+only used in a pattern which you know is correct. Generally, these would
+either be used for atomic operations which do not protect other memory (like
+an atomic counter), or along with a <code class="docutils literal notranslate"><span class="pre">fence</span></code>.</dd>
+<dt>Notes for optimizers</dt>
+<dd>In terms of the optimizer, this can be treated as a read+write on the relevant
+memory location (and alias analysis will take advantage of that). In addition,
+it is legal to reorder non-atomic and Unordered loads around Monotonic
+loads. CSE/DSE and a few other optimizations are allowed, but Monotonic
+operations are unlikely to be used in ways which would make those
+optimizations useful.</dd>
+<dt>Notes for code generation</dt>
+<dd>Code generation is essentially the same as that for unordered for loads and
+stores. No fences are required. <code class="docutils literal notranslate"><span class="pre">cmpxchg</span></code> and <code class="docutils literal notranslate"><span class="pre">atomicrmw</span></code> are required
+to appear as a single operation.</dd>
+</dl>
+</div>
+<div class="section" id="acquire">
+<h3><a class="toc-backref" href="#id11">Acquire</a><a class="headerlink" href="#acquire" title="Permalink to this headline">¶</a></h3>
+<p>Acquire provides a barrier of the sort necessary to acquire a lock to access
+other memory with normal loads and stores.</p>
+<dl class="docutils">
+<dt>Relevant standard</dt>
+<dd>This corresponds to the C++11/C11 <code class="docutils literal notranslate"><span class="pre">memory_order_acquire</span></code>. It should also be
+used for C++11/C11 <code class="docutils literal notranslate"><span class="pre">memory_order_consume</span></code>.</dd>
+<dt>Notes for frontends</dt>
+<dd>If you are writing a frontend which uses this directly, use with caution.
+Acquire only provides a semantic guarantee when paired with a Release
+operation.</dd>
+<dt>Notes for optimizers</dt>
+<dd>Optimizers not aware of atomics can treat this like a nothrow call. It is
+also possible to move stores from before an Acquire load or read-modify-write
+operation to after it, and move non-Acquire loads from before an Acquire
+operation to after it.</dd>
+<dt>Notes for code generation</dt>
+<dd>Architectures with weak memory ordering (essentially everything relevant today
+except x86 and SPARC) require some sort of fence to maintain the Acquire
+semantics. The precise fences required varies widely by architecture, but for
+a simple implementation, most architectures provide a barrier which is strong
+enough for everything (<code class="docutils literal notranslate"><span class="pre">dmb</span></code> on ARM, <code class="docutils literal notranslate"><span class="pre">sync</span></code> on PowerPC, etc.). Putting
+such a fence after the equivalent Monotonic operation is sufficient to
+maintain Acquire semantics for a memory operation.</dd>
+</dl>
+</div>
+<div class="section" id="release">
+<h3><a class="toc-backref" href="#id12">Release</a><a class="headerlink" href="#release" title="Permalink to this headline">¶</a></h3>
+<p>Release is similar to Acquire, but with a barrier of the sort necessary to
+release a lock.</p>
+<dl class="docutils">
+<dt>Relevant standard</dt>
+<dd>This corresponds to the C++11/C11 <code class="docutils literal notranslate"><span class="pre">memory_order_release</span></code>.</dd>
+<dt>Notes for frontends</dt>
+<dd>If you are writing a frontend which uses this directly, use with caution.
+Release only provides a semantic guarantee when paired with a Acquire
+operation.</dd>
+<dt>Notes for optimizers</dt>
+<dd>Optimizers not aware of atomics can treat this like a nothrow call. It is
+also possible to move loads from after a Release store or read-modify-write
+operation to before it, and move non-Release stores from after an Release
+operation to before it.</dd>
+<dt>Notes for code generation</dt>
+<dd>See the section on Acquire; a fence before the relevant operation is usually
+sufficient for Release. Note that a store-store fence is not sufficient to
+implement Release semantics; store-store fences are generally not exposed to
+IR because they are extremely difficult to use correctly.</dd>
+</dl>
+</div>
+<div class="section" id="acquirerelease">
+<h3><a class="toc-backref" href="#id13">AcquireRelease</a><a class="headerlink" href="#acquirerelease" title="Permalink to this headline">¶</a></h3>
+<p>AcquireRelease (<code class="docutils literal notranslate"><span class="pre">acq_rel</span></code> in IR) provides both an Acquire and a Release
+barrier (for fences and operations which both read and write memory).</p>
+<dl class="docutils">
+<dt>Relevant standard</dt>
+<dd>This corresponds to the C++11/C11 <code class="docutils literal notranslate"><span class="pre">memory_order_acq_rel</span></code>.</dd>
+<dt>Notes for frontends</dt>
+<dd>If you are writing a frontend which uses this directly, use with caution.
+Acquire only provides a semantic guarantee when paired with a Release
+operation, and vice versa.</dd>
+<dt>Notes for optimizers</dt>
+<dd>In general, optimizers should treat this like a nothrow call; the possible
+optimizations are usually not interesting.</dd>
+<dt>Notes for code generation</dt>
+<dd>This operation has Acquire and Release semantics; see the sections on Acquire
+and Release.</dd>
+</dl>
+</div>
+<div class="section" id="sequentiallyconsistent">
+<h3><a class="toc-backref" href="#id14">SequentiallyConsistent</a><a class="headerlink" href="#sequentiallyconsistent" title="Permalink to this headline">¶</a></h3>
+<p>SequentiallyConsistent (<code class="docutils literal notranslate"><span class="pre">seq_cst</span></code> in IR) provides Acquire semantics for loads
+and Release semantics for stores. Additionally, it guarantees that a total
+ordering exists between all SequentiallyConsistent operations.</p>
+<dl class="docutils">
+<dt>Relevant standard</dt>
+<dd>This corresponds to the C++11/C11 <code class="docutils literal notranslate"><span class="pre">memory_order_seq_cst</span></code>, Java volatile, and
+the gcc-compatible <code class="docutils literal notranslate"><span class="pre">__sync_*</span></code> builtins which do not specify otherwise.</dd>
+<dt>Notes for frontends</dt>
+<dd>If a frontend is exposing atomic operations, these are much easier to reason
+about for the programmer than other kinds of operations, and using them is
+generally a practical performance tradeoff.</dd>
+<dt>Notes for optimizers</dt>
+<dd>Optimizers not aware of atomics can treat this like a nothrow call. For
+SequentiallyConsistent loads and stores, the same reorderings are allowed as
+for Acquire loads and Release stores, except that SequentiallyConsistent
+operations may not be reordered.</dd>
+<dt>Notes for code generation</dt>
+<dd>SequentiallyConsistent loads minimally require the same barriers as Acquire
+operations and SequentiallyConsistent stores require Release
+barriers. Additionally, the code generator must enforce ordering between
+SequentiallyConsistent stores followed by SequentiallyConsistent loads. This
+is usually done by emitting either a full fence before the loads or a full
+fence after the stores; which is preferred varies by architecture.</dd>
+</dl>
+</div>
+</div>
+<div class="section" id="atomics-and-ir-optimization">
+<h2><a class="toc-backref" href="#id15">Atomics and IR optimization</a><a class="headerlink" href="#atomics-and-ir-optimization" title="Permalink to this headline">¶</a></h2>
+<p>Predicates for optimizer writers to query:</p>
+<ul class="simple">
+<li><code class="docutils literal notranslate"><span class="pre">isSimple()</span></code>: A load or store which is not volatile or atomic. This is
+what, for example, memcpyopt would check for operations it might transform.</li>
+<li><code class="docutils literal notranslate"><span class="pre">isUnordered()</span></code>: A load or store which is not volatile and at most
+Unordered. This would be checked, for example, by LICM before hoisting an
+operation.</li>
+<li><code class="docutils literal notranslate"><span class="pre">mayReadFromMemory()</span></code>/<code class="docutils literal notranslate"><span class="pre">mayWriteToMemory()</span></code>: Existing predicate, but note
+that they return true for any operation which is volatile or at least
+Monotonic.</li>
+<li><code class="docutils literal notranslate"><span class="pre">isStrongerThan</span></code> / <code class="docutils literal notranslate"><span class="pre">isAtLeastOrStrongerThan</span></code>: These are predicates on
+orderings. They can be useful for passes that are aware of atomics, for
+example to do DSE across a single atomic access, but not across a
+release-acquire pair (see MemoryDependencyAnalysis for an example of this)</li>
+<li>Alias analysis: Note that AA will return ModRef for anything Acquire or
+Release, and for the address accessed by any Monotonic operation.</li>
+</ul>
+<p>To support optimizing around atomic operations, make sure you are using the
+right predicates; everything should work if that is done. If your pass should
+optimize some atomic operations (Unordered operations in particular), make sure
+it doesnât replace an atomic load or store with a non-atomic operation.</p>
+<p>Some examples of how optimizations interact with various kinds of atomic
+operations:</p>
+<ul class="simple">
+<li><code class="docutils literal notranslate"><span class="pre">memcpyopt</span></code>: An atomic operation cannot be optimized into part of a
+memcpy/memset, including unordered loads/stores. It can pull operations
+across some atomic operations.</li>
+<li>LICM: Unordered loads/stores can be moved out of a loop. It just treats
+monotonic operations like a read+write to a memory location, and anything
+stricter than that like a nothrow call.</li>
+<li>DSE: Unordered stores can be DSEâed like normal stores. Monotonic stores can
+be DSEâed in some cases, but itâs tricky to reason about, and not especially
+important. It is possible in some case for DSE to operate across a stronger
+atomic operation, but it is fairly tricky. DSE delegates this reasoning to
+MemoryDependencyAnalysis (which is also used by other passes like GVN).</li>
+<li>Folding a load: Any atomic load from a constant global can be constant-folded,
+because it cannot be observed. Similar reasoning allows sroa with
+atomic loads and stores.</li>
+</ul>
+</div>
+<div class="section" id="atomics-and-codegen">
+<h2><a class="toc-backref" href="#id16">Atomics and Codegen</a><a class="headerlink" href="#atomics-and-codegen" title="Permalink to this headline">¶</a></h2>
+<p>Atomic operations are represented in the SelectionDAG with <code class="docutils literal notranslate"><span class="pre">ATOMIC_*</span></code> opcodes.
+On architectures which use barrier instructions for all atomic ordering (like
+ARM), appropriate fences can be emitted by the AtomicExpand Codegen pass if
+<code class="docutils literal notranslate"><span class="pre">setInsertFencesForAtomic()</span></code> was used.</p>
+<p>The MachineMemOperand for all atomic operations is currently marked as volatile;
+this is not correct in the IR sense of volatile, but CodeGen handles anything
+marked volatile very conservatively. This should get fixed at some point.</p>
+<p>One very important property of the atomic operations is that if your backend
+supports any inline lock-free atomic operations of a given size, you should
+support <em>ALL</em> operations of that size in a lock-free manner.</p>
+<p>When the target implements atomic <code class="docutils literal notranslate"><span class="pre">cmpxchg</span></code> or LL/SC instructions (as most do)
+this is trivial: all the other operations can be implemented on top of those
+primitives. However, on many older CPUs (e.g. ARMv5, SparcV8, Intel 80386) there
+are atomic load and store instructions, but no <code class="docutils literal notranslate"><span class="pre">cmpxchg</span></code> or LL/SC. As it is
+invalid to implement <code class="docutils literal notranslate"><span class="pre">atomic</span> <span class="pre">load</span></code> using the native instruction, but
+<code class="docutils literal notranslate"><span class="pre">cmpxchg</span></code> using a library call to a function that uses a mutex, <code class="docutils literal notranslate"><span class="pre">atomic</span>
+<span class="pre">load</span></code> must <em>also</em> expand to a library call on such architectures, so that it
+can remain atomic with regards to a simultaneous <code class="docutils literal notranslate"><span class="pre">cmpxchg</span></code>, by using the same
+mutex.</p>
+<p>AtomicExpandPass can help with that: it will expand all atomic operations to the
+proper <code class="docutils literal notranslate"><span class="pre">__atomic_*</span></code> libcalls for any size above the maximum set by
+<code class="docutils literal notranslate"><span class="pre">setMaxAtomicSizeInBitsSupported</span></code> (which defaults to 0).</p>
+<p>On x86, all atomic loads generate a <code class="docutils literal notranslate"><span class="pre">MOV</span></code>. SequentiallyConsistent stores
+generate an <code class="docutils literal notranslate"><span class="pre">XCHG</span></code>, other stores generate a <code class="docutils literal notranslate"><span class="pre">MOV</span></code>. SequentiallyConsistent
+fences generate an <code class="docutils literal notranslate"><span class="pre">MFENCE</span></code>, other fences do not cause any code to be
+generated. <code class="docutils literal notranslate"><span class="pre">cmpxchg</span></code> uses the <code class="docutils literal notranslate"><span class="pre">LOCK</span> <span class="pre">CMPXCHG</span></code> instruction. <code class="docutils literal notranslate"><span class="pre">atomicrmw</span> <span class="pre">xchg</span></code>
+uses <code class="docutils literal notranslate"><span class="pre">XCHG</span></code>, <code class="docutils literal notranslate"><span class="pre">atomicrmw</span> <span class="pre">add</span></code> and <code class="docutils literal notranslate"><span class="pre">atomicrmw</span> <span class="pre">sub</span></code> use <code class="docutils literal notranslate"><span class="pre">XADD</span></code>, and all
+other <code class="docutils literal notranslate"><span class="pre">atomicrmw</span></code> operations generate a loop with <code class="docutils literal notranslate"><span class="pre">LOCK</span> <span class="pre">CMPXCHG</span></code>. Depending
+on the users of the result, some <code class="docutils literal notranslate"><span class="pre">atomicrmw</span></code> operations can be translated into
+operations like <code class="docutils literal notranslate"><span class="pre">LOCK</span> <span class="pre">AND</span></code>, but that does not work in general.</p>
+<p>On ARM (before v8), MIPS, and many other RISC architectures, Acquire, Release,
+and SequentiallyConsistent semantics require barrier instructions for every such
+operation. Loads and stores generate normal instructions. <code class="docutils literal notranslate"><span class="pre">cmpxchg</span></code> and
+<code class="docutils literal notranslate"><span class="pre">atomicrmw</span></code> can be represented using a loop with LL/SC-style instructions
+which take some sort of exclusive lock on a cache line (<code class="docutils literal notranslate"><span class="pre">LDREX</span></code> and <code class="docutils literal notranslate"><span class="pre">STREX</span></code>
+on ARM, etc.).</p>
+<p>It is often easiest for backends to use AtomicExpandPass to lower some of the
+atomic constructs. Here are some lowerings it can do:</p>
+<ul class="simple">
+<li>cmpxchg -> loop with load-linked/store-conditional
+by overriding <code class="docutils literal notranslate"><span class="pre">shouldExpandAtomicCmpXchgInIR()</span></code>, <code class="docutils literal notranslate"><span class="pre">emitLoadLinked()</span></code>,
+<code class="docutils literal notranslate"><span class="pre">emitStoreConditional()</span></code></li>
+<li>large loads/stores -> ll-sc/cmpxchg
+by overriding <code class="docutils literal notranslate"><span class="pre">shouldExpandAtomicStoreInIR()</span></code>/<code class="docutils literal notranslate"><span class="pre">shouldExpandAtomicLoadInIR()</span></code></li>
+<li>strong atomic accesses -> monotonic accesses + fences by overriding
+<code class="docutils literal notranslate"><span class="pre">shouldInsertFencesForAtomic()</span></code>, <code class="docutils literal notranslate"><span class="pre">emitLeadingFence()</span></code>, and
+<code class="docutils literal notranslate"><span class="pre">emitTrailingFence()</span></code></li>
+<li>atomic rmw -> loop with cmpxchg or load-linked/store-conditional
+by overriding <code class="docutils literal notranslate"><span class="pre">expandAtomicRMWInIR()</span></code></li>
+<li>expansion to __atomic_* libcalls for unsupported sizes.</li>
+<li>part-word atomicrmw/cmpxchg -> target-specific intrinsic by overriding
+<code class="docutils literal notranslate"><span class="pre">shouldExpandAtomicRMWInIR</span></code>, <code class="docutils literal notranslate"><span class="pre">emitMaskedAtomicRMWIntrinsic</span></code>,
+<code class="docutils literal notranslate"><span class="pre">shouldExpandAtomicCmpXchgInIR</span></code>, and <code class="docutils literal notranslate"><span class="pre">emitMaskedAtomicCmpXchgIntrinsic</span></code>.</li>
+</ul>
+<p>For an example of these look at the ARM (first five lowerings) or RISC-V (last
+lowering) backend.</p>
+<p>AtomicExpandPass supports two strategies for lowering atomicrmw/cmpxchg to
+load-linked/store-conditional (LL/SC) loops. The first expands the LL/SC loop
+in IR, calling target lowering hooks to emit intrinsics for the LL and SC
+operations. However, many architectures have strict requirements for LL/SC
+loops to ensure forward progress, such as restrictions on the number and type
+of instructions in the loop. It isnât possible to enforce these restrictions
+when the loop is expanded in LLVM IR, and so affected targets may prefer to
+expand to LL/SC loops at a very late stage (i.e. after register allocation).
+AtomicExpandPass can help support lowering of part-word atomicrmw or cmpxchg
+using this strategy by producing IR for any shifting and masking that can be
+performed outside of the LL/SC loop.</p>
+</div>
+<div class="section" id="libcalls-atomic">
+<h2><a class="toc-backref" href="#id17">Libcalls: __atomic_*</a><a class="headerlink" href="#libcalls-atomic" title="Permalink to this headline">¶</a></h2>
+<p>There are two kinds of atomic library calls that are generated by LLVM. Please
+note that both sets of library functions somewhat confusingly share the names of
+builtin functions defined by clang. Despite this, the library functions are
+not directly related to the builtins: it is <em>not</em> the case that <code class="docutils literal notranslate"><span class="pre">__atomic_*</span></code>
+builtins lower to <code class="docutils literal notranslate"><span class="pre">__atomic_*</span></code> library calls and <code class="docutils literal notranslate"><span class="pre">__sync_*</span></code> builtins lower
+to <code class="docutils literal notranslate"><span class="pre">__sync_*</span></code> library calls.</p>
+<p>The first set of library functions are named <code class="docutils literal notranslate"><span class="pre">__atomic_*</span></code>. This set has been
+âstandardizedâ by GCC, and is described below. (See also <a class="reference external" href="https://gcc.gnu.org/wiki/Atomic/GCCMM/LIbrary">GCCâs documentation</a>)</p>
+<p>LLVMâs AtomicExpandPass will translate atomic operations on data sizes above
+<code class="docutils literal notranslate"><span class="pre">MaxAtomicSizeInBitsSupported</span></code> into calls to these functions.</p>
+<p>There are four generic functions, which can be called with data of any size or
+alignment:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">void</span> <span class="n">__atomic_load</span><span class="p">(</span><span class="n">size_t</span> <span class="n">size</span><span class="p">,</span> <span class="n">void</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">void</span> <span class="o">*</span><span class="n">ret</span><span class="p">,</span> <span class="nb">int</span> <span class="n">ordering</span><span class="p">)</span>
+<span class="n">void</span> <span class="n">__atomic_store</span><span class="p">(</span><span class="n">size_t</span> <span class="n">size</span><span class="p">,</span> <span class="n">void</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">void</span> <span class="o">*</span><span class="n">val</span><span class="p">,</span> <span class="nb">int</span> <span class="n">ordering</span><span class="p">)</span>
+<span class="n">void</span> <span class="n">__atomic_exchange</span><span class="p">(</span><span class="n">size_t</span> <span class="n">size</span><span class="p">,</span> <span class="n">void</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">void</span> <span class="o">*</span><span class="n">val</span><span class="p">,</span> <span class="n">void</span> <span class="o">*</span><span class="n">ret</span><span class="p">,</span> <span class="nb">int</span> <span class="n">ordering</span><span class="p">)</span>
+<span class="nb">bool</span> <span class="n">__atomic_compare_exchange</span><span class="p">(</span><span class="n">size_t</span> <span class="n">size</span><span class="p">,</span> <span class="n">void</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">void</span> <span class="o">*</span><span class="n">expected</span><span class="p">,</span> <span class="n">void</span> <span class="o">*</span><span class="n">desired</span><span class="p">,</span> <span class="nb">int</span> <span class="n">success_order</span><span class="p">,</span> <span class="nb">int</span> <span class="n">failure_order</span><span class="p">)</span>
+</pre></div>
+</div>
+<p>There are also size-specialized versions of the above functions, which can only
+be used with <em>naturally-aligned</em> pointers of the appropriate size. In the
+signatures below, âNâ is one of 1, 2, 4, 8, and 16, and âiNâ is the appropriate
+integer type of that size; if no such integer type exists, the specialization
+cannot be used:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">iN</span> <span class="n">__atomic_load_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">,</span> <span class="nb">int</span> <span class="n">ordering</span><span class="p">)</span>
+<span class="n">void</span> <span class="n">__atomic_store_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">,</span> <span class="nb">int</span> <span class="n">ordering</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__atomic_exchange_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">,</span> <span class="nb">int</span> <span class="n">ordering</span><span class="p">)</span>
+<span class="nb">bool</span> <span class="n">__atomic_compare_exchange_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="o">*</span><span class="n">expected</span><span class="p">,</span> <span class="n">iN</span> <span class="n">desired</span><span class="p">,</span> <span class="nb">int</span> <span class="n">success_order</span><span class="p">,</span> <span class="nb">int</span> <span class="n">failure_order</span><span class="p">)</span>
+</pre></div>
+</div>
+<p>Finally there are some read-modify-write functions, which are only available in
+the size-specific variants (any other sizes use a <code class="docutils literal notranslate"><span class="pre">__atomic_compare_exchange</span></code>
+loop):</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">iN</span> <span class="n">__atomic_fetch_add_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">,</span> <span class="nb">int</span> <span class="n">ordering</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__atomic_fetch_sub_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">,</span> <span class="nb">int</span> <span class="n">ordering</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__atomic_fetch_and_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">,</span> <span class="nb">int</span> <span class="n">ordering</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__atomic_fetch_or_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">,</span> <span class="nb">int</span> <span class="n">ordering</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__atomic_fetch_xor_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">,</span> <span class="nb">int</span> <span class="n">ordering</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__atomic_fetch_nand_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">,</span> <span class="nb">int</span> <span class="n">ordering</span><span class="p">)</span>
+</pre></div>
+</div>
+<p>This set of library functions have some interesting implementation requirements
+to take note of:</p>
+<ul class="simple">
+<li>They support all sizes and alignments â including those which cannot be
+implemented natively on any existing hardware. Therefore, they will certainly
+use mutexes in for some sizes/alignments.</li>
+<li>As a consequence, they cannot be shipped in a statically linked
+compiler-support library, as they have state which must be shared amongst all
+DSOs loaded in the program. They must be provided in a shared library used by
+all objects.</li>
+<li>The set of atomic sizes supported lock-free must be a superset of the sizes
+any compiler can emit. That is: if a new compiler introduces support for
+inline-lock-free atomics of size N, the <code class="docutils literal notranslate"><span class="pre">__atomic_*</span></code> functions must also have a
+lock-free implementation for size N. This is a requirement so that code
+produced by an old compiler (which will have called the <code class="docutils literal notranslate"><span class="pre">__atomic_*</span></code> function)
+interoperates with code produced by the new compiler (which will use native
+the atomic instruction).</li>
+</ul>
+<p>Note that itâs possible to write an entirely target-independent implementation
+of these library functions by using the compiler atomic builtins themselves to
+implement the operations on naturally-aligned pointers of supported sizes, and a
+generic mutex implementation otherwise.</p>
+</div>
+<div class="section" id="libcalls-sync">
+<h2><a class="toc-backref" href="#id18">Libcalls: __sync_*</a><a class="headerlink" href="#libcalls-sync" title="Permalink to this headline">¶</a></h2>
+<p>Some targets or OS/target combinations can support lock-free atomics, but for
+various reasons, it is not practical to emit the instructions inline.</p>
+<p>Thereâs two typical examples of this.</p>
+<p>Some CPUs support multiple instruction sets which can be swiched back and forth
+on function-call boundaries. For example, MIPS supports the MIPS16 ISA, which
+has a smaller instruction encoding than the usual MIPS32 ISA. ARM, similarly,
+has the Thumb ISA. In MIPS16 and earlier versions of Thumb, the atomic
+instructions are not encodable. However, those instructions are available via a
+function call to a function with the longer encoding.</p>
+<p>Additionally, a few OS/target pairs provide kernel-supported lock-free
+atomics. ARM/Linux is an example of this: the kernel <a class="reference external" href="https://www.kernel.org/doc/Documentation/arm/kernel_user_helpers.txt">provides</a> a
+function which on older CPUs contains a âmagically-restartableâ atomic sequence
+(which looks atomic so long as thereâs only one CPU), and contains actual atomic
+instructions on newer multicore models. This sort of functionality can typically
+be provided on any architecture, if all CPUs which are missing atomic
+compare-and-swap support are uniprocessor (no SMP). This is almost always the
+case. The only common architecture without that property is SPARC â SPARCV8 SMP
+systems were common, yet it doesnât support any sort of compare-and-swap
+operation.</p>
+<p>In either of these cases, the Target in LLVM can claim support for atomics of an
+appropriate size, and then implement some subset of the operations via libcalls
+to a <code class="docutils literal notranslate"><span class="pre">__sync_*</span></code> function. Such functions <em>must</em> not use locks in their
+implementation, because unlike the <code class="docutils literal notranslate"><span class="pre">__atomic_*</span></code> routines used by
+AtomicExpandPass, these may be mixed-and-matched with native instructions by the
+target lowering.</p>
+<p>Further, these routines do not need to be shared, as they are stateless. So,
+there is no issue with having multiple copies included in one binary. Thus,
+typically these routines are implemented by the statically-linked compiler
+runtime support library.</p>
+<p>LLVM will emit a call to an appropriate <code class="docutils literal notranslate"><span class="pre">__sync_*</span></code> routine if the target
+ISelLowering code has set the corresponding <code class="docutils literal notranslate"><span class="pre">ATOMIC_CMPXCHG</span></code>, <code class="docutils literal notranslate"><span class="pre">ATOMIC_SWAP</span></code>,
+or <code class="docutils literal notranslate"><span class="pre">ATOMIC_LOAD_*</span></code> operation to âExpandâ, and if it has opted-into the
+availability of those library functions via a call to <code class="docutils literal notranslate"><span class="pre">initSyncLibcalls()</span></code>.</p>
+<p>The full set of functions that may be called by LLVM is (for <code class="docutils literal notranslate"><span class="pre">N</span></code> being 1, 2,
+4, 8, or 16):</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">iN</span> <span class="n">__sync_val_compare_and_swap_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">expected</span><span class="p">,</span> <span class="n">iN</span> <span class="n">desired</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__sync_lock_test_and_set_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__sync_fetch_and_add_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__sync_fetch_and_sub_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__sync_fetch_and_and_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__sync_fetch_and_or_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__sync_fetch_and_xor_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__sync_fetch_and_nand_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__sync_fetch_and_max_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__sync_fetch_and_umax_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__sync_fetch_and_min_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">)</span>
+<span class="n">iN</span> <span class="n">__sync_fetch_and_umin_N</span><span class="p">(</span><span class="n">iN</span> <span class="o">*</span><span class="n">ptr</span><span class="p">,</span> <span class="n">iN</span> <span class="n">val</span><span class="p">)</span>
+</pre></div>
+</div>
+<p>This list doesnât include any function for atomic load or store; all known
+architectures support atomic loads and stores directly (possibly by emitting a
+fence on either side of a normal load or store.)</p>
+<p>Thereâs also, somewhat separately, the possibility to lower <code class="docutils literal notranslate"><span class="pre">ATOMIC_FENCE</span></code> to
+<code class="docutils literal notranslate"><span class="pre">__sync_synchronize()</span></code>. This may happen or not happen independent of all the
+above, controlled purely by <code class="docutils literal notranslate"><span class="pre">setOperationAction(ISD::ATOMIC_FENCE,</span> <span class="pre">...)</span></code>.</p>
+</div>
+</div>
+
+
+ </div>
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+ <div class="section" id="benchmarking-tips">
+<h1>Benchmarking tips<a class="headerlink" href="#benchmarking-tips" title="Permalink to this headline">¶</a></h1>
+<div class="section" id="introduction">
+<h2>Introduction<a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
+<p>For benchmarking a patch we want to reduce all possible sources of
+noise as much as possible. How to do that is very OS dependent.</p>
+<p>Note that low noise is required, but not sufficient. It does not
+exclude measurement bias. See
+<a class="reference external" href="https://www.cis.upenn.edu/~cis501/papers/producing-wrong-data.pdf">https://www.cis.upenn.edu/~cis501/papers/producing-wrong-data.pdf</a> for
+example.</p>
+</div>
+<div class="section" id="general">
+<h2>General<a class="headerlink" href="#general" title="Permalink to this headline">¶</a></h2>
+<ul>
+<li><p class="first">Use a high resolution timer, e.g. perf under linux.</p>
+</li>
+<li><p class="first">Run the benchmark multiple times to be able to recognize noise.</p>
+</li>
+<li><p class="first">Disable as many processes or services as possible on the target system.</p>
+</li>
+<li><p class="first">Disable frequency scaling, turbo boost and address space
+randomization (see OS specific section).</p>
+</li>
+<li><p class="first">Static link if the OS supports it. That avoids any variation that
+might be introduced by loading dynamic libraries. This can be done
+by passing <code class="docutils literal notranslate"><span class="pre">-DLLVM_BUILD_STATIC=ON</span></code> to cmake.</p>
+</li>
+<li><p class="first">Try to avoid storage. On some systems you can use tmpfs. Putting the
+program, inputs and outputs on tmpfs avoids touching a real storage
+system, which can have a pretty big variability.</p>
+<p>To mount it (on linux and freebsd at least):</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">mount</span> <span class="o">-</span><span class="n">t</span> <span class="n">tmpfs</span> <span class="o">-</span><span class="n">o</span> <span class="n">size</span><span class="o">=<</span><span class="n">XX</span><span class="o">></span><span class="n">g</span> <span class="n">none</span> <span class="n">dir_to_mount</span>
+</pre></div>
+</div>
+</li>
+</ul>
+</div>
+<div class="section" id="linux">
+<h2>Linux<a class="headerlink" href="#linux" title="Permalink to this headline">¶</a></h2>
+<ul>
+<li><p class="first">Disable address space randomization:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">echo</span> <span class="mi">0</span> <span class="o">></span> <span class="o">/</span><span class="n">proc</span><span class="o">/</span><span class="n">sys</span><span class="o">/</span><span class="n">kernel</span><span class="o">/</span><span class="n">randomize_va_space</span>
+</pre></div>
+</div>
+</li>
+<li><p class="first">Set scaling_governor to performance:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="k">for</span> <span class="n">i</span> <span class="ow">in</span> <span class="o">/</span><span class="n">sys</span><span class="o">/</span><span class="n">devices</span><span class="o">/</span><span class="n">system</span><span class="o">/</span><span class="n">cpu</span><span class="o">/</span><span class="n">cpu</span><span class="o">*/</span><span class="n">cpufreq</span><span class="o">/</span><span class="n">scaling_governor</span>
+<span class="n">do</span>
+ <span class="n">echo</span> <span class="n">performance</span> <span class="o">></span> <span class="o">/</span><span class="n">sys</span><span class="o">/</span><span class="n">devices</span><span class="o">/</span><span class="n">system</span><span class="o">/</span><span class="n">cpu</span><span class="o">/</span><span class="n">cpu</span><span class="o">*/</span><span class="n">cpufreq</span><span class="o">/</span><span class="n">scaling_governor</span>
+<span class="n">done</span>
+</pre></div>
+</div>
+</li>
+<li><p class="first">Use <a class="reference external" href="https://github.com/lpechacek/cpuset">https://github.com/lpechacek/cpuset</a> to reserve cpus for just the
+program you are benchmarking. If using perf, leave at least 2 cores
+so that perf runs in one and your program in another:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">cset</span> <span class="n">shield</span> <span class="o">-</span><span class="n">c</span> <span class="n">N1</span><span class="p">,</span><span class="n">N2</span> <span class="o">-</span><span class="n">k</span> <span class="n">on</span>
+</pre></div>
+</div>
+<p>This will move all threads out of N1 and N2. The <code class="docutils literal notranslate"><span class="pre">-k</span> <span class="pre">on</span></code> means
+that even kernel threads are moved out.</p>
+</li>
+<li><p class="first">Disable the SMT pair of the cpus you will use for the benchmark. The
+pair of cpu N can be found in
+<code class="docutils literal notranslate"><span class="pre">/sys/devices/system/cpu/cpuN/topology/thread_siblings_list</span></code> and
+disabled with:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">echo</span> <span class="mi">0</span> <span class="o">></span> <span class="o">/</span><span class="n">sys</span><span class="o">/</span><span class="n">devices</span><span class="o">/</span><span class="n">system</span><span class="o">/</span><span class="n">cpu</span><span class="o">/</span><span class="n">cpuX</span><span class="o">/</span><span class="n">online</span>
+</pre></div>
+</div>
+</li>
+<li><p class="first">Run the program with:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">cset</span> <span class="n">shield</span> <span class="o">--</span><span class="n">exec</span> <span class="o">--</span> <span class="n">perf</span> <span class="n">stat</span> <span class="o">-</span><span class="n">r</span> <span class="mi">10</span> <span class="o"><</span><span class="n">cmd</span><span class="o">></span>
+</pre></div>
+</div>
+<p>This will run the command after <code class="docutils literal notranslate"><span class="pre">--</span></code> in the isolated cpus. The
+particular perf command runs the <code class="docutils literal notranslate"><span class="pre"><cmd></span></code> 10 times and reports
+statistics.</p>
+</li>
+</ul>
+<p>With these in place you can expect perf variations of less than 0.1%.</p>
+<div class="section" id="linux-intel">
+<h3>Linux Intel<a class="headerlink" href="#linux-intel" title="Permalink to this headline">¶</a></h3>
+<ul>
+<li><p class="first">Disable turbo mode:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">echo</span> <span class="mi">1</span> <span class="o">></span> <span class="o">/</span><span class="n">sys</span><span class="o">/</span><span class="n">devices</span><span class="o">/</span><span class="n">system</span><span class="o">/</span><span class="n">cpu</span><span class="o">/</span><span class="n">intel_pstate</span><span class="o">/</span><span class="n">no_turbo</span>
+</pre></div>
+</div>
+</li>
+</ul>
+</div>
+</div>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
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+ <h3>Navigation</h3>
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+ >index</a></li>
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+ <div class="section" id="using-arm-neon-instructions-in-big-endian-mode">
+<h1>Using ARM NEON instructions in big endian mode<a class="headerlink" href="#using-arm-neon-instructions-in-big-endian-mode" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#introduction" id="id5">Introduction</a><ul>
+<li><a class="reference internal" href="#example-c-level-intrinsics-assembly" id="id6">Example: C-level intrinsics -> assembly</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#problem" id="id7">Problem</a></li>
+<li><a class="reference internal" href="#ldr-and-ld1" id="id8"><code class="docutils literal notranslate"><span class="pre">LDR</span></code> and <code class="docutils literal notranslate"><span class="pre">LD1</span></code></a></li>
+<li><a class="reference internal" href="#considerations" id="id9">Considerations</a><ul>
+<li><a class="reference internal" href="#llvm-ir-lane-ordering" id="id10">LLVM IR Lane ordering</a></li>
+<li><a class="reference internal" href="#aapcs" id="id11">AAPCS</a></li>
+<li><a class="reference internal" href="#alignment" id="id12">Alignment</a></li>
+<li><a class="reference internal" href="#summary" id="id13">Summary</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#implementation" id="id14">Implementation</a><ul>
+<li><a class="reference internal" href="#bitconverts" id="id15">Bitconverts</a></li>
+</ul>
+</li>
+</ul>
+</div>
+<div class="section" id="introduction">
+<h2><a class="toc-backref" href="#id5">Introduction</a><a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
+<p>Generating code for big endian ARM processors is for the most part straightforward. NEON loads and stores however have some interesting properties that make code generation decisions less obvious in big endian mode.</p>
+<p>The aim of this document is to explain the problem with NEON loads and stores, and the solution that has been implemented in LLVM.</p>
+<p>In this document the term âvectorâ refers to what the ARM ABI calls a âshort vectorâ, which is a sequence of items that can fit in a NEON register. This sequence can be 64 or 128 bits in length, and can constitute 8, 16, 32 or 64 bit items. This document refers to A64 instructions throughout, but is almost applicable to the A32/ARMv7 instruction sets also. The ABI format for passing vectors in A32 is sligtly different to A64. Apart from that, the same concepts apply.</p>
+<div class="section" id="example-c-level-intrinsics-assembly">
+<h3><a class="toc-backref" href="#id6">Example: C-level intrinsics -> assembly</a><a class="headerlink" href="#example-c-level-intrinsics-assembly" title="Permalink to this headline">¶</a></h3>
+<p>It may be helpful first to illustrate how C-level ARM NEON intrinsics are lowered to instructions.</p>
+<p>This trivial C function takes a vector of four ints and sets the zeroâth lane to the value â42â:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="c1">#include <arm_neon.h></span>
+<span class="n">int32x4_t</span> <span class="n">f</span><span class="p">(</span><span class="n">int32x4_t</span> <span class="n">p</span><span class="p">)</span> <span class="p">{</span>
+ <span class="k">return</span> <span class="n">vsetq_lane_s32</span><span class="p">(</span><span class="mi">42</span><span class="p">,</span> <span class="n">p</span><span class="p">,</span> <span class="mi">0</span><span class="p">);</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+<p>arm_neon.h intrinsics generate âgenericâ IR where possible (that is, normal IR instructions not <code class="docutils literal notranslate"><span class="pre">llvm.arm.neon.*</span></code> intrinsic calls). The above generates:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">define</span> <span class="o"><</span><span class="mi">4</span> <span class="n">x</span> <span class="n">i32</span><span class="o">></span> <span class="nd">@f</span><span class="p">(</span><span class="o"><</span><span class="mi">4</span> <span class="n">x</span> <span class="n">i32</span><span class="o">></span> <span class="o">%</span><span class="n">p</span><span class="p">)</span> <span class="p">{</span>
+ <span class="o">%</span><span class="n">vset_lane</span> <span class="o">=</span> <span class="n">insertelement</span> <span class="o"><</span><span class="mi">4</span> <span class="n">x</span> <span class="n">i32</span><span class="o">></span> <span class="o">%</span><span class="n">p</span><span class="p">,</span> <span class="n">i32</span> <span class="mi">42</span><span class="p">,</span> <span class="n">i32</span> <span class="mi">0</span>
+ <span class="n">ret</span> <span class="o"><</span><span class="mi">4</span> <span class="n">x</span> <span class="n">i32</span><span class="o">></span> <span class="o">%</span><span class="n">vset_lane</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+<p>Which then becomes the following trivial assembly:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">f</span><span class="p">:</span> <span class="o">//</span> <span class="nd">@f</span>
+ <span class="n">movz</span> <span class="n">w8</span><span class="p">,</span> <span class="c1">#0x2a</span>
+ <span class="n">ins</span> <span class="n">v0</span><span class="o">.</span><span class="n">s</span><span class="p">[</span><span class="mi">0</span><span class="p">],</span> <span class="n">w8</span>
+ <span class="n">ret</span>
+</pre></div>
+</div>
+</div>
+</div>
+<div class="section" id="problem">
+<h2><a class="toc-backref" href="#id7">Problem</a><a class="headerlink" href="#problem" title="Permalink to this headline">¶</a></h2>
+<p>The main problem is how vectors are represented in memory and in registers.</p>
+<p>First, a recap. The âendiannessâ of an item affects its representation in memory only. In a register, a number is just a sequence of bits - 64 bits in the case of AArch64 general purpose registers. Memory, however, is a sequence of addressable units of 8 bits in size. Any number greater than 8 bits must therefore be split up into 8-bit chunks, and endianness describes the order in which these chunks are laid out in memory.</p>
+<p>A âlittle endianâ layout has the least significant byte first (lowest in memory address). A âbig endianâ layout has the <em>most</em> significant byte first. This means that when loading an item from big endian memory, the lowest 8-bits in memory must go in the most significant 8-bits, and so forth.</p>
+</div>
+<div class="section" id="ldr-and-ld1">
+<h2><a class="toc-backref" href="#id8"><code class="docutils literal notranslate"><span class="pre">LDR</span></code> and <code class="docutils literal notranslate"><span class="pre">LD1</span></code></a><a class="headerlink" href="#ldr-and-ld1" title="Permalink to this headline">¶</a></h2>
+<div class="figure align-right" id="id3">
+<img alt="_images/ARM-BE-ldr.png" src="_images/ARM-BE-ldr.png" />
+<p class="caption"><span class="caption-text">Big endian vector load using <code class="docutils literal notranslate"><span class="pre">LDR</span></code>.</span></p>
+</div>
+<p>A vector is a consecutive sequence of items that are operated on simultaneously. To load a 64-bit vector, 64 bits need to be read from memory. In little endian mode, we can do this by just performing a 64-bit load - <code class="docutils literal notranslate"><span class="pre">LDR</span> <span class="pre">q0,</span> <span class="pre">[foo]</span></code>. However if we try this in big endian mode, because of the byte swapping the lane indices end up being swapped! The zeroâth item as laid out in memory becomes the nâth lane in the vector.</p>
+<div class="figure align-right" id="id4">
+<img alt="_images/ARM-BE-ld1.png" src="_images/ARM-BE-ld1.png" />
+<p class="caption"><span class="caption-text">Big endian vector load using <code class="docutils literal notranslate"><span class="pre">LD1</span></code>. Note that the lanes retain the correct ordering.</span></p>
+</div>
+<p>Because of this, the instruction <code class="docutils literal notranslate"><span class="pre">LD1</span></code> performs a vector load but performs byte swapping not on the entire 64 bits, but on the individual items within the vector. This means that the register content is the same as it would have been on a little endian system.</p>
+<p>It may seem that <code class="docutils literal notranslate"><span class="pre">LD1</span></code> should suffice to peform vector loads on a big endian machine. However there are pros and cons to the two approaches that make it less than simple which register format to pick.</p>
+<p>There are two options:</p>
+<blockquote>
+<div><ol class="arabic simple">
+<li>The content of a vector register is the same <em>as if</em> it had been loaded with an <code class="docutils literal notranslate"><span class="pre">LDR</span></code> instruction.</li>
+<li>The content of a vector register is the same <em>as if</em> it had been loaded with an <code class="docutils literal notranslate"><span class="pre">LD1</span></code> instruction.</li>
+</ol>
+</div></blockquote>
+<p>Because <code class="docutils literal notranslate"><span class="pre">LD1</span> <span class="pre">==</span> <span class="pre">LDR</span> <span class="pre">+</span> <span class="pre">REV</span></code> and similarly <code class="docutils literal notranslate"><span class="pre">LDR</span> <span class="pre">==</span> <span class="pre">LD1</span> <span class="pre">+</span> <span class="pre">REV</span></code> (on a big endian system), we can simulate either type of load with the other type of load plus a <code class="docutils literal notranslate"><span class="pre">REV</span></code> instruction. So weâre not deciding which instructions to use, but which format to use (which will then influence which instruction is best to use).</p>
+<div class="clearer docutils container">
+Note that throughout this section we only mention loads. Stores have exactly the same problems as their associated loads, so have been skipped for brevity.</div>
+</div>
+<div class="section" id="considerations">
+<h2><a class="toc-backref" href="#id9">Considerations</a><a class="headerlink" href="#considerations" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="llvm-ir-lane-ordering">
+<h3><a class="toc-backref" href="#id10">LLVM IR Lane ordering</a><a class="headerlink" href="#llvm-ir-lane-ordering" title="Permalink to this headline">¶</a></h3>
+<p>LLVM IR has first class vector types. In LLVM IR, the zeroâth element of a vector resides at the lowest memory address. The optimizer relies on this property in certain areas, for example when concatenating vectors together. The intention is for arrays and vectors to have identical memory layouts - <code class="docutils literal notranslate"><span class="pre">[4</span> <span class="pre">x</span> <span class="pre">i8]</span></code> and <code class="docutils literal notranslate"><span class="pre"><4</span> <span class="pre">x</span> <span class="pre">i8></span></code> should be represented the same in memory. Without this property there would be many special cases that the optimizer would have to cleverly handle.</p>
+<p>Use of <code class="docutils literal notranslate"><span class="pre">LDR</span></code> would break this lane ordering property. This doesnât preclude the use of <code class="docutils literal notranslate"><span class="pre">LDR</span></code>, but we would have to do one of two things:</p>
+<blockquote>
+<div><ol class="arabic simple">
+<li>Insert a <code class="docutils literal notranslate"><span class="pre">REV</span></code> instruction to reverse the lane order after every <code class="docutils literal notranslate"><span class="pre">LDR</span></code>.</li>
+<li>Disable all optimizations that rely on lane layout, and for every access to an individual lane (<code class="docutils literal notranslate"><span class="pre">insertelement</span></code>/<code class="docutils literal notranslate"><span class="pre">extractelement</span></code>/<code class="docutils literal notranslate"><span class="pre">shufflevector</span></code>) reverse the lane index.</li>
+</ol>
+</div></blockquote>
+</div>
+<div class="section" id="aapcs">
+<h3><a class="toc-backref" href="#id11">AAPCS</a><a class="headerlink" href="#aapcs" title="Permalink to this headline">¶</a></h3>
+<p>The ARM procedure call standard (AAPCS) defines the ABI for passing vectors between functions in registers. It states:</p>
+<blockquote>
+<div><p>When a short vector is transferred between registers and memory it is treated as an opaque object. That is a short vector is stored in memory as if it were stored with a single <code class="docutils literal notranslate"><span class="pre">STR</span></code> of the entire register; a short vector is loaded from memory using the corresponding <code class="docutils literal notranslate"><span class="pre">LDR</span></code> instruction. On a little-endian system this means that element 0 will always contain the lowest addressed element of a short vector; on a big-endian system element 0 will contain the highest-addressed element of a short vector.</p>
+<p class="attribution">—Procedure Call Standard for the ARM 64-bit Architecture (AArch64), 4.1.2 Short Vectors</p>
+</div></blockquote>
+<p>The use of <code class="docutils literal notranslate"><span class="pre">LDR</span></code> and <code class="docutils literal notranslate"><span class="pre">STR</span></code> as the ABI defines has at least one advantage over <code class="docutils literal notranslate"><span class="pre">LD1</span></code> and <code class="docutils literal notranslate"><span class="pre">ST1</span></code>. <code class="docutils literal notranslate"><span class="pre">LDR</span></code> and <code class="docutils literal notranslate"><span class="pre">STR</span></code> are oblivious to the size of the individual lanes of a vector. <code class="docutils literal notranslate"><span class="pre">LD1</span></code> and <code class="docutils literal notranslate"><span class="pre">ST1</span></code> are not - the lane size is encoded within them. This is important across an ABI boundary, because it would become necessary to know the lane width the callee expects. Consider the following code:</p>
+<div class="highlight-c notranslate"><div class="highlight"><pre><span></span><span class="o"><</span><span class="n">callee</span><span class="p">.</span><span class="n">c</span><span class="o">></span>
+<span class="kt">void</span> <span class="n">callee</span><span class="p">(</span><span class="n">uint32x2_t</span> <span class="n">v</span><span class="p">)</span> <span class="p">{</span>
+ <span class="p">...</span>
+<span class="p">}</span>
+
+<span class="o"><</span><span class="n">caller</span><span class="p">.</span><span class="n">c</span><span class="o">></span>
+<span class="k">extern</span> <span class="kt">void</span> <span class="n">callee</span><span class="p">(</span><span class="n">uint32x2_t</span><span class="p">);</span>
+<span class="kt">void</span> <span class="nf">caller</span><span class="p">()</span> <span class="p">{</span>
+ <span class="n">callee</span><span class="p">(...);</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+<p>If <code class="docutils literal notranslate"><span class="pre">callee</span></code> changed its signature to <code class="docutils literal notranslate"><span class="pre">uint16x4_t</span></code>, which is equivalent in register content, if we passed as <code class="docutils literal notranslate"><span class="pre">LD1</span></code> weâd break this code until <code class="docutils literal notranslate"><span class="pre">caller</span></code> was updated and recompiled.</p>
+<p>There is an argument that if the signatures of the two functions are different then the behaviour should be undefined. But there may be functions that are agnostic to the lane layout of the vector, and treating the vector as an opaque value (just loading it and storing it) would be impossible without a common format across ABI boundaries.</p>
+<p>So to preserve ABI compatibility, we need to use the <code class="docutils literal notranslate"><span class="pre">LDR</span></code> lane layout across function calls.</p>
+</div>
+<div class="section" id="alignment">
+<h3><a class="toc-backref" href="#id12">Alignment</a><a class="headerlink" href="#alignment" title="Permalink to this headline">¶</a></h3>
+<p>In strict alignment mode, <code class="docutils literal notranslate"><span class="pre">LDR</span> <span class="pre">qX</span></code> requires its address to be 128-bit aligned, whereas <code class="docutils literal notranslate"><span class="pre">LD1</span></code> only requires it to be as aligned as the lane size. If we canonicalised on using <code class="docutils literal notranslate"><span class="pre">LDR</span></code>, weâd still need to use <code class="docutils literal notranslate"><span class="pre">LD1</span></code> in some places to avoid alignment faults (the result of the <code class="docutils literal notranslate"><span class="pre">LD1</span></code> would then need to be reversed with <code class="docutils literal notranslate"><span class="pre">REV</span></code>).</p>
+<p>Most operating systems however do not run with alignment faults enabled, so this is often not an issue.</p>
+</div>
+<div class="section" id="summary">
+<h3><a class="toc-backref" href="#id13">Summary</a><a class="headerlink" href="#summary" title="Permalink to this headline">¶</a></h3>
+<p>The following table summarises the instructions that are required to be emitted for each property mentioned above for each of the two solutions.</p>
+<table border="1" class="docutils">
+<colgroup>
+<col width="37%" />
+<col width="37%" />
+<col width="25%" />
+</colgroup>
+<thead valign="bottom">
+<tr class="row-odd"><th class="head"> </th>
+<th class="head"><code class="docutils literal notranslate"><span class="pre">LDR</span></code> layout</th>
+<th class="head"><code class="docutils literal notranslate"><span class="pre">LD1</span></code> layout</th>
+</tr>
+</thead>
+<tbody valign="top">
+<tr class="row-even"><td>Lane ordering</td>
+<td><code class="docutils literal notranslate"><span class="pre">LDR</span> <span class="pre">+</span> <span class="pre">REV</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">LD1</span></code></td>
+</tr>
+<tr class="row-odd"><td>AAPCS</td>
+<td><code class="docutils literal notranslate"><span class="pre">LDR</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">LD1</span> <span class="pre">+</span> <span class="pre">REV</span></code></td>
+</tr>
+<tr class="row-even"><td>Alignment for strict mode</td>
+<td><code class="docutils literal notranslate"><span class="pre">LDR</span></code> / <code class="docutils literal notranslate"><span class="pre">LD1</span> <span class="pre">+</span> <span class="pre">REV</span></code></td>
+<td><code class="docutils literal notranslate"><span class="pre">LD1</span></code></td>
+</tr>
+</tbody>
+</table>
+<p>Neither approach is perfect, and choosing one boils down to choosing the lesser of two evils. The issue with lane ordering, it was decided, would have to change target-agnostic compiler passes and would result in a strange IR in which lane indices were reversed. It was decided that this was worse than the changes that would have to be made to support <code class="docutils literal notranslate"><span class="pre">LD1</span></code>, so <code class="docutils literal notranslate"><span class="pre">LD1</span></code> was chosen as the canonical vector load instruction (and by inference, <code class="docutils literal notranslate"><span class="pre">ST1</span></code> for vector stores).</p>
+</div>
+</div>
+<div class="section" id="implementation">
+<h2><a class="toc-backref" href="#id14">Implementation</a><a class="headerlink" href="#implementation" title="Permalink to this headline">¶</a></h2>
+<p>There are 3 parts to the implementation:</p>
+<blockquote>
+<div><ol class="arabic simple">
+<li>Predicate <code class="docutils literal notranslate"><span class="pre">LDR</span></code> and <code class="docutils literal notranslate"><span class="pre">STR</span></code> instructions so that they are never allowed to be selected to generate vector loads and stores. The exception is one-lane vectors <a class="footnote-reference" href="#id2" id="id1">[1]</a> - these by definition cannot have lane ordering problems so are fine to use <code class="docutils literal notranslate"><span class="pre">LDR</span></code>/<code class="docutils literal notranslate"><span class="pre">STR</span></code>.</li>
+<li>Create code generation patterns for bitconverts that create <code class="docutils literal notranslate"><span class="pre">REV</span></code> instructions.</li>
+<li>Make sure appropriate bitconverts are created so that vector values get passed over call boundaries as 1-element vectors (which is the same as if they were loaded with <code class="docutils literal notranslate"><span class="pre">LDR</span></code>).</li>
+</ol>
+</div></blockquote>
+<div class="section" id="bitconverts">
+<h3><a class="toc-backref" href="#id15">Bitconverts</a><a class="headerlink" href="#bitconverts" title="Permalink to this headline">¶</a></h3>
+<img alt="_images/ARM-BE-bitcastfail.png" class="align-right" src="_images/ARM-BE-bitcastfail.png" />
+<p>The main problem with the <code class="docutils literal notranslate"><span class="pre">LD1</span></code> solution is dealing with bitconverts (or bitcasts, or reinterpret casts). These are pseudo instructions that only change the compilerâs interpretation of data, not the underlying data itself. A requirement is that if data is loaded and then saved again (called a âround tripâ), the memory contents should be the same after the store as before the load. If a vector is loaded and is then bitconverted to a different vector type before storing, the round trip will currently be broken.</p>
+<p>Take for example this code sequence:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">%</span><span class="mi">0</span> <span class="o">=</span> <span class="n">load</span> <span class="o"><</span><span class="mi">4</span> <span class="n">x</span> <span class="n">i32</span><span class="o">></span> <span class="o">%</span><span class="n">x</span>
+<span class="o">%</span><span class="mi">1</span> <span class="o">=</span> <span class="n">bitcast</span> <span class="o"><</span><span class="mi">4</span> <span class="n">x</span> <span class="n">i32</span><span class="o">></span> <span class="o">%</span><span class="mi">0</span> <span class="n">to</span> <span class="o"><</span><span class="mi">2</span> <span class="n">x</span> <span class="n">i64</span><span class="o">></span>
+ <span class="n">store</span> <span class="o"><</span><span class="mi">2</span> <span class="n">x</span> <span class="n">i64</span><span class="o">></span> <span class="o">%</span><span class="mi">1</span><span class="p">,</span> <span class="o"><</span><span class="mi">2</span> <span class="n">x</span> <span class="n">i64</span><span class="o">>*</span> <span class="o">%</span><span class="n">y</span>
+</pre></div>
+</div>
+<p>This would produce a code sequence such as that in the figure on the right. The mismatched <code class="docutils literal notranslate"><span class="pre">LD1</span></code> and <code class="docutils literal notranslate"><span class="pre">ST1</span></code> cause the stored data to differ from the loaded data.</p>
+<div class="clearer docutils container">
+When we see a bitcast from type <code class="docutils literal notranslate"><span class="pre">X</span></code> to type <code class="docutils literal notranslate"><span class="pre">Y</span></code>, what we need to do is to change the in-register representation of the data to be <em>as if</em> it had just been loaded by a <code class="docutils literal notranslate"><span class="pre">LD1</span></code> of type <code class="docutils literal notranslate"><span class="pre">Y</span></code>.</div>
+<img alt="_images/ARM-BE-bitcastsuccess.png" class="align-right" src="_images/ARM-BE-bitcastsuccess.png" />
+<p>Conceptually this is simple - we can insert a <code class="docutils literal notranslate"><span class="pre">REV</span></code> undoing the <code class="docutils literal notranslate"><span class="pre">LD1</span></code> of type <code class="docutils literal notranslate"><span class="pre">X</span></code> (converting the in-register representation to the same as if it had been loaded by <code class="docutils literal notranslate"><span class="pre">LDR</span></code>) and then insert another <code class="docutils literal notranslate"><span class="pre">REV</span></code> to change the representation to be as if it had been loaded by an <code class="docutils literal notranslate"><span class="pre">LD1</span></code> of type <code class="docutils literal notranslate"><span class="pre">Y</span></code>.</p>
+<p>For the previous example, this would be:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">LD1</span> <span class="n">v0</span><span class="o">.</span><span class="mi">4</span><span class="n">s</span><span class="p">,</span> <span class="p">[</span><span class="n">x</span><span class="p">]</span>
+
+<span class="n">REV64</span> <span class="n">v0</span><span class="o">.</span><span class="mi">4</span><span class="n">s</span><span class="p">,</span> <span class="n">v0</span><span class="o">.</span><span class="mi">4</span><span class="n">s</span> <span class="o">//</span> <span class="n">There</span> <span class="ow">is</span> <span class="n">no</span> <span class="n">REV128</span> <span class="n">instruction</span><span class="p">,</span> <span class="n">so</span> <span class="n">it</span> <span class="n">must</span> <span class="n">be</span> <span class="n">synthesizedcd</span>
+<span class="n">EXT</span> <span class="n">v0</span><span class="o">.</span><span class="mi">16</span><span class="n">b</span><span class="p">,</span> <span class="n">v0</span><span class="o">.</span><span class="mi">16</span><span class="n">b</span><span class="p">,</span> <span class="n">v0</span><span class="o">.</span><span class="mi">16</span><span class="n">b</span><span class="p">,</span> <span class="c1">#8 // with a REV64 then an EXT to swap the two 64-bit elements.</span>
+
+<span class="n">REV64</span> <span class="n">v0</span><span class="o">.</span><span class="mi">2</span><span class="n">d</span><span class="p">,</span> <span class="n">v0</span><span class="o">.</span><span class="mi">2</span><span class="n">d</span>
+<span class="n">EXT</span> <span class="n">v0</span><span class="o">.</span><span class="mi">16</span><span class="n">b</span><span class="p">,</span> <span class="n">v0</span><span class="o">.</span><span class="mi">16</span><span class="n">b</span><span class="p">,</span> <span class="n">v0</span><span class="o">.</span><span class="mi">16</span><span class="n">b</span><span class="p">,</span> <span class="c1">#8</span>
+
+<span class="n">ST1</span> <span class="n">v0</span><span class="o">.</span><span class="mi">2</span><span class="n">d</span><span class="p">,</span> <span class="p">[</span><span class="n">y</span><span class="p">]</span>
+</pre></div>
+</div>
+<p>It turns out that these <code class="docutils literal notranslate"><span class="pre">REV</span></code> pairs can, in almost all cases, be squashed together into a single <code class="docutils literal notranslate"><span class="pre">REV</span></code>. For the example above, a <code class="docutils literal notranslate"><span class="pre">REV128</span> <span class="pre">4s</span></code> + <code class="docutils literal notranslate"><span class="pre">REV128</span> <span class="pre">2d</span></code> is actually a <code class="docutils literal notranslate"><span class="pre">REV64</span> <span class="pre">4s</span></code>, as shown in the figure on the right.</p>
+<table class="docutils footnote" frame="void" id="id2" rules="none">
+<colgroup><col class="label" /><col /></colgroup>
+<tbody valign="top">
+<tr><td class="label"><a class="fn-backref" href="#id1">[1]</a></td><td>One lane vectors may seem useless as a concept but they serve to distinguish between values held in general purpose registers and values held in NEON/VFP registers. For example, an <code class="docutils literal notranslate"><span class="pre">i64</span></code> would live in an <code class="docutils literal notranslate"><span class="pre">x</span></code> register, but <code class="docutils literal notranslate"><span class="pre"><1</span> <span class="pre">x</span> <span class="pre">i64></span></code> would live in a <code class="docutils literal notranslate"><span class="pre">d</span></code> register.</td></tr>
+</tbody>
+</table>
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+ <div class="section" id="llvm-bitcode-file-format">
+<h1>LLVM Bitcode File Format<a class="headerlink" href="#llvm-bitcode-file-format" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#abstract" id="id9">Abstract</a></li>
+<li><a class="reference internal" href="#overview" id="id10">Overview</a></li>
+<li><a class="reference internal" href="#bitstream-format" id="id11">Bitstream Format</a><ul>
+<li><a class="reference internal" href="#magic-numbers" id="id12">Magic Numbers</a></li>
+<li><a class="reference internal" href="#primitives" id="id13">Primitives</a><ul>
+<li><a class="reference internal" href="#fixed-width-value" id="id14">Fixed Width Integers</a></li>
+<li><a class="reference internal" href="#variable-width-value" id="id15">Variable Width Integers</a></li>
+<li><a class="reference internal" href="#bit-characters" id="id16">6-bit characters</a></li>
+<li><a class="reference internal" href="#word-alignment" id="id17">Word Alignment</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#abbreviation-ids" id="id18">Abbreviation IDs</a></li>
+<li><a class="reference internal" href="#blocks" id="id19">Blocks</a><ul>
+<li><a class="reference internal" href="#enter-subblock-encoding" id="id20">ENTER_SUBBLOCK Encoding</a></li>
+<li><a class="reference internal" href="#end-block-encoding" id="id21">END_BLOCK Encoding</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#data-records" id="id22">Data Records</a><ul>
+<li><a class="reference internal" href="#unabbrev-record-encoding" id="id23">UNABBREV_RECORD Encoding</a></li>
+<li><a class="reference internal" href="#abbreviated-record-encoding" id="id24">Abbreviated Record Encoding</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#abbreviations" id="id25">Abbreviations</a><ul>
+<li><a class="reference internal" href="#define-abbrev-encoding" id="id26">DEFINE_ABBREV Encoding</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#standard-block" id="id27">Standard Blocks</a><ul>
+<li><a class="reference internal" href="#blockinfo-block" id="id28">#0 - BLOCKINFO Block</a></li>
+</ul>
+</li>
+</ul>
+</li>
+<li><a class="reference internal" href="#bitcode-wrapper-format" id="id29">Bitcode Wrapper Format</a></li>
+<li><a class="reference internal" href="#native-object-file-wrapper-format" id="id30">Native Object File Wrapper Format</a></li>
+<li><a class="reference internal" href="#llvm-ir-encoding" id="id31">LLVM IR Encoding</a><ul>
+<li><a class="reference internal" href="#basics" id="id32">Basics</a><ul>
+<li><a class="reference internal" href="#llvm-ir-magic-number" id="id33">LLVM IR Magic Number</a></li>
+<li><a class="reference internal" href="#signed-vbrs" id="id34">Signed VBRs</a></li>
+<li><a class="reference internal" href="#llvm-ir-blocks" id="id35">LLVM IR Blocks</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#module-block-contents" id="id36">MODULE_BLOCK Contents</a><ul>
+<li><a class="reference internal" href="#module-code-version-record" id="id37">MODULE_CODE_VERSION Record</a></li>
+<li><a class="reference internal" href="#module-code-triple-record" id="id38">MODULE_CODE_TRIPLE Record</a></li>
+<li><a class="reference internal" href="#module-code-datalayout-record" id="id39">MODULE_CODE_DATALAYOUT Record</a></li>
+<li><a class="reference internal" href="#module-code-asm-record" id="id40">MODULE_CODE_ASM Record</a></li>
+<li><a class="reference internal" href="#module-code-sectionname-record" id="id41">MODULE_CODE_SECTIONNAME Record</a></li>
+<li><a class="reference internal" href="#module-code-deplib-record" id="id42">MODULE_CODE_DEPLIB Record</a></li>
+<li><a class="reference internal" href="#module-code-globalvar-record" id="id43">MODULE_CODE_GLOBALVAR Record</a></li>
+<li><a class="reference internal" href="#module-code-function-record" id="id44">MODULE_CODE_FUNCTION Record</a></li>
+<li><a class="reference internal" href="#module-code-alias-record" id="id45">MODULE_CODE_ALIAS Record</a></li>
+<li><a class="reference internal" href="#module-code-gcname-record" id="id46">MODULE_CODE_GCNAME Record</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#paramattr-block-contents" id="id47">PARAMATTR_BLOCK Contents</a><ul>
+<li><a class="reference internal" href="#paramattr-code-entry-record" id="id48">PARAMATTR_CODE_ENTRY Record</a></li>
+<li><a class="reference internal" href="#paramattr-code-entry-old-record" id="id49">PARAMATTR_CODE_ENTRY_OLD Record</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#paramattr-group-block-contents" id="id50">PARAMATTR_GROUP_BLOCK Contents</a><ul>
+<li><a class="reference internal" href="#paramattr-grp-code-entry-record" id="id51">PARAMATTR_GRP_CODE_ENTRY Record</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#type-block-contents" id="id52">TYPE_BLOCK Contents</a><ul>
+<li><a class="reference internal" href="#type-code-numentry-record" id="id53">TYPE_CODE_NUMENTRY Record</a></li>
+<li><a class="reference internal" href="#type-code-void-record" id="id54">TYPE_CODE_VOID Record</a></li>
+<li><a class="reference internal" href="#type-code-half-record" id="id55">TYPE_CODE_HALF Record</a></li>
+<li><a class="reference internal" href="#type-code-float-record" id="id56">TYPE_CODE_FLOAT Record</a></li>
+<li><a class="reference internal" href="#type-code-double-record" id="id57">TYPE_CODE_DOUBLE Record</a></li>
+<li><a class="reference internal" href="#type-code-label-record" id="id58">TYPE_CODE_LABEL Record</a></li>
+<li><a class="reference internal" href="#type-code-opaque-record" id="id59">TYPE_CODE_OPAQUE Record</a></li>
+<li><a class="reference internal" href="#type-code-integer-record" id="id60">TYPE_CODE_INTEGER Record</a></li>
+<li><a class="reference internal" href="#type-code-pointer-record" id="id61">TYPE_CODE_POINTER Record</a></li>
+<li><a class="reference internal" href="#type-code-function-old-record" id="id62">TYPE_CODE_FUNCTION_OLD Record</a></li>
+<li><a class="reference internal" href="#type-code-array-record" id="id63">TYPE_CODE_ARRAY Record</a></li>
+<li><a class="reference internal" href="#type-code-vector-record" id="id64">TYPE_CODE_VECTOR Record</a></li>
+<li><a class="reference internal" href="#type-code-x86-fp80-record" id="id65">TYPE_CODE_X86_FP80 Record</a></li>
+<li><a class="reference internal" href="#type-code-fp128-record" id="id66">TYPE_CODE_FP128 Record</a></li>
+<li><a class="reference internal" href="#type-code-ppc-fp128-record" id="id67">TYPE_CODE_PPC_FP128 Record</a></li>
+<li><a class="reference internal" href="#type-code-metadata-record" id="id68">TYPE_CODE_METADATA Record</a></li>
+<li><a class="reference internal" href="#type-code-x86-mmx-record" id="id69">TYPE_CODE_X86_MMX Record</a></li>
+<li><a class="reference internal" href="#type-code-struct-anon-record" id="id70">TYPE_CODE_STRUCT_ANON Record</a></li>
+<li><a class="reference internal" href="#type-code-struct-name-record" id="id71">TYPE_CODE_STRUCT_NAME Record</a></li>
+<li><a class="reference internal" href="#type-code-struct-named-record" id="id72">TYPE_CODE_STRUCT_NAMED Record</a></li>
+<li><a class="reference internal" href="#type-code-function-record" id="id73">TYPE_CODE_FUNCTION Record</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#constants-block-contents" id="id74">CONSTANTS_BLOCK Contents</a></li>
+<li><a class="reference internal" href="#function-block-contents" id="id75">FUNCTION_BLOCK Contents</a></li>
+<li><a class="reference internal" href="#value-symtab-block-contents" id="id76">VALUE_SYMTAB_BLOCK Contents</a></li>
+<li><a class="reference internal" href="#metadata-block-contents" id="id77">METADATA_BLOCK Contents</a></li>
+<li><a class="reference internal" href="#metadata-attachment-contents" id="id78">METADATA_ATTACHMENT Contents</a></li>
+<li><a class="reference internal" href="#strtab-block-contents" id="id79">STRTAB_BLOCK Contents</a></li>
+</ul>
+</li>
+</ul>
+</div>
+<div class="section" id="abstract">
+<h2><a class="toc-backref" href="#id9">Abstract</a><a class="headerlink" href="#abstract" title="Permalink to this headline">¶</a></h2>
+<p>This document describes the LLVM bitstream file format and the encoding of the
+LLVM IR into it.</p>
+</div>
+<div class="section" id="overview">
+<h2><a class="toc-backref" href="#id10">Overview</a><a class="headerlink" href="#overview" title="Permalink to this headline">¶</a></h2>
+<p>What is commonly known as the LLVM bitcode file format (also, sometimes
+anachronistically known as bytecode) is actually two things: a <a class="reference internal" href="#bitstream-container-format">bitstream
+container format</a> and an <a class="reference internal" href="#encoding-of-llvm-ir">encoding of LLVM IR</a> into the container format.</p>
+<p>The bitstream format is an abstract encoding of structured data, very similar to
+XML in some ways. Like XML, bitstream files contain tags, and nested
+structures, and you can parse the file without having to understand the tags.
+Unlike XML, the bitstream format is a binary encoding, and unlike XML it
+provides a mechanism for the file to self-describe âabbreviationsâ, which are
+effectively size optimizations for the content.</p>
+<p>LLVM IR files may be optionally embedded into a <a class="reference internal" href="#wrapper">wrapper</a> structure, or in a
+<a class="reference internal" href="#native-object-file">native object file</a>. Both of these mechanisms make it easy to embed extra
+data along with LLVM IR files.</p>
+<p>This document first describes the LLVM bitstream format, describes the wrapper
+format, then describes the record structure used by LLVM IR files.</p>
+</div>
+<div class="section" id="bitstream-format">
+<span id="bitstream-container-format"></span><h2><a class="toc-backref" href="#id11">Bitstream Format</a><a class="headerlink" href="#bitstream-format" title="Permalink to this headline">¶</a></h2>
+<p>The bitstream format is literally a stream of bits, with a very simple
+structure. This structure consists of the following concepts:</p>
+<ul class="simple">
+<li>A â<a class="reference internal" href="#magic-number">magic number</a>â that identifies the contents of the stream.</li>
+<li>Encoding <a class="reference internal" href="#primitives">primitives</a> like variable bit-rate integers.</li>
+<li><a class="reference internal" href="#blocks">Blocks</a>, which define nested content.</li>
+<li><a class="reference internal" href="#data-records">Data Records</a>, which describe entities within the file.</li>
+<li>Abbreviations, which specify compression optimizations for the file.</li>
+</ul>
+<p>Note that the <a class="reference internal" href="CommandGuide/llvm-bcanalyzer.html"><span class="doc">llvm-bcanalyzer</span></a> tool can be
+used to dump and inspect arbitrary bitstreams, which is very useful for
+understanding the encoding.</p>
+<div class="section" id="magic-numbers">
+<span id="magic-number"></span><h3><a class="toc-backref" href="#id12">Magic Numbers</a><a class="headerlink" href="#magic-numbers" title="Permalink to this headline">¶</a></h3>
+<p>The first four bytes of a bitstream are used as an application-specific magic
+number. Generic bitcode tools may look at the first four bytes to determine
+whether the stream is a known stream type. However, these tools should <em>not</em>
+determine whether a bitstream is valid based on its magic number alone. New
+application-specific bitstream formats are being developed all the time; tools
+should not reject them just because they have a hitherto unseen magic number.</p>
+</div>
+<div class="section" id="primitives">
+<span id="id1"></span><h3><a class="toc-backref" href="#id13">Primitives</a><a class="headerlink" href="#primitives" title="Permalink to this headline">¶</a></h3>
+<p>A bitstream literally consists of a stream of bits, which are read in order
+starting with the least significant bit of each byte. The stream is made up of
+a number of primitive values that encode a stream of unsigned integer values.
+These integers are encoded in two ways: either as <a class="reference internal" href="#fixed-width-integers">Fixed Width Integers</a> or as
+<a class="reference internal" href="#variable-width-integers">Variable Width Integers</a>.</p>
+<div class="section" id="fixed-width-value">
+<span id="fixed-width-integers"></span><span id="id2"></span><h4><a class="toc-backref" href="#id14">Fixed Width Integers</a><a class="headerlink" href="#fixed-width-value" title="Permalink to this headline">¶</a></h4>
+<p>Fixed-width integer values have their low bits emitted directly to the file.
+For example, a 3-bit integer value encodes 1 as 001. Fixed width integers are
+used when there are a well-known number of options for a field. For example,
+boolean values are usually encoded with a 1-bit wide integer.</p>
+</div>
+<div class="section" id="variable-width-value">
+<span id="variable-width-integer"></span><span id="variable-width-integers"></span><span id="id3"></span><h4><a class="toc-backref" href="#id15">Variable Width Integers</a><a class="headerlink" href="#variable-width-value" title="Permalink to this headline">¶</a></h4>
+<p>Variable-width integer (VBR) values encode values of arbitrary size, optimizing
+for the case where the values are small. Given a 4-bit VBR field, any 3-bit
+value (0 through 7) is encoded directly, with the high bit set to zero. Values
+larger than N-1 bits emit their bits in a series of N-1 bit chunks, where all
+but the last set the high bit.</p>
+<p>For example, the value 27 (0x1B) is encoded as 1011 0011 when emitted as a vbr4
+value. The first set of four bits indicates the value 3 (011) with a
+continuation piece (indicated by a high bit of 1). The next word indicates a
+value of 24 (011 << 3) with no continuation. The sum (3+24) yields the value
+27.</p>
+</div>
+<div class="section" id="bit-characters">
+<span id="char6-encoded-value"></span><h4><a class="toc-backref" href="#id16">6-bit characters</a><a class="headerlink" href="#bit-characters" title="Permalink to this headline">¶</a></h4>
+<p>6-bit characters encode common characters into a fixed 6-bit field. They
+represent the following characters with the following 6-bit values:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="s1">'a'</span> <span class="o">..</span> <span class="s1">'z'</span> <span class="o">---</span> <span class="mi">0</span> <span class="o">..</span> <span class="mi">25</span>
+<span class="s1">'A'</span> <span class="o">..</span> <span class="s1">'Z'</span> <span class="o">---</span> <span class="mi">26</span> <span class="o">..</span> <span class="mi">51</span>
+<span class="s1">'0'</span> <span class="o">..</span> <span class="s1">'9'</span> <span class="o">---</span> <span class="mi">52</span> <span class="o">..</span> <span class="mi">61</span>
+ <span class="s1">'.'</span> <span class="o">---</span> <span class="mi">62</span>
+ <span class="s1">'_'</span> <span class="o">---</span> <span class="mi">63</span>
+</pre></div>
+</div>
+<p>This encoding is only suitable for encoding characters and strings that consist
+only of the above characters. It is completely incapable of encoding characters
+not in the set.</p>
+</div>
+<div class="section" id="word-alignment">
+<h4><a class="toc-backref" href="#id17">Word Alignment</a><a class="headerlink" href="#word-alignment" title="Permalink to this headline">¶</a></h4>
+<p>Occasionally, it is useful to emit zero bits until the bitstream is a multiple
+of 32 bits. This ensures that the bit position in the stream can be represented
+as a multiple of 32-bit words.</p>
+</div>
+</div>
+<div class="section" id="abbreviation-ids">
+<h3><a class="toc-backref" href="#id18">Abbreviation IDs</a><a class="headerlink" href="#abbreviation-ids" title="Permalink to this headline">¶</a></h3>
+<p>A bitstream is a sequential series of <a class="reference internal" href="#blocks">Blocks</a> and <a class="reference internal" href="#data-records">Data Records</a>. Both of
+these start with an abbreviation ID encoded as a fixed-bitwidth field. The
+width is specified by the current block, as described below. The value of the
+abbreviation ID specifies either a builtin ID (which have special meanings,
+defined below) or one of the abbreviation IDs defined for the current block by
+the stream itself.</p>
+<p>The set of builtin abbrev IDs is:</p>
+<ul class="simple">
+<li>0 - <a class="reference internal" href="#end-block">END_BLOCK</a> â This abbrev ID marks the end of the current block.</li>
+<li>1 - <a class="reference internal" href="#enter-subblock">ENTER_SUBBLOCK</a> â This abbrev ID marks the beginning of a new
+block.</li>
+<li>2 - <a class="reference internal" href="#define-abbrev">DEFINE_ABBREV</a> â This defines a new abbreviation.</li>
+<li>3 - <a class="reference internal" href="#unabbrev-record">UNABBREV_RECORD</a> â This ID specifies the definition of an
+unabbreviated record.</li>
+</ul>
+<p>Abbreviation IDs 4 and above are defined by the stream itself, and specify an
+<a class="reference internal" href="#abbreviated-record-encoding">abbreviated record encoding</a>.</p>
+</div>
+<div class="section" id="blocks">
+<span id="id4"></span><h3><a class="toc-backref" href="#id19">Blocks</a><a class="headerlink" href="#blocks" title="Permalink to this headline">¶</a></h3>
+<p>Blocks in a bitstream denote nested regions of the stream, and are identified by
+a content-specific id number (for example, LLVM IR uses an ID of 12 to represent
+function bodies). Block IDs 0-7 are reserved for <a class="reference internal" href="#standard-blocks">standard blocks</a> whose
+meaning is defined by Bitcode; block IDs 8 and greater are application
+specific. Nested blocks capture the hierarchical structure of the data encoded
+in it, and various properties are associated with blocks as the file is parsed.
+Block definitions allow the reader to efficiently skip blocks in constant time
+if the reader wants a summary of blocks, or if it wants to efficiently skip data
+it does not understand. The LLVM IR reader uses this mechanism to skip function
+bodies, lazily reading them on demand.</p>
+<p>When reading and encoding the stream, several properties are maintained for the
+block. In particular, each block maintains:</p>
+<ol class="arabic simple">
+<li>A current abbrev id width. This value starts at 2 at the beginning of the
+stream, and is set every time a block record is entered. The block entry
+specifies the abbrev id width for the body of the block.</li>
+<li>A set of abbreviations. Abbreviations may be defined within a block, in
+which case they are only defined in that block (neither subblocks nor
+enclosing blocks see the abbreviation). Abbreviations can also be defined
+inside a <a class="reference internal" href="#blockinfo">BLOCKINFO</a> block, in which case they are defined in all blocks
+that match the ID that the <code class="docutils literal notranslate"><span class="pre">BLOCKINFO</span></code> block is describing.</li>
+</ol>
+<p>As sub blocks are entered, these properties are saved and the new sub-block has
+its own set of abbreviations, and its own abbrev id width. When a sub-block is
+popped, the saved values are restored.</p>
+<div class="section" id="enter-subblock-encoding">
+<span id="enter-subblock"></span><h4><a class="toc-backref" href="#id20">ENTER_SUBBLOCK Encoding</a><a class="headerlink" href="#enter-subblock-encoding" title="Permalink to this headline">¶</a></h4>
+<p><span class="raw-html"><tt></span>
+[ENTER_SUBBLOCK, blockid<sub>vbr8</sub>, newabbrevlen<sub>vbr4</sub>, <align32bits>, blocklen_32]
+<span class="raw-html"></tt></span></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">ENTER_SUBBLOCK</span></code> abbreviation ID specifies the start of a new block
+record. The <code class="docutils literal notranslate"><span class="pre">blockid</span></code> value is encoded as an 8-bit VBR identifier, and
+indicates the type of block being entered, which can be a <a class="reference internal" href="#standard-block">standard block</a> or
+an application-specific block. The <code class="docutils literal notranslate"><span class="pre">newabbrevlen</span></code> value is a 4-bit VBR, which
+specifies the abbrev id width for the sub-block. The <code class="docutils literal notranslate"><span class="pre">blocklen</span></code> value is a
+32-bit aligned value that specifies the size of the subblock in 32-bit
+words. This value allows the reader to skip over the entire block in one jump.</p>
+</div>
+<div class="section" id="end-block-encoding">
+<span id="end-block"></span><h4><a class="toc-backref" href="#id21">END_BLOCK Encoding</a><a class="headerlink" href="#end-block-encoding" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[END_BLOCK,</span> <span class="pre"><align32bits>]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">END_BLOCK</span></code> abbreviation ID specifies the end of the current block record.
+Its end is aligned to 32-bits to ensure that the size of the block is an even
+multiple of 32-bits.</p>
+</div>
+</div>
+<div class="section" id="data-records">
+<span id="id5"></span><h3><a class="toc-backref" href="#id22">Data Records</a><a class="headerlink" href="#data-records" title="Permalink to this headline">¶</a></h3>
+<p>Data records consist of a record code and a number of (up to) 64-bit integer
+values. The interpretation of the code and values is application specific and
+may vary between different block types. Records can be encoded either using an
+unabbrev record, or with an abbreviation. In the LLVM IR format, for example,
+there is a record which encodes the target triple of a module. The code is
+<code class="docutils literal notranslate"><span class="pre">MODULE_CODE_TRIPLE</span></code>, and the values of the record are the ASCII codes for the
+characters in the string.</p>
+<div class="section" id="unabbrev-record-encoding">
+<span id="unabbrev-record"></span><h4><a class="toc-backref" href="#id23">UNABBREV_RECORD Encoding</a><a class="headerlink" href="#unabbrev-record-encoding" title="Permalink to this headline">¶</a></h4>
+<p><span class="raw-html"><tt></span>
+[UNABBREV_RECORD, code<sub>vbr6</sub>, numops<sub>vbr6</sub>, op0<sub>vbr6</sub>, op1<sub>vbr6</sub>, â¦]
+<span class="raw-html"></tt></span></p>
+<p>An <code class="docutils literal notranslate"><span class="pre">UNABBREV_RECORD</span></code> provides a default fallback encoding, which is both
+completely general and extremely inefficient. It can describe an arbitrary
+record by emitting the code and operands as VBRs.</p>
+<p>For example, emitting an LLVM IR target triple as an unabbreviated record
+requires emitting the <code class="docutils literal notranslate"><span class="pre">UNABBREV_RECORD</span></code> abbrevid, a vbr6 for the
+<code class="docutils literal notranslate"><span class="pre">MODULE_CODE_TRIPLE</span></code> code, a vbr6 for the length of the string, which is equal
+to the number of operands, and a vbr6 for each character. Because there are no
+letters with values less than 32, each letter would need to be emitted as at
+least a two-part VBR, which means that each letter would require at least 12
+bits. This is not an efficient encoding, but it is fully general.</p>
+</div>
+<div class="section" id="abbreviated-record-encoding">
+<span id="id6"></span><h4><a class="toc-backref" href="#id24">Abbreviated Record Encoding</a><a class="headerlink" href="#abbreviated-record-encoding" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[<abbrevid>,</span> <span class="pre">fields...]</span></code></p>
+<p>An abbreviated record is a abbreviation id followed by a set of fields that are
+encoded according to the <a class="reference internal" href="#abbreviation-definition">abbreviation definition</a>. This allows records to be
+encoded significantly more densely than records encoded with the
+<a class="reference internal" href="#unabbrev-record">UNABBREV_RECORD</a> type, and allows the abbreviation types to be specified in
+the stream itself, which allows the files to be completely self describing. The
+actual encoding of abbreviations is defined below.</p>
+<p>The record code, which is the first field of an abbreviated record, may be
+encoded in the abbreviation definition (as a literal operand) or supplied in the
+abbreviated record (as a Fixed or VBR operand value).</p>
+</div>
+</div>
+<div class="section" id="abbreviations">
+<span id="abbreviation-definition"></span><h3><a class="toc-backref" href="#id25">Abbreviations</a><a class="headerlink" href="#abbreviations" title="Permalink to this headline">¶</a></h3>
+<p>Abbreviations are an important form of compression for bitstreams. The idea is
+to specify a dense encoding for a class of records once, then use that encoding
+to emit many records. It takes space to emit the encoding into the file, but
+the space is recouped (hopefully plus some) when the records that use it are
+emitted.</p>
+<p>Abbreviations can be determined dynamically per client, per file. Because the
+abbreviations are stored in the bitstream itself, different streams of the same
+format can contain different sets of abbreviations according to the needs of the
+specific stream. As a concrete example, LLVM IR files usually emit an
+abbreviation for binary operators. If a specific LLVM module contained no or
+few binary operators, the abbreviation does not need to be emitted.</p>
+<div class="section" id="define-abbrev-encoding">
+<span id="define-abbrev"></span><h4><a class="toc-backref" href="#id26">DEFINE_ABBREV Encoding</a><a class="headerlink" href="#define-abbrev-encoding" title="Permalink to this headline">¶</a></h4>
+<p><span class="raw-html"><tt></span>
+[DEFINE_ABBREV, numabbrevops<sub>vbr5</sub>, abbrevop0, abbrevop1, â¦]
+<span class="raw-html"></tt></span></p>
+<p>A <code class="docutils literal notranslate"><span class="pre">DEFINE_ABBREV</span></code> record adds an abbreviation to the list of currently defined
+abbreviations in the scope of this block. This definition only exists inside
+this immediate block â it is not visible in subblocks or enclosing blocks.
+Abbreviations are implicitly assigned IDs sequentially starting from 4 (the
+first application-defined abbreviation ID). Any abbreviations defined in a
+<code class="docutils literal notranslate"><span class="pre">BLOCKINFO</span></code> record for the particular block type receive IDs first, in order,
+followed by any abbreviations defined within the block itself. Abbreviated data
+records reference this ID to indicate what abbreviation they are invoking.</p>
+<p>An abbreviation definition consists of the <code class="docutils literal notranslate"><span class="pre">DEFINE_ABBREV</span></code> abbrevid followed
+by a VBR that specifies the number of abbrev operands, then the abbrev operands
+themselves. Abbreviation operands come in three forms. They all start with a
+single bit that indicates whether the abbrev operand is a literal operand (when
+the bit is 1) or an encoding operand (when the bit is 0).</p>
+<ol class="arabic simple">
+<li>Literal operands â <span class="raw-html"><tt></span> [1<sub>1</sub>, litvalue<sub>vbr8</sub>] <span class="raw-html"></tt></span> â Literal operands specify that the value in
+the result is always a single specific value. This specific value is emitted
+as a vbr8 after the bit indicating that it is a literal operand.</li>
+<li>Encoding info without data â <span class="raw-html"><tt></span> [0<sub>1</sub>, encoding<sub>3</sub>] <span class="raw-html"></tt></span> â Operand encodings that do not have extra data
+are just emitted as their code.</li>
+<li>Encoding info with data â <span class="raw-html"><tt></span> [0<sub>1</sub>, encoding<sub>3</sub>, value<sub>vbr5</sub>] <span class="raw-html"></tt></span> â Operand encodings that do
+have extra data are emitted as their code, followed by the extra data.</li>
+</ol>
+<p>The possible operand encodings are:</p>
+<ul class="simple">
+<li>Fixed (code 1): The field should be emitted as a <a class="reference internal" href="#fixed-width-value">fixed-width value</a>, whose
+width is specified by the operandâs extra data.</li>
+<li>VBR (code 2): The field should be emitted as a <a class="reference internal" href="#variable-width-value">variable-width value</a>, whose
+width is specified by the operandâs extra data.</li>
+<li>Array (code 3): This field is an array of values. The array operand has no
+extra data, but expects another operand to follow it, indicating the element
+type of the array. When reading an array in an abbreviated record, the first
+integer is a vbr6 that indicates the array length, followed by the encoded
+elements of the array. An array may only occur as the last operand of an
+abbreviation (except for the one final operand that gives the arrayâs
+type).</li>
+<li>Char6 (code 4): This field should be emitted as a <a class="reference internal" href="#char6-encoded-value">char6-encoded value</a>.
+This operand type takes no extra data. Char6 encoding is normally used as an
+array element type.</li>
+<li>Blob (code 5): This field is emitted as a vbr6, followed by padding to a
+32-bit boundary (for alignment) and an array of 8-bit objects. The array of
+bytes is further followed by tail padding to ensure that its total length is a
+multiple of 4 bytes. This makes it very efficient for the reader to decode
+the data without having to make a copy of it: it can use a pointer to the data
+in the mapped in file and poke directly at it. A blob may only occur as the
+last operand of an abbreviation.</li>
+</ul>
+<p>For example, target triples in LLVM modules are encoded as a record of the form
+<code class="docutils literal notranslate"><span class="pre">[TRIPLE,</span> <span class="pre">'a',</span> <span class="pre">'b',</span> <span class="pre">'c',</span> <span class="pre">'d']</span></code>. Consider if the bitstream emitted the
+following abbrev entry:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="p">[</span><span class="mi">0</span><span class="p">,</span> <span class="n">Fixed</span><span class="p">,</span> <span class="mi">4</span><span class="p">]</span>
+<span class="p">[</span><span class="mi">0</span><span class="p">,</span> <span class="n">Array</span><span class="p">]</span>
+<span class="p">[</span><span class="mi">0</span><span class="p">,</span> <span class="n">Char6</span><span class="p">]</span>
+</pre></div>
+</div>
+<p>When emitting a record with this abbreviation, the above entry would be emitted
+as:</p>
+<p><span class="raw-html"><tt><blockquote></span>
+[4<sub>abbrevwidth</sub>, 2<sub>4</sub>, 4<sub>vbr6</sub>, 0<sub>6</sub>, 1<sub>6</sub>, 2<sub>6</sub>, 3<sub>6</sub>]
+<span class="raw-html"></blockquote></tt></span></p>
+<p>These values are:</p>
+<ol class="arabic simple">
+<li>The first value, 4, is the abbreviation ID for this abbreviation.</li>
+<li>The second value, 2, is the record code for <code class="docutils literal notranslate"><span class="pre">TRIPLE</span></code> records within LLVM IR
+file <code class="docutils literal notranslate"><span class="pre">MODULE_BLOCK</span></code> blocks.</li>
+<li>The third value, 4, is the length of the array.</li>
+<li>The rest of the values are the char6 encoded values for <code class="docutils literal notranslate"><span class="pre">"abcd"</span></code>.</li>
+</ol>
+<p>With this abbreviation, the triple is emitted with only 37 bits (assuming a
+abbrev id width of 3). Without the abbreviation, significantly more space would
+be required to emit the target triple. Also, because the <code class="docutils literal notranslate"><span class="pre">TRIPLE</span></code> value is
+not emitted as a literal in the abbreviation, the abbreviation can also be used
+for any other string value.</p>
+</div>
+</div>
+<div class="section" id="standard-block">
+<span id="standard-blocks"></span><span id="id7"></span><h3><a class="toc-backref" href="#id27">Standard Blocks</a><a class="headerlink" href="#standard-block" title="Permalink to this headline">¶</a></h3>
+<p>In addition to the basic block structure and record encodings, the bitstream
+also defines specific built-in block types. These block types specify how the
+stream is to be decoded or other metadata. In the future, new standard blocks
+may be added. Block IDs 0-7 are reserved for standard blocks.</p>
+<div class="section" id="blockinfo-block">
+<span id="blockinfo"></span><h4><a class="toc-backref" href="#id28">#0 - BLOCKINFO Block</a><a class="headerlink" href="#blockinfo-block" title="Permalink to this headline">¶</a></h4>
+<p>The <code class="docutils literal notranslate"><span class="pre">BLOCKINFO</span></code> block allows the description of metadata for other blocks.
+The currently specified records are:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="p">[</span><span class="n">SETBID</span> <span class="p">(</span><span class="c1">#1), blockid]</span>
+<span class="p">[</span><span class="n">DEFINE_ABBREV</span><span class="p">,</span> <span class="o">...</span><span class="p">]</span>
+<span class="p">[</span><span class="n">BLOCKNAME</span><span class="p">,</span> <span class="o">...</span><span class="n">name</span><span class="o">...</span><span class="p">]</span>
+<span class="p">[</span><span class="n">SETRECORDNAME</span><span class="p">,</span> <span class="n">RecordID</span><span class="p">,</span> <span class="o">...</span><span class="n">name</span><span class="o">...</span><span class="p">]</span>
+</pre></div>
+</div>
+<p>The <code class="docutils literal notranslate"><span class="pre">SETBID</span></code> record (code 1) indicates which block ID is being described.
+<code class="docutils literal notranslate"><span class="pre">SETBID</span></code> records can occur multiple times throughout the block to change which
+block ID is being described. There must be a <code class="docutils literal notranslate"><span class="pre">SETBID</span></code> record prior to any
+other records.</p>
+<p>Standard <code class="docutils literal notranslate"><span class="pre">DEFINE_ABBREV</span></code> records can occur inside <code class="docutils literal notranslate"><span class="pre">BLOCKINFO</span></code> blocks, but
+unlike their occurrence in normal blocks, the abbreviation is defined for blocks
+matching the block ID we are describing, <em>not</em> the <code class="docutils literal notranslate"><span class="pre">BLOCKINFO</span></code> block
+itself. The abbreviations defined in <code class="docutils literal notranslate"><span class="pre">BLOCKINFO</span></code> blocks receive abbreviation
+IDs as described in <a class="reference internal" href="#define-abbrev">DEFINE_ABBREV</a>.</p>
+<p>The <code class="docutils literal notranslate"><span class="pre">BLOCKNAME</span></code> record (code 2) can optionally occur in this block. The
+elements of the record are the bytes of the string name of the block.
+llvm-bcanalyzer can use this to dump out bitcode files symbolically.</p>
+<p>The <code class="docutils literal notranslate"><span class="pre">SETRECORDNAME</span></code> record (code 3) can also optionally occur in this block.
+The first operand value is a record ID number, and the rest of the elements of
+the record are the bytes for the string name of the record. llvm-bcanalyzer can
+use this to dump out bitcode files symbolically.</p>
+<p>Note that although the data in <code class="docutils literal notranslate"><span class="pre">BLOCKINFO</span></code> blocks is described as âmetadata,â
+the abbreviations they contain are essential for parsing records from the
+corresponding blocks. It is not safe to skip them.</p>
+</div>
+</div>
+</div>
+<div class="section" id="bitcode-wrapper-format">
+<span id="wrapper"></span><h2><a class="toc-backref" href="#id29">Bitcode Wrapper Format</a><a class="headerlink" href="#bitcode-wrapper-format" title="Permalink to this headline">¶</a></h2>
+<p>Bitcode files for LLVM IR may optionally be wrapped in a simple wrapper
+structure. This structure contains a simple header that indicates the offset
+and size of the embedded BC file. This allows additional information to be
+stored alongside the BC file. The structure of this file header is:</p>
+<p><span class="raw-html"><tt><blockquote></span>
+[Magic<sub>32</sub>, Version<sub>32</sub>, Offset<sub>32</sub>, Size<sub>32</sub>, CPUType<sub>32</sub>]
+<span class="raw-html"></blockquote></tt></span></p>
+<p>Each of the fields are 32-bit fields stored in little endian form (as with the
+rest of the bitcode file fields). The Magic number is always <code class="docutils literal notranslate"><span class="pre">0x0B17C0DE</span></code> and
+the version is currently always <code class="docutils literal notranslate"><span class="pre">0</span></code>. The Offset field is the offset in bytes
+to the start of the bitcode stream in the file, and the Size field is the size
+in bytes of the stream. CPUType is a target-specific value that can be used to
+encode the CPU of the target.</p>
+</div>
+<div class="section" id="native-object-file-wrapper-format">
+<span id="native-object-file"></span><h2><a class="toc-backref" href="#id30">Native Object File Wrapper Format</a><a class="headerlink" href="#native-object-file-wrapper-format" title="Permalink to this headline">¶</a></h2>
+<p>Bitcode files for LLVM IR may also be wrapped in a native object file
+(i.e. ELF, COFF, Mach-O). The bitcode must be stored in a section of the object
+file named <code class="docutils literal notranslate"><span class="pre">__LLVM,__bitcode</span></code> for MachO and <code class="docutils literal notranslate"><span class="pre">.llvmbc</span></code> for the other object
+formats. This wrapper format is useful for accommodating LTO in compilation
+pipelines where intermediate objects must be native object files which contain
+metadata in other sections.</p>
+<p>Not all tools support this format.</p>
+</div>
+<div class="section" id="llvm-ir-encoding">
+<span id="encoding-of-llvm-ir"></span><h2><a class="toc-backref" href="#id31">LLVM IR Encoding</a><a class="headerlink" href="#llvm-ir-encoding" title="Permalink to this headline">¶</a></h2>
+<p>LLVM IR is encoded into a bitstream by defining blocks and records. It uses
+blocks for things like constant pools, functions, symbol tables, etc. It uses
+records for things like instructions, global variable descriptors, type
+descriptions, etc. This document does not describe the set of abbreviations
+that the writer uses, as these are fully self-described in the file, and the
+reader is not allowed to build in any knowledge of this.</p>
+<div class="section" id="basics">
+<h3><a class="toc-backref" href="#id32">Basics</a><a class="headerlink" href="#basics" title="Permalink to this headline">¶</a></h3>
+<div class="section" id="llvm-ir-magic-number">
+<h4><a class="toc-backref" href="#id33">LLVM IR Magic Number</a><a class="headerlink" href="#llvm-ir-magic-number" title="Permalink to this headline">¶</a></h4>
+<p>The magic number for LLVM IR files is:</p>
+<p><span class="raw-html"><tt><blockquote></span>
+[âBâ<sub>8</sub>, âCâ<sub>8</sub>, 0x0<sub>4</sub>, 0xC<sub>4</sub>, 0xE<sub>4</sub>, 0xD<sub>4</sub>]
+<span class="raw-html"></blockquote></tt></span></p>
+</div>
+<div class="section" id="signed-vbrs">
+<span id="id8"></span><h4><a class="toc-backref" href="#id34">Signed VBRs</a><a class="headerlink" href="#signed-vbrs" title="Permalink to this headline">¶</a></h4>
+<p><a class="reference internal" href="#variable-width-integer">Variable Width Integer</a> encoding is an efficient way to encode arbitrary sized
+unsigned values, but is an extremely inefficient for encoding signed values, as
+signed values are otherwise treated as maximally large unsigned values.</p>
+<p>As such, signed VBR values of a specific width are emitted as follows:</p>
+<ul class="simple">
+<li>Positive values are emitted as VBRs of the specified width, but with their
+value shifted left by one.</li>
+<li>Negative values are emitted as VBRs of the specified width, but the negated
+value is shifted left by one, and the low bit is set.</li>
+</ul>
+<p>With this encoding, small positive and small negative values can both be emitted
+efficiently. Signed VBR encoding is used in <code class="docutils literal notranslate"><span class="pre">CST_CODE_INTEGER</span></code> and
+<code class="docutils literal notranslate"><span class="pre">CST_CODE_WIDE_INTEGER</span></code> records within <code class="docutils literal notranslate"><span class="pre">CONSTANTS_BLOCK</span></code> blocks.
+It is also used for phi instruction operands in <a class="reference internal" href="#module-code-version">MODULE_CODE_VERSION</a> 1.</p>
+</div>
+<div class="section" id="llvm-ir-blocks">
+<h4><a class="toc-backref" href="#id35">LLVM IR Blocks</a><a class="headerlink" href="#llvm-ir-blocks" title="Permalink to this headline">¶</a></h4>
+<p>LLVM IR is defined with the following blocks:</p>
+<ul class="simple">
+<li>8 â <a class="reference internal" href="#module-block">MODULE_BLOCK</a> â This is the top-level block that contains the entire
+module, and describes a variety of per-module information.</li>
+<li>9 â <a class="reference internal" href="#paramattr-block">PARAMATTR_BLOCK</a> â This enumerates the parameter attributes.</li>
+<li>10 â <a class="reference internal" href="#paramattr-group-block">PARAMATTR_GROUP_BLOCK</a> â This describes the attribute group table.</li>
+<li>11 â <a class="reference internal" href="#constants-block">CONSTANTS_BLOCK</a> â This describes constants for a module or
+function.</li>
+<li>12 â <a class="reference internal" href="#function-block">FUNCTION_BLOCK</a> â This describes a function body.</li>
+<li>14 â <a class="reference internal" href="#value-symtab-block">VALUE_SYMTAB_BLOCK</a> â This describes a value symbol table.</li>
+<li>15 â <a class="reference internal" href="#metadata-block">METADATA_BLOCK</a> â This describes metadata items.</li>
+<li>16 â <a class="reference internal" href="#metadata-attachment">METADATA_ATTACHMENT</a> â This contains records associating metadata
+with function instruction values.</li>
+<li>17 â <a class="reference internal" href="#type-block">TYPE_BLOCK</a> â This describes all of the types in the module.</li>
+<li>23 â <a class="reference internal" href="#strtab-block">STRTAB_BLOCK</a> â The bitcode fileâs string table.</li>
+</ul>
+</div>
+</div>
+<div class="section" id="module-block-contents">
+<span id="module-block"></span><h3><a class="toc-backref" href="#id36">MODULE_BLOCK Contents</a><a class="headerlink" href="#module-block-contents" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal notranslate"><span class="pre">MODULE_BLOCK</span></code> block (id 8) is the top-level block for LLVM bitcode files,
+and each bitcode file must contain exactly one. In addition to records
+(described below) containing information about the module, a <code class="docutils literal notranslate"><span class="pre">MODULE_BLOCK</span></code>
+block may contain the following sub-blocks:</p>
+<ul class="simple">
+<li><a class="reference internal" href="#blockinfo">BLOCKINFO</a></li>
+<li><a class="reference internal" href="#paramattr-block">PARAMATTR_BLOCK</a></li>
+<li><a class="reference internal" href="#paramattr-group-block">PARAMATTR_GROUP_BLOCK</a></li>
+<li><a class="reference internal" href="#type-block">TYPE_BLOCK</a></li>
+<li><a class="reference internal" href="#value-symtab-block">VALUE_SYMTAB_BLOCK</a></li>
+<li><a class="reference internal" href="#constants-block">CONSTANTS_BLOCK</a></li>
+<li><a class="reference internal" href="#function-block">FUNCTION_BLOCK</a></li>
+<li><a class="reference internal" href="#metadata-block">METADATA_BLOCK</a></li>
+</ul>
+<div class="section" id="module-code-version-record">
+<span id="module-code-version"></span><h4><a class="toc-backref" href="#id37">MODULE_CODE_VERSION Record</a><a class="headerlink" href="#module-code-version-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[VERSION,</span> <span class="pre">version#]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">VERSION</span></code> record (code 1) contains a single value indicating the format
+version. Versions 0, 1 and 2 are supported at this time. The difference between
+version 0 and 1 is in the encoding of instruction operands in
+each <a class="reference internal" href="#function-block">FUNCTION_BLOCK</a>.</p>
+<p>In version 0, each value defined by an instruction is assigned an ID
+unique to the function. Function-level value IDs are assigned starting from
+<code class="docutils literal notranslate"><span class="pre">NumModuleValues</span></code> since they share the same namespace as module-level
+values. The value enumerator resets after each function. When a value is
+an operand of an instruction, the value ID is used to represent the operand.
+For large functions or large modules, these operand values can be large.</p>
+<p>The encoding in version 1 attempts to avoid large operand values
+in common cases. Instead of using the value ID directly, operands are
+encoded as relative to the current instruction. Thus, if an operand
+is the value defined by the previous instruction, the operand
+will be encoded as 1.</p>
+<p>For example, instead of</p>
+<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>#n = load #n-1
+#n+1 = icmp eq #n, #const0
+br #n+1, label #(bb1), label #(bb2)
+</pre></div>
+</div>
+<p>version 1 will encode the instructions as</p>
+<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>#n = load #1
+#n+1 = icmp eq #1, (#n+1)-#const0
+br #1, label #(bb1), label #(bb2)
+</pre></div>
+</div>
+<p>Note in the example that operands which are constants also use
+the relative encoding, while operands like basic block labels
+do not use the relative encoding.</p>
+<p>Forward references will result in a negative value.
+This can be inefficient, as operands are normally encoded
+as unsigned VBRs. However, forward references are rare, except in the
+case of phi instructions. For phi instructions, operands are encoded as
+<a class="reference internal" href="#signed-vbrs">Signed VBRs</a> to deal with forward references.</p>
+<p>In version 2, the meaning of module records <code class="docutils literal notranslate"><span class="pre">FUNCTION</span></code>, <code class="docutils literal notranslate"><span class="pre">GLOBALVAR</span></code>,
+<code class="docutils literal notranslate"><span class="pre">ALIAS</span></code>, <code class="docutils literal notranslate"><span class="pre">IFUNC</span></code> and <code class="docutils literal notranslate"><span class="pre">COMDAT</span></code> change such that the first two operands
+specify an offset and size of a string in a string table (see <a class="reference internal" href="#strtab-block-contents">STRTAB_BLOCK
+Contents</a>), the function name is removed from the <code class="docutils literal notranslate"><span class="pre">FNENTRY</span></code> record in the
+value symbol table, and the top-level <code class="docutils literal notranslate"><span class="pre">VALUE_SYMTAB_BLOCK</span></code> may only contain
+<code class="docutils literal notranslate"><span class="pre">FNENTRY</span></code> records.</p>
+</div>
+<div class="section" id="module-code-triple-record">
+<h4><a class="toc-backref" href="#id38">MODULE_CODE_TRIPLE Record</a><a class="headerlink" href="#module-code-triple-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[TRIPLE,</span> <span class="pre">...string...]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">TRIPLE</span></code> record (code 2) contains a variable number of values representing
+the bytes of the <code class="docutils literal notranslate"><span class="pre">target</span> <span class="pre">triple</span></code> specification string.</p>
+</div>
+<div class="section" id="module-code-datalayout-record">
+<h4><a class="toc-backref" href="#id39">MODULE_CODE_DATALAYOUT Record</a><a class="headerlink" href="#module-code-datalayout-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[DATALAYOUT,</span> <span class="pre">...string...]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">DATALAYOUT</span></code> record (code 3) contains a variable number of values
+representing the bytes of the <code class="docutils literal notranslate"><span class="pre">target</span> <span class="pre">datalayout</span></code> specification string.</p>
+</div>
+<div class="section" id="module-code-asm-record">
+<h4><a class="toc-backref" href="#id40">MODULE_CODE_ASM Record</a><a class="headerlink" href="#module-code-asm-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[ASM,</span> <span class="pre">...string...]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">ASM</span></code> record (code 4) contains a variable number of values representing
+the bytes of <code class="docutils literal notranslate"><span class="pre">module</span> <span class="pre">asm</span></code> strings, with individual assembly blocks separated
+by newline (ASCII 10) characters.</p>
+</div>
+<div class="section" id="module-code-sectionname-record">
+<span id="module-code-sectionname"></span><h4><a class="toc-backref" href="#id41">MODULE_CODE_SECTIONNAME Record</a><a class="headerlink" href="#module-code-sectionname-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[SECTIONNAME,</span> <span class="pre">...string...]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">SECTIONNAME</span></code> record (code 5) contains a variable number of values
+representing the bytes of a single section name string. There should be one
+<code class="docutils literal notranslate"><span class="pre">SECTIONNAME</span></code> record for each section name referenced (e.g., in global
+variable or function <code class="docutils literal notranslate"><span class="pre">section</span></code> attributes) within the module. These records
+can be referenced by the 1-based index in the <em>section</em> fields of <code class="docutils literal notranslate"><span class="pre">GLOBALVAR</span></code>
+or <code class="docutils literal notranslate"><span class="pre">FUNCTION</span></code> records.</p>
+</div>
+<div class="section" id="module-code-deplib-record">
+<h4><a class="toc-backref" href="#id42">MODULE_CODE_DEPLIB Record</a><a class="headerlink" href="#module-code-deplib-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[DEPLIB,</span> <span class="pre">...string...]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">DEPLIB</span></code> record (code 6) contains a variable number of values representing
+the bytes of a single dependent library name string, one of the libraries
+mentioned in a <code class="docutils literal notranslate"><span class="pre">deplibs</span></code> declaration. There should be one <code class="docutils literal notranslate"><span class="pre">DEPLIB</span></code> record
+for each library name referenced.</p>
+</div>
+<div class="section" id="module-code-globalvar-record">
+<h4><a class="toc-backref" href="#id43">MODULE_CODE_GLOBALVAR Record</a><a class="headerlink" href="#module-code-globalvar-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[GLOBALVAR,</span> <span class="pre">strtab</span> <span class="pre">offset,</span> <span class="pre">strtab</span> <span class="pre">size,</span> <span class="pre">pointer</span> <span class="pre">type,</span> <span class="pre">isconst,</span> <span class="pre">initid,</span> <span class="pre">linkage,</span> <span class="pre">alignment,</span> <span class="pre">section,</span> <span class="pre">visibility,</span> <span class="pre">threadlocal,</span> <span class="pre">unnamed_addr,</span> <span class="pre">externally_initialized,</span> <span class="pre">dllstorageclass,</span> <span class="pre">comdat,</span> <span class="pre">attributes,</span> <span class="pre">preemptionspecifier]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">GLOBALVAR</span></code> record (code 7) marks the declaration or definition of a
+global variable. The operand fields are:</p>
+<ul class="simple">
+<li><em>strtab offset</em>, <em>strtab size</em>: Specifies the name of the global variable.
+See <a class="reference internal" href="#strtab-block-contents">STRTAB_BLOCK Contents</a>.</li>
+<li><em>pointer type</em>: The type index of the pointer type used to point to this
+global variable</li>
+<li><em>isconst</em>: Non-zero if the variable is treated as constant within the module,
+or zero if it is not</li>
+<li><em>initid</em>: If non-zero, the value index of the initializer for this variable,
+plus 1.</li>
+</ul>
+<ul class="simple" id="linkage-type">
+<li><em>linkage</em>: An encoding of the linkage type for this variable:<ul>
+<li><code class="docutils literal notranslate"><span class="pre">external</span></code>: code 0</li>
+<li><code class="docutils literal notranslate"><span class="pre">weak</span></code>: code 1</li>
+<li><code class="docutils literal notranslate"><span class="pre">appending</span></code>: code 2</li>
+<li><code class="docutils literal notranslate"><span class="pre">internal</span></code>: code 3</li>
+<li><code class="docutils literal notranslate"><span class="pre">linkonce</span></code>: code 4</li>
+<li><code class="docutils literal notranslate"><span class="pre">dllimport</span></code>: code 5</li>
+<li><code class="docutils literal notranslate"><span class="pre">dllexport</span></code>: code 6</li>
+<li><code class="docutils literal notranslate"><span class="pre">extern_weak</span></code>: code 7</li>
+<li><code class="docutils literal notranslate"><span class="pre">common</span></code>: code 8</li>
+<li><code class="docutils literal notranslate"><span class="pre">private</span></code>: code 9</li>
+<li><code class="docutils literal notranslate"><span class="pre">weak_odr</span></code>: code 10</li>
+<li><code class="docutils literal notranslate"><span class="pre">linkonce_odr</span></code>: code 11</li>
+<li><code class="docutils literal notranslate"><span class="pre">available_externally</span></code>: code 12</li>
+<li>deprecated : code 13</li>
+<li>deprecated : code 14</li>
+</ul>
+</li>
+<li>alignment*: The logarithm base 2 of the variableâs requested alignment, plus 1</li>
+<li><em>section</em>: If non-zero, the 1-based section index in the table of
+<a class="reference internal" href="#module-code-sectionname">MODULE_CODE_SECTIONNAME</a> entries.</li>
+</ul>
+<ul class="simple" id="visibility">
+<li><em>visibility</em>: If present, an encoding of the visibility of this variable:<ul>
+<li><code class="docutils literal notranslate"><span class="pre">default</span></code>: code 0</li>
+<li><code class="docutils literal notranslate"><span class="pre">hidden</span></code>: code 1</li>
+<li><code class="docutils literal notranslate"><span class="pre">protected</span></code>: code 2</li>
+</ul>
+</li>
+</ul>
+<ul class="simple" id="bcthreadlocal">
+<li><em>threadlocal</em>: If present, an encoding of the thread local storage mode of the
+variable:<ul>
+<li><code class="docutils literal notranslate"><span class="pre">not</span> <span class="pre">thread</span> <span class="pre">local</span></code>: code 0</li>
+<li><code class="docutils literal notranslate"><span class="pre">thread</span> <span class="pre">local;</span> <span class="pre">default</span> <span class="pre">TLS</span> <span class="pre">model</span></code>: code 1</li>
+<li><code class="docutils literal notranslate"><span class="pre">localdynamic</span></code>: code 2</li>
+<li><code class="docutils literal notranslate"><span class="pre">initialexec</span></code>: code 3</li>
+<li><code class="docutils literal notranslate"><span class="pre">localexec</span></code>: code 4</li>
+</ul>
+</li>
+</ul>
+<ul class="simple" id="bcunnamedaddr">
+<li><em>unnamed_addr</em>: If present, an encoding of the <code class="docutils literal notranslate"><span class="pre">unnamed_addr</span></code> attribute of this
+variable:<ul>
+<li>not <code class="docutils literal notranslate"><span class="pre">unnamed_addr</span></code>: code 0</li>
+<li><code class="docutils literal notranslate"><span class="pre">unnamed_addr</span></code>: code 1</li>
+<li><code class="docutils literal notranslate"><span class="pre">local_unnamed_addr</span></code>: code 2</li>
+</ul>
+</li>
+</ul>
+<ul class="simple" id="bcdllstorageclass">
+<li><em>dllstorageclass</em>: If present, an encoding of the DLL storage class of this variable:<ul>
+<li><code class="docutils literal notranslate"><span class="pre">default</span></code>: code 0</li>
+<li><code class="docutils literal notranslate"><span class="pre">dllimport</span></code>: code 1</li>
+<li><code class="docutils literal notranslate"><span class="pre">dllexport</span></code>: code 2</li>
+</ul>
+</li>
+<li><em>comdat</em>: An encoding of the COMDAT of this function</li>
+<li><em>attributes</em>: If nonzero, the 1-based index into the table of AttributeLists.</li>
+</ul>
+<ul class="simple" id="bcpreemptionspecifier">
+<li><em>preemptionspecifier</em>: If present, an encoding of the runtime preemption specifier of this variable:<ul>
+<li><code class="docutils literal notranslate"><span class="pre">dso_preemptable</span></code>: code 0</li>
+<li><code class="docutils literal notranslate"><span class="pre">dso_local</span></code>: code 1</li>
+</ul>
+</li>
+</ul>
+</div>
+<div class="section" id="module-code-function-record">
+<span id="function"></span><h4><a class="toc-backref" href="#id44">MODULE_CODE_FUNCTION Record</a><a class="headerlink" href="#module-code-function-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[FUNCTION,</span> <span class="pre">strtab</span> <span class="pre">offset,</span> <span class="pre">strtab</span> <span class="pre">size,</span> <span class="pre">type,</span> <span class="pre">callingconv,</span> <span class="pre">isproto,</span> <span class="pre">linkage,</span> <span class="pre">paramattr,</span> <span class="pre">alignment,</span> <span class="pre">section,</span> <span class="pre">visibility,</span> <span class="pre">gc,</span> <span class="pre">prologuedata,</span> <span class="pre">dllstorageclass,</span> <span class="pre">comdat,</span> <span class="pre">prefixdata,</span> <span class="pre">personalityfn,</span> <span class="pre">preemptionspecifier]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">FUNCTION</span></code> record (code 8) marks the declaration or definition of a
+function. The operand fields are:</p>
+<ul class="simple">
+<li><em>strtab offset</em>, <em>strtab size</em>: Specifies the name of the function.
+See <a class="reference internal" href="#strtab-block-contents">STRTAB_BLOCK Contents</a>.</li>
+<li><em>type</em>: The type index of the function type describing this function</li>
+<li><em>callingconv</em>: The calling convention number:
+* <code class="docutils literal notranslate"><span class="pre">ccc</span></code>: code 0
+* <code class="docutils literal notranslate"><span class="pre">fastcc</span></code>: code 8
+* <code class="docutils literal notranslate"><span class="pre">coldcc</span></code>: code 9
+* <code class="docutils literal notranslate"><span class="pre">webkit_jscc</span></code>: code 12
+* <code class="docutils literal notranslate"><span class="pre">anyregcc</span></code>: code 13
+* <code class="docutils literal notranslate"><span class="pre">preserve_mostcc</span></code>: code 14
+* <code class="docutils literal notranslate"><span class="pre">preserve_allcc</span></code>: code 15
+* <code class="docutils literal notranslate"><span class="pre">swiftcc</span></code> : code 16
+* <code class="docutils literal notranslate"><span class="pre">cxx_fast_tlscc</span></code>: code 17
+* <code class="docutils literal notranslate"><span class="pre">x86_stdcallcc</span></code>: code 64
+* <code class="docutils literal notranslate"><span class="pre">x86_fastcallcc</span></code>: code 65
+* <code class="docutils literal notranslate"><span class="pre">arm_apcscc</span></code>: code 66
+* <code class="docutils literal notranslate"><span class="pre">arm_aapcscc</span></code>: code 67
+* <code class="docutils literal notranslate"><span class="pre">arm_aapcs_vfpcc</span></code>: code 68</li>
+<li>isproto*: Non-zero if this entry represents a declaration rather than a
+definition</li>
+<li><em>linkage</em>: An encoding of the <a class="reference internal" href="#linkage-type">linkage type</a> for this function</li>
+<li><em>paramattr</em>: If nonzero, the 1-based parameter attribute index into the table
+of <a class="reference internal" href="#paramattr-code-entry">PARAMATTR_CODE_ENTRY</a> entries.</li>
+<li><em>alignment</em>: The logarithm base 2 of the functionâs requested alignment, plus
+1</li>
+<li><em>section</em>: If non-zero, the 1-based section index in the table of
+<a class="reference internal" href="#module-code-sectionname">MODULE_CODE_SECTIONNAME</a> entries.</li>
+<li><em>visibility</em>: An encoding of the <a class="reference internal" href="#visibility">visibility</a> of this function</li>
+<li><em>gc</em>: If present and nonzero, the 1-based garbage collector index in the table
+of <a class="reference internal" href="#module-code-gcname">MODULE_CODE_GCNAME</a> entries.</li>
+<li><em>unnamed_addr</em>: If present, an encoding of the
+<a class="reference internal" href="#bcunnamedaddr"><span class="std std-ref">unnamed_addr</span></a> attribute of this function</li>
+<li><em>prologuedata</em>: If non-zero, the value index of the prologue data for this function,
+plus 1.</li>
+<li><em>dllstorageclass</em>: An encoding of the
+<a class="reference internal" href="#bcdllstorageclass"><span class="std std-ref">dllstorageclass</span></a> of this function</li>
+<li><em>comdat</em>: An encoding of the COMDAT of this function</li>
+<li><em>prefixdata</em>: If non-zero, the value index of the prefix data for this function,
+plus 1.</li>
+<li><em>personalityfn</em>: If non-zero, the value index of the personality function for this function,
+plus 1.</li>
+<li><em>preemptionspecifier</em>: If present, an encoding of the <a class="reference internal" href="#bcpreemptionspecifier"><span class="std std-ref">runtime preemption specifier</span></a> of this function.</li>
+</ul>
+</div>
+<div class="section" id="module-code-alias-record">
+<h4><a class="toc-backref" href="#id45">MODULE_CODE_ALIAS Record</a><a class="headerlink" href="#module-code-alias-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[ALIAS,</span> <span class="pre">strtab</span> <span class="pre">offset,</span> <span class="pre">strtab</span> <span class="pre">size,</span> <span class="pre">alias</span> <span class="pre">type,</span> <span class="pre">aliasee</span> <span class="pre">val#,</span> <span class="pre">linkage,</span> <span class="pre">visibility,</span> <span class="pre">dllstorageclass,</span> <span class="pre">threadlocal,</span> <span class="pre">unnamed_addr,</span> <span class="pre">preemptionspecifier]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">ALIAS</span></code> record (code 9) marks the definition of an alias. The operand
+fields are</p>
+<ul class="simple">
+<li><em>strtab offset</em>, <em>strtab size</em>: Specifies the name of the alias.
+See <a class="reference internal" href="#strtab-block-contents">STRTAB_BLOCK Contents</a>.</li>
+<li><em>alias type</em>: The type index of the alias</li>
+<li><em>aliasee val#</em>: The value index of the aliased value</li>
+<li><em>linkage</em>: An encoding of the <a class="reference internal" href="#linkage-type">linkage type</a> for this alias</li>
+<li><em>visibility</em>: If present, an encoding of the <a class="reference internal" href="#visibility">visibility</a> of the alias</li>
+<li><em>dllstorageclass</em>: If present, an encoding of the
+<a class="reference internal" href="#bcdllstorageclass"><span class="std std-ref">dllstorageclass</span></a> of the alias</li>
+<li><em>threadlocal</em>: If present, an encoding of the
+<a class="reference internal" href="#bcthreadlocal"><span class="std std-ref">thread local property</span></a> of the alias</li>
+<li><em>unnamed_addr</em>: If present, an encoding of the
+<a class="reference internal" href="#bcunnamedaddr"><span class="std std-ref">unnamed_addr</span></a> attribute of this alias</li>
+<li><em>preemptionspecifier</em>: If present, an encoding of the <a class="reference internal" href="#bcpreemptionspecifier"><span class="std std-ref">runtime preemption specifier</span></a> of this alias.</li>
+</ul>
+</div>
+<div class="section" id="module-code-gcname-record">
+<span id="module-code-gcname"></span><h4><a class="toc-backref" href="#id46">MODULE_CODE_GCNAME Record</a><a class="headerlink" href="#module-code-gcname-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[GCNAME,</span> <span class="pre">...string...]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">GCNAME</span></code> record (code 11) contains a variable number of values
+representing the bytes of a single garbage collector name string. There should
+be one <code class="docutils literal notranslate"><span class="pre">GCNAME</span></code> record for each garbage collector name referenced in function
+<code class="docutils literal notranslate"><span class="pre">gc</span></code> attributes within the module. These records can be referenced by 1-based
+index in the <em>gc</em> fields of <code class="docutils literal notranslate"><span class="pre">FUNCTION</span></code> records.</p>
+</div>
+</div>
+<div class="section" id="paramattr-block-contents">
+<span id="paramattr-block"></span><h3><a class="toc-backref" href="#id47">PARAMATTR_BLOCK Contents</a><a class="headerlink" href="#paramattr-block-contents" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal notranslate"><span class="pre">PARAMATTR_BLOCK</span></code> block (id 9) contains a table of entries describing the
+attributes of function parameters. These entries are referenced by 1-based index
+in the <em>paramattr</em> field of module block <a class="reference internal" href="#function">FUNCTION</a> records, or within the
+<em>attr</em> field of function block <code class="docutils literal notranslate"><span class="pre">INST_INVOKE</span></code> and <code class="docutils literal notranslate"><span class="pre">INST_CALL</span></code> records.</p>
+<p>Entries within <code class="docutils literal notranslate"><span class="pre">PARAMATTR_BLOCK</span></code> are constructed to ensure that each is unique
+(i.e., no two indices represent equivalent attribute lists).</p>
+<div class="section" id="paramattr-code-entry-record">
+<span id="paramattr-code-entry"></span><h4><a class="toc-backref" href="#id48">PARAMATTR_CODE_ENTRY Record</a><a class="headerlink" href="#paramattr-code-entry-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[ENTRY,</span> <span class="pre">attrgrp0,</span> <span class="pre">attrgrp1,</span> <span class="pre">...]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">ENTRY</span></code> record (code 2) contains a variable number of values describing a
+unique set of function parameter attributes. Each <em>attrgrp</em> value is used as a
+key with which to look up an entry in the attribute group table described
+in the <code class="docutils literal notranslate"><span class="pre">PARAMATTR_GROUP_BLOCK</span></code> block.</p>
+</div>
+<div class="section" id="paramattr-code-entry-old-record">
+<span id="paramattr-code-entry-old"></span><h4><a class="toc-backref" href="#id49">PARAMATTR_CODE_ENTRY_OLD Record</a><a class="headerlink" href="#paramattr-code-entry-old-record" title="Permalink to this headline">¶</a></h4>
+<div class="admonition note">
+<p class="first admonition-title">Note</p>
+<p class="last">This is a legacy encoding for attributes, produced by LLVM versions 3.2 and
+earlier. It is guaranteed to be understood by the current LLVM version, as
+specified in the <a class="reference internal" href="DeveloperPolicy.html#ir-backwards-compatibility"><span class="std std-ref">IR Backwards Compatibility</span></a> policy.</p>
+</div>
+<p><code class="docutils literal notranslate"><span class="pre">[ENTRY,</span> <span class="pre">paramidx0,</span> <span class="pre">attr0,</span> <span class="pre">paramidx1,</span> <span class="pre">attr1...]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">ENTRY</span></code> record (code 1) contains an even number of values describing a
+unique set of function parameter attributes. Each <em>paramidx</em> value indicates
+which set of attributes is represented, with 0 representing the return value
+attributes, 0xFFFFFFFF representing function attributes, and other values
+representing 1-based function parameters. Each <em>attr</em> value is a bitmap with the
+following interpretation:</p>
+<ul class="simple">
+<li>bit 0: <code class="docutils literal notranslate"><span class="pre">zeroext</span></code></li>
+<li>bit 1: <code class="docutils literal notranslate"><span class="pre">signext</span></code></li>
+<li>bit 2: <code class="docutils literal notranslate"><span class="pre">noreturn</span></code></li>
+<li>bit 3: <code class="docutils literal notranslate"><span class="pre">inreg</span></code></li>
+<li>bit 4: <code class="docutils literal notranslate"><span class="pre">sret</span></code></li>
+<li>bit 5: <code class="docutils literal notranslate"><span class="pre">nounwind</span></code></li>
+<li>bit 6: <code class="docutils literal notranslate"><span class="pre">noalias</span></code></li>
+<li>bit 7: <code class="docutils literal notranslate"><span class="pre">byval</span></code></li>
+<li>bit 8: <code class="docutils literal notranslate"><span class="pre">nest</span></code></li>
+<li>bit 9: <code class="docutils literal notranslate"><span class="pre">readnone</span></code></li>
+<li>bit 10: <code class="docutils literal notranslate"><span class="pre">readonly</span></code></li>
+<li>bit 11: <code class="docutils literal notranslate"><span class="pre">noinline</span></code></li>
+<li>bit 12: <code class="docutils literal notranslate"><span class="pre">alwaysinline</span></code></li>
+<li>bit 13: <code class="docutils literal notranslate"><span class="pre">optsize</span></code></li>
+<li>bit 14: <code class="docutils literal notranslate"><span class="pre">ssp</span></code></li>
+<li>bit 15: <code class="docutils literal notranslate"><span class="pre">sspreq</span></code></li>
+<li>bits 16-31: <code class="docutils literal notranslate"><span class="pre">align</span> <span class="pre">n</span></code></li>
+<li>bit 32: <code class="docutils literal notranslate"><span class="pre">nocapture</span></code></li>
+<li>bit 33: <code class="docutils literal notranslate"><span class="pre">noredzone</span></code></li>
+<li>bit 34: <code class="docutils literal notranslate"><span class="pre">noimplicitfloat</span></code></li>
+<li>bit 35: <code class="docutils literal notranslate"><span class="pre">naked</span></code></li>
+<li>bit 36: <code class="docutils literal notranslate"><span class="pre">inlinehint</span></code></li>
+<li>bits 37-39: <code class="docutils literal notranslate"><span class="pre">alignstack</span> <span class="pre">n</span></code>, represented as the logarithm
+base 2 of the requested alignment, plus 1</li>
+</ul>
+</div>
+</div>
+<div class="section" id="paramattr-group-block-contents">
+<span id="paramattr-group-block"></span><h3><a class="toc-backref" href="#id50">PARAMATTR_GROUP_BLOCK Contents</a><a class="headerlink" href="#paramattr-group-block-contents" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal notranslate"><span class="pre">PARAMATTR_GROUP_BLOCK</span></code> block (id 10) contains a table of entries
+describing the attribute groups present in the module. These entries can be
+referenced within <code class="docutils literal notranslate"><span class="pre">PARAMATTR_CODE_ENTRY</span></code> entries.</p>
+<div class="section" id="paramattr-grp-code-entry-record">
+<span id="paramattr-grp-code-entry"></span><h4><a class="toc-backref" href="#id51">PARAMATTR_GRP_CODE_ENTRY Record</a><a class="headerlink" href="#paramattr-grp-code-entry-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[ENTRY,</span> <span class="pre">grpid,</span> <span class="pre">paramidx,</span> <span class="pre">attr0,</span> <span class="pre">attr1,</span> <span class="pre">...]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">ENTRY</span></code> record (code 3) contains <em>grpid</em> and <em>paramidx</em> values, followed
+by a variable number of values describing a unique group of attributes. The
+<em>grpid</em> value is a unique key for the attribute group, which can be referenced
+within <code class="docutils literal notranslate"><span class="pre">PARAMATTR_CODE_ENTRY</span></code> entries. The <em>paramidx</em> value indicates which
+set of attributes is represented, with 0 representing the return value
+attributes, 0xFFFFFFFF representing function attributes, and other values
+representing 1-based function parameters.</p>
+<p>Each <em>attr</em> is itself represented as a variable number of values:</p>
+<p><code class="docutils literal notranslate"><span class="pre">kind,</span> <span class="pre">key</span> <span class="pre">[,</span> <span class="pre">...],</span> <span class="pre">[value</span> <span class="pre">[,</span> <span class="pre">...]]</span></code></p>
+<p>Each attribute is either a well-known LLVM attribute (possibly with an integer
+value associated with it), or an arbitrary string (possibly with an arbitrary
+string value associated with it). The <em>kind</em> value is an integer code
+distinguishing between these possibilities:</p>
+<ul class="simple">
+<li>code 0: well-known attribute</li>
+<li>code 1: well-known attribute with an integer value</li>
+<li>code 3: string attribute</li>
+<li>code 4: string attribute with a string value</li>
+</ul>
+<p>For well-known attributes (code 0 or 1), the <em>key</em> value is an integer code
+identifying the attribute. For attributes with an integer argument (code 1),
+the <em>value</em> value indicates the argument.</p>
+<p>For string attributes (code 3 or 4), the <em>key</em> value is actually a variable
+number of values representing the bytes of a null-terminated string. For
+attributes with a string argument (code 4), the <em>value</em> value is similarly a
+variable number of values representing the bytes of a null-terminated string.</p>
+<p>The integer codes are mapped to well-known attributes as follows.</p>
+<ul class="simple">
+<li>code 1: <code class="docutils literal notranslate"><span class="pre">align(<n>)</span></code></li>
+<li>code 2: <code class="docutils literal notranslate"><span class="pre">alwaysinline</span></code></li>
+<li>code 3: <code class="docutils literal notranslate"><span class="pre">byval</span></code></li>
+<li>code 4: <code class="docutils literal notranslate"><span class="pre">inlinehint</span></code></li>
+<li>code 5: <code class="docutils literal notranslate"><span class="pre">inreg</span></code></li>
+<li>code 6: <code class="docutils literal notranslate"><span class="pre">minsize</span></code></li>
+<li>code 7: <code class="docutils literal notranslate"><span class="pre">naked</span></code></li>
+<li>code 8: <code class="docutils literal notranslate"><span class="pre">nest</span></code></li>
+<li>code 9: <code class="docutils literal notranslate"><span class="pre">noalias</span></code></li>
+<li>code 10: <code class="docutils literal notranslate"><span class="pre">nobuiltin</span></code></li>
+<li>code 11: <code class="docutils literal notranslate"><span class="pre">nocapture</span></code></li>
+<li>code 12: <code class="docutils literal notranslate"><span class="pre">noduplicates</span></code></li>
+<li>code 13: <code class="docutils literal notranslate"><span class="pre">noimplicitfloat</span></code></li>
+<li>code 14: <code class="docutils literal notranslate"><span class="pre">noinline</span></code></li>
+<li>code 15: <code class="docutils literal notranslate"><span class="pre">nonlazybind</span></code></li>
+<li>code 16: <code class="docutils literal notranslate"><span class="pre">noredzone</span></code></li>
+<li>code 17: <code class="docutils literal notranslate"><span class="pre">noreturn</span></code></li>
+<li>code 18: <code class="docutils literal notranslate"><span class="pre">nounwind</span></code></li>
+<li>code 19: <code class="docutils literal notranslate"><span class="pre">optsize</span></code></li>
+<li>code 20: <code class="docutils literal notranslate"><span class="pre">readnone</span></code></li>
+<li>code 21: <code class="docutils literal notranslate"><span class="pre">readonly</span></code></li>
+<li>code 22: <code class="docutils literal notranslate"><span class="pre">returned</span></code></li>
+<li>code 23: <code class="docutils literal notranslate"><span class="pre">returns_twice</span></code></li>
+<li>code 24: <code class="docutils literal notranslate"><span class="pre">signext</span></code></li>
+<li>code 25: <code class="docutils literal notranslate"><span class="pre">alignstack(<n>)</span></code></li>
+<li>code 26: <code class="docutils literal notranslate"><span class="pre">ssp</span></code></li>
+<li>code 27: <code class="docutils literal notranslate"><span class="pre">sspreq</span></code></li>
+<li>code 28: <code class="docutils literal notranslate"><span class="pre">sspstrong</span></code></li>
+<li>code 29: <code class="docutils literal notranslate"><span class="pre">sret</span></code></li>
+<li>code 30: <code class="docutils literal notranslate"><span class="pre">sanitize_address</span></code></li>
+<li>code 31: <code class="docutils literal notranslate"><span class="pre">sanitize_thread</span></code></li>
+<li>code 32: <code class="docutils literal notranslate"><span class="pre">sanitize_memory</span></code></li>
+<li>code 33: <code class="docutils literal notranslate"><span class="pre">uwtable</span></code></li>
+<li>code 34: <code class="docutils literal notranslate"><span class="pre">zeroext</span></code></li>
+<li>code 35: <code class="docutils literal notranslate"><span class="pre">builtin</span></code></li>
+<li>code 36: <code class="docutils literal notranslate"><span class="pre">cold</span></code></li>
+<li>code 37: <code class="docutils literal notranslate"><span class="pre">optnone</span></code></li>
+<li>code 38: <code class="docutils literal notranslate"><span class="pre">inalloca</span></code></li>
+<li>code 39: <code class="docutils literal notranslate"><span class="pre">nonnull</span></code></li>
+<li>code 40: <code class="docutils literal notranslate"><span class="pre">jumptable</span></code></li>
+<li>code 41: <code class="docutils literal notranslate"><span class="pre">dereferenceable(<n>)</span></code></li>
+<li>code 42: <code class="docutils literal notranslate"><span class="pre">dereferenceable_or_null(<n>)</span></code></li>
+<li>code 43: <code class="docutils literal notranslate"><span class="pre">convergent</span></code></li>
+<li>code 44: <code class="docutils literal notranslate"><span class="pre">safestack</span></code></li>
+<li>code 45: <code class="docutils literal notranslate"><span class="pre">argmemonly</span></code></li>
+<li>code 46: <code class="docutils literal notranslate"><span class="pre">swiftself</span></code></li>
+<li>code 47: <code class="docutils literal notranslate"><span class="pre">swifterror</span></code></li>
+<li>code 48: <code class="docutils literal notranslate"><span class="pre">norecurse</span></code></li>
+<li>code 49: <code class="docutils literal notranslate"><span class="pre">inaccessiblememonly</span></code></li>
+<li>code 50: <code class="docutils literal notranslate"><span class="pre">inaccessiblememonly_or_argmemonly</span></code></li>
+<li>code 51: <code class="docutils literal notranslate"><span class="pre">allocsize(<EltSizeParam>[,</span> <span class="pre"><NumEltsParam>])</span></code></li>
+<li>code 52: <code class="docutils literal notranslate"><span class="pre">writeonly</span></code></li>
+<li>code 53: <code class="docutils literal notranslate"><span class="pre">speculatable</span></code></li>
+<li>code 54: <code class="docutils literal notranslate"><span class="pre">strictfp</span></code></li>
+<li>code 55: <code class="docutils literal notranslate"><span class="pre">sanitize_hwaddress</span></code></li>
+<li>code 56: <code class="docutils literal notranslate"><span class="pre">nocf_check</span></code></li>
+<li>code 57: <code class="docutils literal notranslate"><span class="pre">optforfuzzing</span></code></li>
+<li>code 58: <code class="docutils literal notranslate"><span class="pre">shadowcallstack</span></code></li>
+<li>code 64: <code class="docutils literal notranslate"><span class="pre">sanitize_memtag</span></code></li>
+</ul>
+<div class="admonition note">
+<p class="first admonition-title">Note</p>
+<p class="last">The <code class="docutils literal notranslate"><span class="pre">allocsize</span></code> attribute has a special encoding for its arguments. Its two
+arguments, which are 32-bit integers, are packed into one 64-bit integer value
+(i.e. <code class="docutils literal notranslate"><span class="pre">(EltSizeParam</span> <span class="pre"><<</span> <span class="pre">32)</span> <span class="pre">|</span> <span class="pre">NumEltsParam</span></code>), with <code class="docutils literal notranslate"><span class="pre">NumEltsParam</span></code> taking on
+the sentinel value -1 if it is not specified.</p>
+</div>
+</div>
+</div>
+<div class="section" id="type-block-contents">
+<span id="type-block"></span><h3><a class="toc-backref" href="#id52">TYPE_BLOCK Contents</a><a class="headerlink" href="#type-block-contents" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal notranslate"><span class="pre">TYPE_BLOCK</span></code> block (id 17) contains records which constitute a table of
+type operator entries used to represent types referenced within an LLVM
+module. Each record (with the exception of <a class="reference internal" href="#numentry">NUMENTRY</a>) generates a single type
+table entry, which may be referenced by 0-based index from instructions,
+constants, metadata, type symbol table entries, or other type operator records.</p>
+<p>Entries within <code class="docutils literal notranslate"><span class="pre">TYPE_BLOCK</span></code> are constructed to ensure that each entry is
+unique (i.e., no two indices represent structurally equivalent types).</p>
+<div class="section" id="type-code-numentry-record">
+<span id="numentry"></span><span id="type-code-numentry"></span><h4><a class="toc-backref" href="#id53">TYPE_CODE_NUMENTRY Record</a><a class="headerlink" href="#type-code-numentry-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[NUMENTRY,</span> <span class="pre">numentries]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">NUMENTRY</span></code> record (code 1) contains a single value which indicates the
+total number of type code entries in the type table of the module. If present,
+<code class="docutils literal notranslate"><span class="pre">NUMENTRY</span></code> should be the first record in the block.</p>
+</div>
+<div class="section" id="type-code-void-record">
+<h4><a class="toc-backref" href="#id54">TYPE_CODE_VOID Record</a><a class="headerlink" href="#type-code-void-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[VOID]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">VOID</span></code> record (code 2) adds a <code class="docutils literal notranslate"><span class="pre">void</span></code> type to the type table.</p>
+</div>
+<div class="section" id="type-code-half-record">
+<h4><a class="toc-backref" href="#id55">TYPE_CODE_HALF Record</a><a class="headerlink" href="#type-code-half-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[HALF]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">HALF</span></code> record (code 10) adds a <code class="docutils literal notranslate"><span class="pre">half</span></code> (16-bit floating point) type to
+the type table.</p>
+</div>
+<div class="section" id="type-code-float-record">
+<h4><a class="toc-backref" href="#id56">TYPE_CODE_FLOAT Record</a><a class="headerlink" href="#type-code-float-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[FLOAT]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">FLOAT</span></code> record (code 3) adds a <code class="docutils literal notranslate"><span class="pre">float</span></code> (32-bit floating point) type to
+the type table.</p>
+</div>
+<div class="section" id="type-code-double-record">
+<h4><a class="toc-backref" href="#id57">TYPE_CODE_DOUBLE Record</a><a class="headerlink" href="#type-code-double-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[DOUBLE]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">DOUBLE</span></code> record (code 4) adds a <code class="docutils literal notranslate"><span class="pre">double</span></code> (64-bit floating point) type to
+the type table.</p>
+</div>
+<div class="section" id="type-code-label-record">
+<h4><a class="toc-backref" href="#id58">TYPE_CODE_LABEL Record</a><a class="headerlink" href="#type-code-label-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[LABEL]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">LABEL</span></code> record (code 5) adds a <code class="docutils literal notranslate"><span class="pre">label</span></code> type to the type table.</p>
+</div>
+<div class="section" id="type-code-opaque-record">
+<h4><a class="toc-backref" href="#id59">TYPE_CODE_OPAQUE Record</a><a class="headerlink" href="#type-code-opaque-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[OPAQUE]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">OPAQUE</span></code> record (code 6) adds an <code class="docutils literal notranslate"><span class="pre">opaque</span></code> type to the type table, with
+a name defined by a previously encountered <code class="docutils literal notranslate"><span class="pre">STRUCT_NAME</span></code> record. Note that
+distinct <code class="docutils literal notranslate"><span class="pre">opaque</span></code> types are not unified.</p>
+</div>
+<div class="section" id="type-code-integer-record">
+<h4><a class="toc-backref" href="#id60">TYPE_CODE_INTEGER Record</a><a class="headerlink" href="#type-code-integer-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[INTEGER,</span> <span class="pre">width]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">INTEGER</span></code> record (code 7) adds an integer type to the type table. The
+single <em>width</em> field indicates the width of the integer type.</p>
+</div>
+<div class="section" id="type-code-pointer-record">
+<h4><a class="toc-backref" href="#id61">TYPE_CODE_POINTER Record</a><a class="headerlink" href="#type-code-pointer-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[POINTER,</span> <span class="pre">pointee</span> <span class="pre">type,</span> <span class="pre">address</span> <span class="pre">space]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">POINTER</span></code> record (code 8) adds a pointer type to the type table. The
+operand fields are</p>
+<ul class="simple">
+<li><em>pointee type</em>: The type index of the pointed-to type</li>
+<li><em>address space</em>: If supplied, the target-specific numbered address space where
+the pointed-to object resides. Otherwise, the default address space is zero.</li>
+</ul>
+</div>
+<div class="section" id="type-code-function-old-record">
+<h4><a class="toc-backref" href="#id62">TYPE_CODE_FUNCTION_OLD Record</a><a class="headerlink" href="#type-code-function-old-record" title="Permalink to this headline">¶</a></h4>
+<div class="admonition note">
+<p class="first admonition-title">Note</p>
+<p class="last">This is a legacy encoding for functions, produced by LLVM versions 3.0 and
+earlier. It is guaranteed to be understood by the current LLVM version, as
+specified in the <a class="reference internal" href="DeveloperPolicy.html#ir-backwards-compatibility"><span class="std std-ref">IR Backwards Compatibility</span></a> policy.</p>
+</div>
+<p><code class="docutils literal notranslate"><span class="pre">[FUNCTION_OLD,</span> <span class="pre">vararg,</span> <span class="pre">ignored,</span> <span class="pre">retty,</span> <span class="pre">...paramty...</span> <span class="pre">]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">FUNCTION_OLD</span></code> record (code 9) adds a function type to the type table.
+The operand fields are</p>
+<ul class="simple">
+<li><em>vararg</em>: Non-zero if the type represents a varargs function</li>
+<li><em>ignored</em>: This value field is present for backward compatibility only, and is
+ignored</li>
+<li><em>retty</em>: The type index of the functionâs return type</li>
+<li><em>paramty</em>: Zero or more type indices representing the parameter types of the
+function</li>
+</ul>
+</div>
+<div class="section" id="type-code-array-record">
+<h4><a class="toc-backref" href="#id63">TYPE_CODE_ARRAY Record</a><a class="headerlink" href="#type-code-array-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[ARRAY,</span> <span class="pre">numelts,</span> <span class="pre">eltty]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">ARRAY</span></code> record (code 11) adds an array type to the type table. The
+operand fields are</p>
+<ul class="simple">
+<li><em>numelts</em>: The number of elements in arrays of this type</li>
+<li><em>eltty</em>: The type index of the array element type</li>
+</ul>
+</div>
+<div class="section" id="type-code-vector-record">
+<h4><a class="toc-backref" href="#id64">TYPE_CODE_VECTOR Record</a><a class="headerlink" href="#type-code-vector-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[VECTOR,</span> <span class="pre">numelts,</span> <span class="pre">eltty]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">VECTOR</span></code> record (code 12) adds a vector type to the type table. The
+operand fields are</p>
+<ul class="simple">
+<li><em>numelts</em>: The number of elements in vectors of this type</li>
+<li><em>eltty</em>: The type index of the vector element type</li>
+</ul>
+</div>
+<div class="section" id="type-code-x86-fp80-record">
+<h4><a class="toc-backref" href="#id65">TYPE_CODE_X86_FP80 Record</a><a class="headerlink" href="#type-code-x86-fp80-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[X86_FP80]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">X86_FP80</span></code> record (code 13) adds an <code class="docutils literal notranslate"><span class="pre">x86_fp80</span></code> (80-bit floating point)
+type to the type table.</p>
+</div>
+<div class="section" id="type-code-fp128-record">
+<h4><a class="toc-backref" href="#id66">TYPE_CODE_FP128 Record</a><a class="headerlink" href="#type-code-fp128-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[FP128]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">FP128</span></code> record (code 14) adds an <code class="docutils literal notranslate"><span class="pre">fp128</span></code> (128-bit floating point) type
+to the type table.</p>
+</div>
+<div class="section" id="type-code-ppc-fp128-record">
+<h4><a class="toc-backref" href="#id67">TYPE_CODE_PPC_FP128 Record</a><a class="headerlink" href="#type-code-ppc-fp128-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[PPC_FP128]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">PPC_FP128</span></code> record (code 15) adds a <code class="docutils literal notranslate"><span class="pre">ppc_fp128</span></code> (128-bit floating point)
+type to the type table.</p>
+</div>
+<div class="section" id="type-code-metadata-record">
+<h4><a class="toc-backref" href="#id68">TYPE_CODE_METADATA Record</a><a class="headerlink" href="#type-code-metadata-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[METADATA]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">METADATA</span></code> record (code 16) adds a <code class="docutils literal notranslate"><span class="pre">metadata</span></code> type to the type table.</p>
+</div>
+<div class="section" id="type-code-x86-mmx-record">
+<h4><a class="toc-backref" href="#id69">TYPE_CODE_X86_MMX Record</a><a class="headerlink" href="#type-code-x86-mmx-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[X86_MMX]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">X86_MMX</span></code> record (code 17) adds an <code class="docutils literal notranslate"><span class="pre">x86_mmx</span></code> type to the type table.</p>
+</div>
+<div class="section" id="type-code-struct-anon-record">
+<h4><a class="toc-backref" href="#id70">TYPE_CODE_STRUCT_ANON Record</a><a class="headerlink" href="#type-code-struct-anon-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[STRUCT_ANON,</span> <span class="pre">ispacked,</span> <span class="pre">...eltty...]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">STRUCT_ANON</span></code> record (code 18) adds a literal struct type to the type
+table. The operand fields are</p>
+<ul class="simple">
+<li><em>ispacked</em>: Non-zero if the type represents a packed structure</li>
+<li><em>eltty</em>: Zero or more type indices representing the element types of the
+structure</li>
+</ul>
+</div>
+<div class="section" id="type-code-struct-name-record">
+<h4><a class="toc-backref" href="#id71">TYPE_CODE_STRUCT_NAME Record</a><a class="headerlink" href="#type-code-struct-name-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[STRUCT_NAME,</span> <span class="pre">...string...]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">STRUCT_NAME</span></code> record (code 19) contains a variable number of values
+representing the bytes of a struct name. The next <code class="docutils literal notranslate"><span class="pre">OPAQUE</span></code> or
+<code class="docutils literal notranslate"><span class="pre">STRUCT_NAMED</span></code> record will use this name.</p>
+</div>
+<div class="section" id="type-code-struct-named-record">
+<h4><a class="toc-backref" href="#id72">TYPE_CODE_STRUCT_NAMED Record</a><a class="headerlink" href="#type-code-struct-named-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[STRUCT_NAMED,</span> <span class="pre">ispacked,</span> <span class="pre">...eltty...]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">STRUCT_NAMED</span></code> record (code 20) adds an identified struct type to the
+type table, with a name defined by a previously encountered <code class="docutils literal notranslate"><span class="pre">STRUCT_NAME</span></code>
+record. The operand fields are</p>
+<ul class="simple">
+<li><em>ispacked</em>: Non-zero if the type represents a packed structure</li>
+<li><em>eltty</em>: Zero or more type indices representing the element types of the
+structure</li>
+</ul>
+</div>
+<div class="section" id="type-code-function-record">
+<h4><a class="toc-backref" href="#id73">TYPE_CODE_FUNCTION Record</a><a class="headerlink" href="#type-code-function-record" title="Permalink to this headline">¶</a></h4>
+<p><code class="docutils literal notranslate"><span class="pre">[FUNCTION,</span> <span class="pre">vararg,</span> <span class="pre">retty,</span> <span class="pre">...paramty...</span> <span class="pre">]</span></code></p>
+<p>The <code class="docutils literal notranslate"><span class="pre">FUNCTION</span></code> record (code 21) adds a function type to the type table. The
+operand fields are</p>
+<ul class="simple">
+<li><em>vararg</em>: Non-zero if the type represents a varargs function</li>
+<li><em>retty</em>: The type index of the functionâs return type</li>
+<li><em>paramty</em>: Zero or more type indices representing the parameter types of the
+function</li>
+</ul>
+</div>
+</div>
+<div class="section" id="constants-block-contents">
+<span id="constants-block"></span><h3><a class="toc-backref" href="#id74">CONSTANTS_BLOCK Contents</a><a class="headerlink" href="#constants-block-contents" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal notranslate"><span class="pre">CONSTANTS_BLOCK</span></code> block (id 11) â¦</p>
+</div>
+<div class="section" id="function-block-contents">
+<span id="function-block"></span><h3><a class="toc-backref" href="#id75">FUNCTION_BLOCK Contents</a><a class="headerlink" href="#function-block-contents" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal notranslate"><span class="pre">FUNCTION_BLOCK</span></code> block (id 12) â¦</p>
+<p>In addition to the record types described below, a <code class="docutils literal notranslate"><span class="pre">FUNCTION_BLOCK</span></code> block may
+contain the following sub-blocks:</p>
+<ul class="simple">
+<li><a class="reference internal" href="#constants-block">CONSTANTS_BLOCK</a></li>
+<li><a class="reference internal" href="#value-symtab-block">VALUE_SYMTAB_BLOCK</a></li>
+<li><a class="reference internal" href="#metadata-attachment">METADATA_ATTACHMENT</a></li>
+</ul>
+</div>
+<div class="section" id="value-symtab-block-contents">
+<span id="value-symtab-block"></span><h3><a class="toc-backref" href="#id76">VALUE_SYMTAB_BLOCK Contents</a><a class="headerlink" href="#value-symtab-block-contents" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal notranslate"><span class="pre">VALUE_SYMTAB_BLOCK</span></code> block (id 14) â¦</p>
+</div>
+<div class="section" id="metadata-block-contents">
+<span id="metadata-block"></span><h3><a class="toc-backref" href="#id77">METADATA_BLOCK Contents</a><a class="headerlink" href="#metadata-block-contents" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal notranslate"><span class="pre">METADATA_BLOCK</span></code> block (id 15) â¦</p>
+</div>
+<div class="section" id="metadata-attachment-contents">
+<span id="metadata-attachment"></span><h3><a class="toc-backref" href="#id78">METADATA_ATTACHMENT Contents</a><a class="headerlink" href="#metadata-attachment-contents" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal notranslate"><span class="pre">METADATA_ATTACHMENT</span></code> block (id 16) â¦</p>
+</div>
+<div class="section" id="strtab-block-contents">
+<span id="strtab-block"></span><h3><a class="toc-backref" href="#id79">STRTAB_BLOCK Contents</a><a class="headerlink" href="#strtab-block-contents" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal notranslate"><span class="pre">STRTAB</span></code> block (id 23) contains a single record (<code class="docutils literal notranslate"><span class="pre">STRTAB_BLOB</span></code>, id 1)
+with a single blob operand containing the bitcode fileâs string table.</p>
+<p>Strings in the string table are not null terminated. A recordâs <em>strtab
+offset</em> and <em>strtab size</em> operands specify the byte offset and size of a
+string within the string table.</p>
+<p>The string table is used by all preceding blocks in the bitcode file that are
+not succeeded by another intervening <code class="docutils literal notranslate"><span class="pre">STRTAB</span></code> block. Normally a bitcode
+file will have a single string table, but it may have more than one if it
+was created by binary concatenation of multiple bitcode files.</p>
+</div>
+</div>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="BlockFrequencyTerminology.html" title="LLVM Block Frequency Terminology"
+ >next</a> |</li>
+ <li class="right" >
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+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
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+ Last updated on 2019-09-19.
+ Created using <a href="http://sphinx-doc.org/">Sphinx</a> 1.8.4.
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+</html>
\ No newline at end of file
Added: www-releases/trunk/9.0.0/docs/BlockFrequencyTerminology.html
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==============================================================================
--- www-releases/trunk/9.0.0/docs/BlockFrequencyTerminology.html (added)
+++ www-releases/trunk/9.0.0/docs/BlockFrequencyTerminology.html Thu Sep 19 07:32:46 2019
@@ -0,0 +1,205 @@
+
+
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
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+ <meta http-equiv="X-UA-Compatible" content="IE=Edge" />
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+ <title>LLVM Block Frequency Terminology — LLVM 9 documentation</title>
+ <link rel="stylesheet" href="_static/llvm-theme.css" type="text/css" />
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+ <script type="text/javascript" src="_static/jquery.js"></script>
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+ <link rel="index" title="Index" href="genindex.html" />
+ <link rel="search" title="Search" href="search.html" />
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+<style type="text/css">
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+ table.right td { border: 1px solid #ccc; }
+</style>
+
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+<div class="logo">
+ <a href="index.html">
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+ alt="LLVM Logo" width="250" height="88"/></a>
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+ <div class="document">
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+ <div class="body" role="main">
+
+ <div class="section" id="llvm-block-frequency-terminology">
+<h1>LLVM Block Frequency Terminology<a class="headerlink" href="#llvm-block-frequency-terminology" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#introduction" id="id1">Introduction</a></li>
+<li><a class="reference internal" href="#branch-probability" id="id2">Branch Probability</a></li>
+<li><a class="reference internal" href="#branch-weight" id="id3">Branch Weight</a></li>
+<li><a class="reference internal" href="#block-frequency" id="id4">Block Frequency</a></li>
+<li><a class="reference internal" href="#implementation-a-series-of-dags" id="id5">Implementation: a series of DAGs</a></li>
+<li><a class="reference internal" href="#block-mass" id="id6">Block Mass</a></li>
+<li><a class="reference internal" href="#loop-scale" id="id7">Loop Scale</a></li>
+<li><a class="reference internal" href="#implementation-getting-from-mass-and-scale-to-frequency" id="id8">Implementation: Getting from mass and scale to frequency</a></li>
+<li><a class="reference internal" href="#block-bias" id="id9">Block Bias</a></li>
+</ul>
+</div>
+<div class="section" id="introduction">
+<h2><a class="toc-backref" href="#id1">Introduction</a><a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
+<p>Block Frequency is a metric for estimating the relative frequency of different
+basic blocks. This document describes the terminology that the
+<code class="docutils literal notranslate"><span class="pre">BlockFrequencyInfo</span></code> and <code class="docutils literal notranslate"><span class="pre">MachineBlockFrequencyInfo</span></code> analysis passes use.</p>
+</div>
+<div class="section" id="branch-probability">
+<h2><a class="toc-backref" href="#id2">Branch Probability</a><a class="headerlink" href="#branch-probability" title="Permalink to this headline">¶</a></h2>
+<p>Blocks with multiple successors have probabilities associated with each
+outgoing edge. These are called branch probabilities. For a given block, the
+sum of its outgoing branch probabilities should be 1.0.</p>
+</div>
+<div class="section" id="branch-weight">
+<h2><a class="toc-backref" href="#id3">Branch Weight</a><a class="headerlink" href="#branch-weight" title="Permalink to this headline">¶</a></h2>
+<p>Rather than storing fractions on each edge, we store an integer weight.
+Weights are relative to the other edges of a given predecessor block. The
+branch probability associated with a given edge is its own weight divided by
+the sum of the weights on the predecessorâs outgoing edges.</p>
+<p>For example, consider this IR:</p>
+<div class="highlight-llvm notranslate"><div class="highlight"><pre><span></span><span class="k">define</span> <span class="kt">void</span> <span class="vg">@foo</span><span class="p">()</span> <span class="p">{</span>
+ <span class="c">; ...</span>
+ <span class="nl">A:</span>
+ <span class="k">br</span> <span class="k">i1</span> <span class="nv">%cond</span><span class="p">,</span> <span class="kt">label</span> <span class="nv">%B</span><span class="p">,</span> <span class="kt">label</span> <span class="nv">%C</span><span class="p">,</span> <span class="nv">!prof</span> <span class="nv nv-Anonymous">!0</span>
+ <span class="c">; ...</span>
+<span class="p">}</span>
+<span class="nv nv-Anonymous">!0</span> <span class="p">=</span> <span class="kt">metadata</span> <span class="p">!{</span><span class="kt">metadata</span> <span class="nv">!"branch_weights"</span><span class="p">,</span> <span class="k">i32</span> <span class="m">7</span><span class="p">,</span> <span class="k">i32</span> <span class="m">8</span><span class="p">}</span>
+</pre></div>
+</div>
+<p>and this simple graph representation:</p>
+<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">A</span> <span class="o">-></span> <span class="n">B</span> <span class="p">(</span><span class="n">edge</span><span class="o">-</span><span class="n">weight</span><span class="p">:</span> <span class="mi">7</span><span class="p">)</span>
+<span class="n">A</span> <span class="o">-></span> <span class="n">C</span> <span class="p">(</span><span class="n">edge</span><span class="o">-</span><span class="n">weight</span><span class="p">:</span> <span class="mi">8</span><span class="p">)</span>
+</pre></div>
+</div>
+<p>The probability of branching from block A to block B is 7/15, and the
+probability of branching from block A to block C is 8/15.</p>
+<p>See <a class="reference internal" href="BranchWeightMetadata.html"><span class="doc">LLVM Branch Weight Metadata</span></a> for details about the branch weight IR
+representation.</p>
+</div>
+<div class="section" id="block-frequency">
+<h2><a class="toc-backref" href="#id4">Block Frequency</a><a class="headerlink" href="#block-frequency" title="Permalink to this headline">¶</a></h2>
+<p>Block frequency is a relative metric that represents the number of times a
+block executes. The ratio of a block frequency to the entry block frequency is
+the expected number of times the block will execute per entry to the function.</p>
+<p>Block frequency is the main output of the <code class="docutils literal notranslate"><span class="pre">BlockFrequencyInfo</span></code> and
+<code class="docutils literal notranslate"><span class="pre">MachineBlockFrequencyInfo</span></code> analysis passes.</p>
+</div>
+<div class="section" id="implementation-a-series-of-dags">
+<h2><a class="toc-backref" href="#id5">Implementation: a series of DAGs</a><a class="headerlink" href="#implementation-a-series-of-dags" title="Permalink to this headline">¶</a></h2>
+<p>The implementation of the block frequency calculation analyses each loop,
+bottom-up, ignoring backedges; i.e., as a DAG. After each loop is processed,
+itâs packaged up to act as a pseudo-node in its parent loopâs (or the
+functionâs) DAG analysis.</p>
+</div>
+<div class="section" id="block-mass">
+<h2><a class="toc-backref" href="#id6">Block Mass</a><a class="headerlink" href="#block-mass" title="Permalink to this headline">¶</a></h2>
+<p>For each DAG, the entry node is assigned a mass of <code class="docutils literal notranslate"><span class="pre">UINT64_MAX</span></code> and mass is
+distributed to successors according to branch weights. Block Mass uses a
+fixed-point representation where <code class="docutils literal notranslate"><span class="pre">UINT64_MAX</span></code> represents <code class="docutils literal notranslate"><span class="pre">1.0</span></code> and <code class="docutils literal notranslate"><span class="pre">0</span></code>
+represents a number just above <code class="docutils literal notranslate"><span class="pre">0.0</span></code>.</p>
+<p>After mass is fully distributed, in any cut of the DAG that separates the exit
+nodes from the entry node, the sum of the block masses of the nodes succeeded
+by a cut edge should equal <code class="docutils literal notranslate"><span class="pre">UINT64_MAX</span></code>. In other words, mass is conserved
+as it âfallsâ through the DAG.</p>
+<p>If a functionâs basic block graph is a DAG, then block masses are valid block
+frequencies. This works poorly in practise though, since downstream users rely
+on adding block frequencies together without hitting the maximum.</p>
+</div>
+<div class="section" id="loop-scale">
+<h2><a class="toc-backref" href="#id7">Loop Scale</a><a class="headerlink" href="#loop-scale" title="Permalink to this headline">¶</a></h2>
+<p>Loop scale is a metric that indicates how many times a loop iterates per entry.
+As mass is distributed through the loopâs DAG, the (otherwise ignored) backedge
+mass is collected. This backedge mass is used to compute the exit frequency,
+and thus the loop scale.</p>
+</div>
+<div class="section" id="implementation-getting-from-mass-and-scale-to-frequency">
+<h2><a class="toc-backref" href="#id8">Implementation: Getting from mass and scale to frequency</a><a class="headerlink" href="#implementation-getting-from-mass-and-scale-to-frequency" title="Permalink to this headline">¶</a></h2>
+<p>After analysing the complete series of DAGs, each block has a mass (local to
+its containing loop, if any), and each loop pseudo-node has a loop scale and
+its own mass (from its parentâs DAG).</p>
+<p>We can get an initial frequency assignment (with entry frequency of 1.0) by
+multiplying these masses and loop scales together. A given blockâs frequency
+is the product of its mass, the mass of containing loopsâ pseudo nodes, and the
+containing loopsâ loop scales.</p>
+<p>Since downstream users need integers (not floating point), this initial
+frequency assignment is shifted as necessary into the range of <code class="docutils literal notranslate"><span class="pre">uint64_t</span></code>.</p>
+</div>
+<div class="section" id="block-bias">
+<h2><a class="toc-backref" href="#id9">Block Bias</a><a class="headerlink" href="#block-bias" title="Permalink to this headline">¶</a></h2>
+<p>Block bias is a proposed <em>absolute</em> metric to indicate a bias toward or away
+from a given block during a functionâs execution. The idea is that bias can be
+used in isolation to indicate whether a block is relatively hot or cold, or to
+compare two blocks to indicate whether one is hotter or colder than the other.</p>
+<p>The proposed calculation involves calculating a <em>reference</em> block frequency,
+where:</p>
+<ul class="simple">
+<li>every branch weight is assumed to be 1 (i.e., every branch probability
+distribution is even) and</li>
+<li>loop scales are ignored.</li>
+</ul>
+<p>This reference frequency represents what the block frequency would be in an
+unbiased graph.</p>
+<p>The bias is the ratio of the block frequency to this reference block frequency.</p>
+</div>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
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+
+ <div class="section" id="llvm-branch-weight-metadata">
+<h1>LLVM Branch Weight Metadata<a class="headerlink" href="#llvm-branch-weight-metadata" title="Permalink to this headline">¶</a></h1>
+<div class="contents local topic" id="contents">
+<ul class="simple">
+<li><a class="reference internal" href="#introduction" id="id1">Introduction</a></li>
+<li><a class="reference internal" href="#supported-instructions" id="id2">Supported Instructions</a><ul>
+<li><a class="reference internal" href="#branchinst" id="id3"><code class="docutils literal notranslate"><span class="pre">BranchInst</span></code></a></li>
+<li><a class="reference internal" href="#switchinst" id="id4"><code class="docutils literal notranslate"><span class="pre">SwitchInst</span></code></a></li>
+<li><a class="reference internal" href="#indirectbrinst" id="id5"><code class="docutils literal notranslate"><span class="pre">IndirectBrInst</span></code></a></li>
+<li><a class="reference internal" href="#callinst" id="id6"><code class="docutils literal notranslate"><span class="pre">CallInst</span></code></a></li>
+<li><a class="reference internal" href="#other" id="id7">Other</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#built-in-expect-instructions" id="id8">Built-in <code class="docutils literal notranslate"><span class="pre">expect</span></code> Instructions</a><ul>
+<li><a class="reference internal" href="#if-statement" id="id9"><code class="docutils literal notranslate"><span class="pre">if</span></code> statement</a></li>
+<li><a class="reference internal" href="#switch-statement" id="id10"><code class="docutils literal notranslate"><span class="pre">switch</span></code> statement</a></li>
+</ul>
+</li>
+<li><a class="reference internal" href="#cfg-modifications" id="id11">CFG Modifications</a></li>
+<li><a class="reference internal" href="#function-entry-counts" id="id12">Function Entry Counts</a></li>
+</ul>
+</div>
+<div class="section" id="introduction">
+<h2><a class="toc-backref" href="#id1">Introduction</a><a class="headerlink" href="#introduction" title="Permalink to this headline">¶</a></h2>
+<p>Branch Weight Metadata represents branch weights as its likeliness to be taken
+(see <a class="reference internal" href="BlockFrequencyTerminology.html"><span class="doc">LLVM Block Frequency Terminology</span></a>). Metadata is assigned to an
+<code class="docutils literal notranslate"><span class="pre">Instruction</span></code> that is a terminator as a <code class="docutils literal notranslate"><span class="pre">MDNode</span></code> of the <code class="docutils literal notranslate"><span class="pre">MD_prof</span></code> kind.
+The first operator is always a <code class="docutils literal notranslate"><span class="pre">MDString</span></code> node with the string
+âbranch_weightsâ. Number of operators depends on the terminator type.</p>
+<p>Branch weights might be fetch from the profiling file, or generated based on
+<a class="reference internal" href="#builtin-expect">__builtin_expect</a> instruction.</p>
+<p>All weights are represented as an unsigned 32-bit values, where higher value
+indicates greater chance to be taken.</p>
+</div>
+<div class="section" id="supported-instructions">
+<h2><a class="toc-backref" href="#id2">Supported Instructions</a><a class="headerlink" href="#supported-instructions" title="Permalink to this headline">¶</a></h2>
+<div class="section" id="branchinst">
+<h3><a class="toc-backref" href="#id3"><code class="docutils literal notranslate"><span class="pre">BranchInst</span></code></a><a class="headerlink" href="#branchinst" title="Permalink to this headline">¶</a></h3>
+<p>Metadata is only assigned to the conditional branches. There are two extra
+operands for the true and the false branch.</p>
+<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>!0 = metadata !{
+ metadata !"branch_weights",
+ i32 <TRUE_BRANCH_WEIGHT>,
+ i32 <FALSE_BRANCH_WEIGHT>
+}
+</pre></div>
+</div>
+</div>
+<div class="section" id="switchinst">
+<h3><a class="toc-backref" href="#id4"><code class="docutils literal notranslate"><span class="pre">SwitchInst</span></code></a><a class="headerlink" href="#switchinst" title="Permalink to this headline">¶</a></h3>
+<p>Branch weights are assigned to every case (including the <code class="docutils literal notranslate"><span class="pre">default</span></code> case which
+is always case #0).</p>
+<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>!0 = metadata !{
+ metadata !"branch_weights",
+ i32 <DEFAULT_BRANCH_WEIGHT>
+ [ , i32 <CASE_BRANCH_WEIGHT> ... ]
+}
+</pre></div>
+</div>
+</div>
+<div class="section" id="indirectbrinst">
+<h3><a class="toc-backref" href="#id5"><code class="docutils literal notranslate"><span class="pre">IndirectBrInst</span></code></a><a class="headerlink" href="#indirectbrinst" title="Permalink to this headline">¶</a></h3>
+<p>Branch weights are assigned to every destination.</p>
+<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>!0 = metadata !{
+ metadata !"branch_weights",
+ i32 <LABEL_BRANCH_WEIGHT>
+ [ , i32 <LABEL_BRANCH_WEIGHT> ... ]
+}
+</pre></div>
+</div>
+</div>
+<div class="section" id="callinst">
+<h3><a class="toc-backref" href="#id6"><code class="docutils literal notranslate"><span class="pre">CallInst</span></code></a><a class="headerlink" href="#callinst" title="Permalink to this headline">¶</a></h3>
+<p>Calls may have branch weight metadata, containing the execution count of
+the call. It is currently used in SamplePGO mode only, to augment the
+block and entry counts which may not be accurate with sampling.</p>
+<div class="highlight-none notranslate"><div class="highlight"><pre><span></span>!0 = metadata !{
+ metadata !"branch_weights",
+ i32 <CALL_BRANCH_WEIGHT>
+}
+</pre></div>
+</div>
+</div>
+<div class="section" id="other">
+<h3><a class="toc-backref" href="#id7">Other</a><a class="headerlink" href="#other" title="Permalink to this headline">¶</a></h3>
+<p>Other terminator instructions are not allowed to contain Branch Weight Metadata.</p>
+</div>
+</div>
+<div class="section" id="built-in-expect-instructions">
+<span id="builtin-expect"></span><h2><a class="toc-backref" href="#id8">Built-in <code class="docutils literal notranslate"><span class="pre">expect</span></code> Instructions</a><a class="headerlink" href="#built-in-expect-instructions" title="Permalink to this headline">¶</a></h2>
+<p><code class="docutils literal notranslate"><span class="pre">__builtin_expect(long</span> <span class="pre">exp,</span> <span class="pre">long</span> <span class="pre">c)</span></code> instruction provides branch prediction
+information. The return value is the value of <code class="docutils literal notranslate"><span class="pre">exp</span></code>.</p>
+<p>It is especially useful in conditional statements. Currently Clang supports two
+conditional statements:</p>
+<div class="section" id="if-statement">
+<h3><a class="toc-backref" href="#id9"><code class="docutils literal notranslate"><span class="pre">if</span></code> statement</a><a class="headerlink" href="#if-statement" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal notranslate"><span class="pre">exp</span></code> parameter is the condition. The <code class="docutils literal notranslate"><span class="pre">c</span></code> parameter is the expected
+comparison value. If it is equal to 1 (true), the condition is likely to be
+true, in other case condition is likely to be false. For example:</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">if</span> <span class="p">(</span><span class="n">__builtin_expect</span><span class="p">(</span><span class="n">x</span> <span class="o">></span> <span class="mi">0</span><span class="p">,</span> <span class="mi">1</span><span class="p">))</span> <span class="p">{</span>
+ <span class="c1">// This block is likely to be taken.</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+</div>
+<div class="section" id="switch-statement">
+<h3><a class="toc-backref" href="#id10"><code class="docutils literal notranslate"><span class="pre">switch</span></code> statement</a><a class="headerlink" href="#switch-statement" title="Permalink to this headline">¶</a></h3>
+<p>The <code class="docutils literal notranslate"><span class="pre">exp</span></code> parameter is the value. The <code class="docutils literal notranslate"><span class="pre">c</span></code> parameter is the expected
+value. If the expected value doesnât show on the cases list, the <code class="docutils literal notranslate"><span class="pre">default</span></code>
+case is assumed to be likely taken.</p>
+<div class="highlight-c++ notranslate"><div class="highlight"><pre><span></span><span class="k">switch</span> <span class="p">(</span><span class="n">__builtin_expect</span><span class="p">(</span><span class="n">x</span><span class="p">,</span> <span class="mi">5</span><span class="p">))</span> <span class="p">{</span>
+<span class="k">default</span><span class="o">:</span> <span class="k">break</span><span class="p">;</span>
+<span class="k">case</span> <span class="mi">0</span><span class="o">:</span> <span class="c1">// ...</span>
+<span class="k">case</span> <span class="mi">3</span><span class="o">:</span> <span class="c1">// ...</span>
+<span class="k">case</span> <span class="mi">5</span><span class="o">:</span> <span class="c1">// This case is likely to be taken.</span>
+<span class="p">}</span>
+</pre></div>
+</div>
+</div>
+</div>
+<div class="section" id="cfg-modifications">
+<h2><a class="toc-backref" href="#id11">CFG Modifications</a><a class="headerlink" href="#cfg-modifications" title="Permalink to this headline">¶</a></h2>
+<p>Branch Weight Metatada is not proof against CFG changes. If terminator operandsâ
+are changed some action should be taken. In other case some misoptimizations may
+occur due to incorrect branch prediction information.</p>
+</div>
+<div class="section" id="function-entry-counts">
+<h2><a class="toc-backref" href="#id12">Function Entry Counts</a><a class="headerlink" href="#function-entry-counts" title="Permalink to this headline">¶</a></h2>
+<p>To allow comparing different functions during inter-procedural analysis and
+optimization, <code class="docutils literal notranslate"><span class="pre">MD_prof</span></code> nodes can also be assigned to a function definition.
+The first operand is a string indicating the name of the associated counter.</p>
+<p>Currently, one counter is supported: âfunction_entry_countâ. The second operand
+is a 64-bit counter that indicates the number of times that this function was
+invoked (in the case of instrumentation-based profiles). In the case of
+sampling-based profiles, this operand is an approximation of how many times
+the function was invoked.</p>
+<p>For example, in the code below, the instrumentation for function foo()
+indicates that it was called 2,590 times at runtime.</p>
+<div class="highlight-llvm notranslate"><div class="highlight"><pre><span></span><span class="k">define</span> <span class="k">i32</span> <span class="vg">@foo</span><span class="p">()</span> <span class="nv">!prof</span> <span class="nv nv-Anonymous">!1</span> <span class="p">{</span>
+ <span class="k">ret</span> <span class="k">i32</span> <span class="m">0</span>
+<span class="p">}</span>
+<span class="nv nv-Anonymous">!1</span> <span class="p">=</span> <span class="p">!{</span><span class="nv">!"function_entry_count"</span><span class="p">,</span> <span class="k">i64</span> <span class="m">2590</span><span class="p">}</span>
+</pre></div>
+</div>
+<p>If âfunction_entry_countâ has more than 2 operands, the later operands are
+the GUID of the functions that needs to be imported by ThinLTO. This is only
+set by sampling based profile. It is needed because the sampling based profile
+was collected on a binary that had already imported and inlined these functions,
+and we need to ensure the IR matches in the ThinLTO backends for profile
+annotation. The reason why we cannot annotate this on the callsite is that it
+can only goes down 1 level in the call chain. For the cases where
+foo_in_a_cc()->bar_in_b_cc()->baz_in_c_cc(), we will need to go down 2 levels
+in the call chain to import both bar_in_b_cc and baz_in_c_cc.</p>
+</div>
+</div>
+
+
+ </div>
+ </div>
+ <div class="clearer"></div>
+ </div>
+ <div class="related" role="navigation" aria-label="related navigation">
+ <h3>Navigation</h3>
+ <ul>
+ <li class="right" style="margin-right: 10px">
+ <a href="genindex.html" title="General Index"
+ >index</a></li>
+ <li class="right" >
+ <a href="Bugpoint.html" title="LLVM bugpoint tool: design and usage"
+ >next</a> |</li>
+ <li class="right" >
+ <a href="BlockFrequencyTerminology.html" title="LLVM Block Frequency Terminology"
+ >previous</a> |</li>
+ <li><a href="http://llvm.org/">LLVM Home</a> | </li>
+ <li><a href="index.html">Documentation</a>»</li>
+
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