[PATCH] D66773: [TableGen] Emit OperandType enums for RegisterOperands/RegisterClasses

[Nicolas Guillemot via Phabricator via llvm-commits]

nlguillemot updated this revision to Diff 220743.
nlguillemot added a comment.

Refactored loop over the list of vectors to avoid the tricky array/pointer loops.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66773/new/

https://reviews.llvm.org/D66773

Files:
  test/TableGen/get-operand-type.td
  utils/TableGen/InstrInfoEmitter.cpp


Index: utils/TableGen/InstrInfoEmitter.cpp
===================================================================
--- utils/TableGen/InstrInfoEmitter.cpp
+++ utils/TableGen/InstrInfoEmitter.cpp
@@ -332,6 +332,10 @@
 
   StringRef Namespace = Target.getInstNamespace();
   std::vector<Record *> Operands = Records.getAllDerivedDefinitions("Operand");
+  std::vector<Record *> RegisterOperands =
+      Records.getAllDerivedDefinitions("RegisterOperand");
+  std::vector<Record *> RegisterClasses =
+      Records.getAllDerivedDefinitions("RegisterClass");
 
   OS << "#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
   OS << "#undef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
@@ -341,10 +345,13 @@
   OS << "enum OperandType {\n";
 
   unsigned EnumVal = 0;
-  for (const Record *Op : Operands) {
-    if (!Op->isAnonymous())
-      OS << "  " << Op->getName() << " = " << EnumVal << ",\n";
-    ++EnumVal;
+  for (const std::vector<Record *> *RecordsToAdd :
+       {&Operands, &RegisterOperands, &RegisterClasses}) {
+    for (const Record *Op : *RecordsToAdd) {
+      if (!Op->isAnonymous())
+        OS << "  " << Op->getName() << " = " << EnumVal << ",\n";
+      ++EnumVal;
+    }
   }
 
   OS << "  OPERAND_TYPE_LIST_END" << "\n};\n";
@@ -358,7 +365,8 @@
   OS << "namespace llvm {\n";
   OS << "namespace " << Namespace << " {\n";
   OS << "LLVM_READONLY\n";
-  OS << "int getOperandType(uint16_t Opcode, uint16_t OpIdx) {\n";
+  OS << "static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {\n";
+  // TODO: Factor out instructions with same operands to compress the tables.
   if (!NumberedInstructions.empty()) {
     std::vector<int> OperandOffsets;
     std::vector<Record *> OperandRecords;
@@ -399,7 +407,10 @@
           OS << "/**/\n    ";
       }
       Record *OpR = OperandRecords[I];
-      if (OpR->isSubClassOf("Operand") && !OpR->isAnonymous())
+      if ((OpR->isSubClassOf("Operand") ||
+           OpR->isSubClassOf("RegisterOperand") ||
+           OpR->isSubClassOf("RegisterClass")) &&
+          !OpR->isAnonymous())
         OS << "OpTypes::" << OpR->getName();
       else
         OS << -1;
@@ -414,7 +425,7 @@
   OS << "}\n";
   OS << "} // end namespace " << Namespace << "\n";
   OS << "} // end namespace llvm\n";
-  OS << "#endif //GET_INSTRINFO_OPERAND_TYPE\n\n";
+  OS << "#endif // GET_INSTRINFO_OPERAND_TYPE\n\n";
 }
 
 void InstrInfoEmitter::emitMCIIHelperMethods(raw_ostream &OS,
Index: test/TableGen/get-operand-type.td
===================================================================
--- test/TableGen/get-operand-type.td
+++ test/TableGen/get-operand-type.td
@@ -16,6 +16,8 @@
 def OpA : Operand<i32>;
 def OpB : Operand<i32>;
 
+def RegOp : RegisterOperand<RegClass>;
+
 def InstA : Instruction {
   let Size = 1;
   let OutOperandList = (outs OpA:$a);
@@ -34,7 +36,17 @@
   let Namespace = "MyNamespace";
 }
 
+def InstC : Instruction {
+  let Size = 1;
+  let OutOperandList = (outs RegClass:$d);
+  let InOperandList = (ins RegOp:$x);
+  field bits<8> Inst;
+  field bits<8> SoftFail = 0;
+  let Namespace = "MyNamespace";
+}
+
 // CHECK: #ifdef GET_INSTRINFO_OPERAND_TYPE
 // CHECK:        OpTypes::OpA, OpTypes::OpB, OpTypes::i32imm,
 // CHECK-NEXT:   OpTypes::i32imm, -1,
-// CHECK: #endif //GET_INSTRINFO_OPERAND_TYPE
+// CHECK-NEXT:   OpTypes::RegClass, OpTypes::RegOp,
+// CHECK: #endif // GET_INSTRINFO_OPERAND_TYPE


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