[PATCH] D67698: [RISCV] Remove RA from reserved register to use as callee saved register

[Shiva Chen via Phabricator via llvm-commits]

shiva0217 created this revision.
shiva0217 added reviewers: asb, lenary, luismarques.
Herald added subscribers: pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar.
Herald added a project: LLVM.

Remove RA from reserved register list, so we could use it as callee saved register


Repository:
  rL LLVM

https://reviews.llvm.org/D67698

Files:
  lib/Target/RISCV/RISCVRegisterInfo.cpp
  test/CodeGen/RISCV/callee-saved-gprs.ll


Index: test/CodeGen/RISCV/callee-saved-gprs.ll
===================================================================
--- test/CodeGen/RISCV/callee-saved-gprs.ll
+++ test/CodeGen/RISCV/callee-saved-gprs.ll
@@ -28,18 +28,19 @@
 ; RV32I-LABEL: callee:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -80
-; RV32I-NEXT:    sw s0, 76(sp)
-; RV32I-NEXT:    sw s1, 72(sp)
-; RV32I-NEXT:    sw s2, 68(sp)
-; RV32I-NEXT:    sw s3, 64(sp)
-; RV32I-NEXT:    sw s4, 60(sp)
-; RV32I-NEXT:    sw s5, 56(sp)
-; RV32I-NEXT:    sw s6, 52(sp)
-; RV32I-NEXT:    sw s7, 48(sp)
-; RV32I-NEXT:    sw s8, 44(sp)
-; RV32I-NEXT:    sw s9, 40(sp)
-; RV32I-NEXT:    sw s10, 36(sp)
-; RV32I-NEXT:    sw s11, 32(sp)
+; RV32I-NEXT:    sw ra, 76(sp)
+; RV32I-NEXT:    sw s0, 72(sp)
+; RV32I-NEXT:    sw s1, 68(sp)
+; RV32I-NEXT:    sw s2, 64(sp)
+; RV32I-NEXT:    sw s3, 60(sp)
+; RV32I-NEXT:    sw s4, 56(sp)
+; RV32I-NEXT:    sw s5, 52(sp)
+; RV32I-NEXT:    sw s6, 48(sp)
+; RV32I-NEXT:    sw s7, 44(sp)
+; RV32I-NEXT:    sw s8, 40(sp)
+; RV32I-NEXT:    sw s9, 36(sp)
+; RV32I-NEXT:    sw s10, 32(sp)
+; RV32I-NEXT:    sw s11, 28(sp)
 ; RV32I-NEXT:    lui a0, %hi(var)
 ; RV32I-NEXT:    addi a1, a0, %lo(var)
 ;
@@ -66,18 +67,19 @@
 ; RV64I-LABEL: callee:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -144
-; RV64I-NEXT:    sd s0, 136(sp)
-; RV64I-NEXT:    sd s1, 128(sp)
-; RV64I-NEXT:    sd s2, 120(sp)
-; RV64I-NEXT:    sd s3, 112(sp)
-; RV64I-NEXT:    sd s4, 104(sp)
-; RV64I-NEXT:    sd s5, 96(sp)
-; RV64I-NEXT:    sd s6, 88(sp)
-; RV64I-NEXT:    sd s7, 80(sp)
-; RV64I-NEXT:    sd s8, 72(sp)
-; RV64I-NEXT:    sd s9, 64(sp)
-; RV64I-NEXT:    sd s10, 56(sp)
-; RV64I-NEXT:    sd s11, 48(sp)
+; RV64I-NEXT:    sd ra, 136(sp)
+; RV64I-NEXT:    sd s0, 128(sp)
+; RV64I-NEXT:    sd s1, 120(sp)
+; RV64I-NEXT:    sd s2, 112(sp)
+; RV64I-NEXT:    sd s3, 104(sp)
+; RV64I-NEXT:    sd s4, 96(sp)
+; RV64I-NEXT:    sd s5, 88(sp)
+; RV64I-NEXT:    sd s6, 80(sp)
+; RV64I-NEXT:    sd s7, 72(sp)
+; RV64I-NEXT:    sd s8, 64(sp)
+; RV64I-NEXT:    sd s9, 56(sp)
+; RV64I-NEXT:    sd s10, 48(sp)
+; RV64I-NEXT:    sd s11, 40(sp)
 ; RV64I-NEXT:    lui a0, %hi(var)
 ; RV64I-NEXT:    addi a1, a0, %lo(var)
 ;
Index: lib/Target/RISCV/RISCVRegisterInfo.cpp
===================================================================
--- lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -62,7 +62,6 @@
 
   // Use markSuperRegs to ensure any register aliases are also reserved
   markSuperRegs(Reserved, RISCV::X0); // zero
-  markSuperRegs(Reserved, RISCV::X1); // ra
   markSuperRegs(Reserved, RISCV::X2); // sp
   markSuperRegs(Reserved, RISCV::X3); // gp
   markSuperRegs(Reserved, RISCV::X4); // tp


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