[PATCH] D67464: MachineScheduler: Fix assert from not checking subregs

[Quentin Colombet via Phabricator via llvm-commits]

qcolombet accepted this revision.
qcolombet added a comment.
This revision is now accepted and ready to land.

Hi Matt,

Looks sensible.

The check is not quite right I think see inline comment (you should be able to write a test case to expose the issue), but the direction is the right one).

With that fixed LGTM.

Cheers,
-Quentin



================
Comment at: lib/CodeGen/ScheduleDAGInstrs.cpp:383
+  const MachineInstr *UseInst = RegUse->SU->getInstr();
+  return UseInst->getOperand(RegUse->OperandIndex).getSubReg() != MO.getSubReg();
+}
----------------
We should check that the lane masks don't overlap instead.


================
Comment at: test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir:5
+# This would assert that a dead def should have no uses, but the dead
+# def and use have different subreg indicise.
+
----------------
typo: indices


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