[PATCH] D67664: [ARM] Ensure we do not attempt to create lsll #0

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: t.p.northover, samparker, SjoerdMeijer, simon_tatham, ostannard.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: LLVM.

During legalisation we can end up with some pretty odd nodes, like shifts of 0. We need to make sure we don't try to make long shifts of these, ending up with invalid nodes. A long shift with a zero immediate actually encodes a shift by 32.


https://reviews.llvm.org/D67664

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/Thumb2/lsll0.ll


Index: llvm/test/CodeGen/Thumb2/lsll0.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/lsll0.ll
+++ llvm/test/CodeGen/Thumb2/lsll0.ll
@@ -6,18 +6,14 @@
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vldrw.u32 q0, [r0]
 ; CHECK-NEXT:    vmov r1, s2
-; CHECK-NEXT:    sxth r2, r1
-; CHECK-NEXT:    asrs r1, r2, #31
-; CHECK-NEXT:    lsll r2, r1, #0
-; CHECK-NEXT:    rsbs r1, r2, #0
 ; CHECK-NEXT:    vmov r2, s0
 ; CHECK-NEXT:    sxth r1, r1
-; CHECK-NEXT:    asr.w r12, r1, #31
 ; CHECK-NEXT:    sxth r2, r2
-; CHECK-NEXT:    asrs r3, r2, #31
-; CHECK-NEXT:    lsll r2, r3, #0
+; CHECK-NEXT:    rsbs r1, r1, #0
 ; CHECK-NEXT:    rsbs r2, r2, #0
+; CHECK-NEXT:    sxth r1, r1
 ; CHECK-NEXT:    sxth r2, r2
+; CHECK-NEXT:    asr.w r12, r1, #31
 ; CHECK-NEXT:    asrs r3, r2, #31
 ; CHECK-NEXT:    strd r2, r3, [r0]
 ; CHECK-NEXT:    strd r1, r12, [r0, #8]
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -6010,7 +6010,7 @@
     // If the shift amount is greater than 32 or has a greater bitwidth than 64
     // then do the default optimisation
     if (ShAmt->getValueType(0).getSizeInBits() > 64 ||
-        (Con && Con->getZExtValue() >= 32))
+        (Con && (Con->getZExtValue() == 0 || Con->getZExtValue() >= 32)))
       return SDValue();
 
     // Extract the lower 32 bits of the shift amount if it's not an i32


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