[PATCH] D67489: [ARM] Add a SelectTAddrModeImm7 for MVE narrow loads and stores

Tue Sep 17 02:43:50 PDT 2019

samparker accepted this revision.
samparker added a comment.
This revision is now accepted and ready to land.

LGTM

================
Comment at: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1159
+                                          SDValue &OffImm) {
+  if (N.getOpcode() == ISD::SUB || CurDAG->isBaseWithConstantOffset(N)) {
+    int RHSC;
----------------
dmgreen wrote:
> samparker wrote:
> > What happens if N == ISD::ADD?
> Oh, i forgot to mention that this is just a copy of SelectT2AddrModeImm7, with the part about FrameIndex's removed. The other code is the same, so I hope will work as well as it did before.
> 
> I think isBaseWithConstantOffset will handle adds (and or's where we know the alignment). We just don't negate the RHSC.
Ah, ok then.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67489/new/

https://reviews.llvm.org/D67489