[llvm] r371950 - AMDGPU/GlobalISel: Select S16->S32 fptoint
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 15 17:32:56 PDT 2019
Author: arsenm
Date: Sun Sep 15 17:32:56 2019
New Revision: 371950
URL: http://llvm.org/viewvc/llvm-project?rev=371950&view=rev
Log:
AMDGPU/GlobalISel: Select S16->S32 fptoint
Added:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=371950&r1=371949&r2=371950&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Sun Sep 15 17:32:56 2019
@@ -422,7 +422,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
.scalarize(0);
getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
- .legalFor({{S32, S32}, {S32, S64}})
+ .legalFor({{S32, S32}, {S32, S64}, {S32, S16}})
.scalarize(0);
getActionDefinitionsBuilder(G_INTRINSIC_ROUND)
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=371950&r1=371949&r2=371950&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Sun Sep 15 17:32:56 2019
@@ -743,12 +743,12 @@ def : GCNPat <
def : GCNPat <
(i32 (fp_to_sint f16:$src)),
- (V_CVT_I32_F32_e32 (V_CVT_F32_F16_e32 $src))
+ (V_CVT_I32_F32_e32 (V_CVT_F32_F16_e32 VSrc_b32:$src))
>;
def : GCNPat <
(i32 (fp_to_uint f16:$src)),
- (V_CVT_U32_F32_e32 (V_CVT_F32_F16_e32 $src))
+ (V_CVT_U32_F32_e32 (V_CVT_F32_F16_e32 VSrc_b32:$src))
>;
def : GCNPat <
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir?rev=371950&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir Sun Sep 15 17:32:56 2019
@@ -0,0 +1,132 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN
+
+---
+name: fptosi_s32_to_s32_vv
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; GCN-LABEL: name: fptosi_s32_to_s32_vv
+ ; GCN: liveins: $vgpr0
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[V_CVT_I32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e64 0, [[COPY]], 0, 0, implicit $exec
+ ; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = G_FPTOSI %0
+ $vgpr0 = COPY %1
+...
+
+---
+name: fptosi_s32_to_s32_vs
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+
+ ; GCN-LABEL: name: fptosi_s32_to_s32_vs
+ ; GCN: liveins: $sgpr0
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: [[V_CVT_I32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e64 0, [[COPY]], 0, 0, implicit $exec
+ ; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e64_]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:vgpr(s32) = G_FPTOSI %0
+ $vgpr0 = COPY %1
+...
+
+---
+name: fptosi_s32_to_s32_fneg_vv
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; GCN-LABEL: name: fptosi_s32_to_s32_fneg_vv
+ ; GCN: liveins: $vgpr0
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[V_CVT_I32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e64 1, [[COPY]], 0, 0, implicit $exec
+ ; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = G_FNEG %0
+ %2:vgpr(s32) = G_FPTOSI %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: fptosi_s16_to_s32_vv
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; GCN-LABEL: name: fptosi_s16_to_s32_vv
+ ; GCN: liveins: $vgpr0
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $exec
+ ; GCN: [[V_CVT_I32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec
+ ; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e32_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s16) = G_TRUNC %0
+ %2:vgpr(s32) = G_FPTOSI %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: fptosi_s16_to_s32_vs
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+
+ ; GCN-LABEL: name: fptosi_s16_to_s32_vs
+ ; GCN: liveins: $sgpr0
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $exec
+ ; GCN: [[V_CVT_I32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec
+ ; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e32_]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:sgpr(s16) = G_TRUNC %0
+ %2:vgpr(s32) = G_FPTOSI %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: fptosi_s16_to_s32_fneg_vv
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; GCN-LABEL: name: fptosi_s16_to_s32_fneg_vv
+ ; GCN: liveins: $vgpr0
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
+ ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
+ ; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $exec
+ ; GCN: [[V_CVT_I32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec
+ ; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e32_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s16) = G_TRUNC %0
+ %2:vgpr(s16) = G_FNEG %1
+ %3:vgpr(s32) = G_FPTOSI %2
+ $vgpr0 = COPY %3
+...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir?rev=371950&r1=371949&r2=371950&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir Sun Sep 15 17:32:56 2019
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN
---
@@ -6,27 +7,99 @@ name: fptoui
legalized: true
regBankSelected: true
-# GCN-LABEL: name: fptoui
body: |
bb.0:
liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4
- ; GCN: [[SGPR:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN-LABEL: name: fptoui
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
+ ; GCN: [[V_CVT_U32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e64 0, [[COPY]], 0, 0, implicit $exec
+ ; GCN: [[V_CVT_U32_F32_e64_1:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e64 0, [[COPY1]], 0, 0, implicit $exec
+ ; GCN: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_U32_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
+ ; GCN: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_U32_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
%0:sgpr(s32) = COPY $sgpr0
- ; GCN: [[VGPR:%[0-9]+]]:vgpr_32 = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(p1) = COPY $vgpr3_vgpr4
; fptoui s
- ; GCN: V_CVT_U32_F32_e64 0, [[SGPR]], 0, 0
%3:vgpr(s32) = G_FPTOUI %0
; fptoui v
- ; GCN: V_CVT_U32_F32_e64 0, [[VGPR]], 0, 0
%4:vgpr(s32) = G_FPTOUI %1
G_STORE %3, %2 :: (store 4, addrspace 1)
G_STORE %4, %2 :: (store 4, addrspace 1)
...
+
+---
+name: fptoui_s16_to_s32_vv
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; GCN-LABEL: name: fptoui_s16_to_s32_vv
+ ; GCN: liveins: $vgpr0
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $exec
+ ; GCN: [[V_CVT_U32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec
+ ; GCN: $vgpr0 = COPY [[V_CVT_U32_F32_e32_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s16) = G_TRUNC %0
+ %2:vgpr(s32) = G_FPTOUI %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: fptoui_s16_to_s32_vs
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+
+ ; GCN-LABEL: name: fptoui_s16_to_s32_vs
+ ; GCN: liveins: $sgpr0
+ ; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $exec
+ ; GCN: [[V_CVT_U32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec
+ ; GCN: $vgpr0 = COPY [[V_CVT_U32_F32_e32_]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:sgpr(s16) = G_TRUNC %0
+ %2:vgpr(s32) = G_FPTOUI %1
+ $vgpr0 = COPY %2
+...
+
+---
+name: fptoui_s16_to_s32_fneg_vv
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+
+ ; GCN-LABEL: name: fptoui_s16_to_s32_fneg_vv
+ ; GCN: liveins: $vgpr0
+ ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
+ ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
+ ; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $exec
+ ; GCN: [[V_CVT_U32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec
+ ; GCN: $vgpr0 = COPY [[V_CVT_U32_F32_e32_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s16) = G_TRUNC %0
+ %2:vgpr(s16) = G_FNEG %1
+ %3:vgpr(s32) = G_FPTOUI %2
+ $vgpr0 = COPY %3
+...
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