[PATCH] D67423: [RISCV] Rename FPRs and use Register arithmetic

[Luís Marques via Phabricator via llvm-commits]

luismarques marked 2 inline comments as done.
luismarques added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:31
+static_assert(RISCV::F31_F == RISCV::F0_F + 31, "Register list not consecutive");
+static_assert(RISCV::F18_D == RISCV::F3_D + 15, "Register list not consecutive");
+
----------------
lenary wrote:
> Why does this static assert not cover all 31 64-bit FP regs?
You'd need a static_foreach to really check that all 32 of them are consecutive. Checking R31 == R0 + 31 strictly speaking doesn't check that R1-30 aren't scrambled. Choosing different indices for that last assert was a compromise attempt to both impart that concept and to take the opportunity to check some different indices. There's a precedent for checking other regs than the first and last.


Repository:
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  https://reviews.llvm.org/D67423/new/

https://reviews.llvm.org/D67423