[llvm] r371827 - [ARM] Add support for MVE vmaxv and vminv
Sam Tebbs via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 13 02:11:46 PDT 2019
Author: samtebbs
Date: Fri Sep 13 02:11:46 2019
New Revision: 371827
URL: http://llvm.org/viewvc/llvm-project?rev=371827&view=rev
Log:
[ARM] Add support for MVE vmaxv and vminv
This patch adds vecreduce_smax, vecredude_umax, vecreduce_smin, vecreduce_umin and selection for vmaxv and minv.
Differential Revision: https://reviews.llvm.org/D66413
Added:
llvm/trunk/test/CodeGen/Thumb2/mve-vmaxv.ll
Modified:
llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMInstrMVE.td
llvm/trunk/lib/Target/ARM/ARMTargetTransformInfo.cpp
Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=371827&r1=371826&r2=371827&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original)
+++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Fri Sep 13 02:11:46 2019
@@ -423,6 +423,10 @@ def extractelt : SDNode<"ISD::EXTRACT_VE
def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
def vecreduce_add : SDNode<"ISD::VECREDUCE_ADD", SDTVecReduce>;
+def vecreduce_smax : SDNode<"ISD::VECREDUCE_SMAX", SDTVecReduce>;
+def vecreduce_umax : SDNode<"ISD::VECREDUCE_UMAX", SDTVecReduce>;
+def vecreduce_smin : SDNode<"ISD::VECREDUCE_SMIN", SDTVecReduce>;
+def vecreduce_umin : SDNode<"ISD::VECREDUCE_UMIN", SDTVecReduce>;
def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=371827&r1=371826&r2=371827&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Sep 13 02:11:46 2019
@@ -269,6 +269,10 @@ void ARMTargetLowering::addMVEVectorType
// Vector reductions
setOperationAction(ISD::VECREDUCE_ADD, VT, Legal);
+ setOperationAction(ISD::VECREDUCE_SMAX, VT, Legal);
+ setOperationAction(ISD::VECREDUCE_UMAX, VT, Legal);
+ setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal);
+ setOperationAction(ISD::VECREDUCE_UMIN, VT, Legal);
if (!HasMVEFP) {
setOperationAction(ISD::SINT_TO_FP, VT, Expand);
Modified: llvm/trunk/lib/Target/ARM/ARMInstrMVE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrMVE.td?rev=371827&r1=371826&r2=371827&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrMVE.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrMVE.td Fri Sep 13 02:11:46 2019
@@ -669,6 +669,35 @@ multiclass MVE_VMINMAXV_ty<string iname,
defm MVE_VMINV : MVE_VMINMAXV_ty<"vminv", 0b1>;
defm MVE_VMAXV : MVE_VMINMAXV_ty<"vmaxv", 0b0>;
+let Predicates = [HasMVEInt] in {
+ def : Pat<(i32 (vecreduce_smax (v16i8 MQPR:$src))),
+ (i32 (MVE_VMAXVs8 (t2MVNi (i32 127)), $src))>;
+ def : Pat<(i32 (vecreduce_smax (v8i16 MQPR:$src))),
+ (i32 (MVE_VMAXVs16 (t2MOVi32imm (i32 -32768)), $src))>;
+ def : Pat<(i32 (vecreduce_smax (v4i32 MQPR:$src))),
+ (i32 (MVE_VMAXVs32 (t2MOVi (i32 -2147483648)), $src))>;
+ def : Pat<(i32 (vecreduce_umax (v16i8 MQPR:$src))),
+ (i32 (MVE_VMAXVu8 (t2MOVi (i32 0)), $src))>;
+ def : Pat<(i32 (vecreduce_umax (v8i16 MQPR:$src))),
+ (i32 (MVE_VMAXVu16 (t2MOVi (i32 0)), $src))>;
+ def : Pat<(i32 (vecreduce_umax (v4i32 MQPR:$src))),
+ (i32 (MVE_VMAXVu32 (t2MOVi (i32 0)), $src))>;
+
+ def : Pat<(i32 (vecreduce_smin (v16i8 MQPR:$src))),
+ (i32 (MVE_VMINVs8 (t2MOVi (i32 127)), $src))>;
+ def : Pat<(i32 (vecreduce_smin (v8i16 MQPR:$src))),
+ (i32 (MVE_VMINVs16 (t2MOVi16 (i32 32767)), $src))>;
+ def : Pat<(i32 (vecreduce_smin (v4i32 MQPR:$src))),
+ (i32 (MVE_VMINVs32 (t2MVNi (i32 -2147483648)), $src))>;
+ def : Pat<(i32 (vecreduce_umin (v16i8 MQPR:$src))),
+ (i32 (MVE_VMINVu8 (t2MOVi (i32 255)), $src))>;
+ def : Pat<(i32 (vecreduce_umin (v8i16 MQPR:$src))),
+ (i32 (MVE_VMINVu16 (t2MOVi16 (i32 65535)), $src))>;
+ def : Pat<(i32 (vecreduce_umin (v4i32 MQPR:$src))),
+ (i32 (MVE_VMINVu32 (t2MOVi (i32 4294967295)), $src))>;
+
+}
+
multiclass MVE_VMINMAXAV_ty<string iname, bit bit_7, list<dag> pattern=[]> {
def s8 : MVE_VMINMAXV<iname, "s8", 0b0, 0b00, 0b0, bit_7>;
def s16 : MVE_VMINMAXV<iname, "s16", 0b0, 0b01, 0b0, bit_7>;
Modified: llvm/trunk/lib/Target/ARM/ARMTargetTransformInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetTransformInfo.cpp?rev=371827&r1=371826&r2=371827&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetTransformInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetTransformInfo.cpp Fri Sep 13 02:11:46 2019
@@ -1059,11 +1059,11 @@ bool ARMTTIImpl::useReductionIntrinsic(u
case Instruction::Or:
case Instruction::Xor:
case Instruction::Mul:
- case Instruction::ICmp:
case Instruction::FCmp:
return false;
+ case Instruction::ICmp:
case Instruction::Add:
- return ScalarBits * Ty->getVectorNumElements() == 128;
+ return ScalarBits < 64 && ScalarBits * Ty->getVectorNumElements() == 128;
default:
llvm_unreachable("Unhandled reduction opcode");
}
Added: llvm/trunk/test/CodeGen/Thumb2/mve-vmaxv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-vmaxv.ll?rev=371827&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-vmaxv.ll (added)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-vmaxv.ll Fri Sep 13 02:11:46 2019
@@ -0,0 +1,135 @@
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s
+
+declare i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8>)
+declare i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16>)
+declare i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32>)
+declare i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8>)
+declare i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16>)
+declare i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32>)
+declare i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8>)
+declare i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16>)
+declare i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32>)
+declare i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8>)
+declare i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16>)
+declare i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32>)
+
+define arm_aapcs_vfpcc i8 @vmaxv_s_v16i8_i32(<16 x i8> %s1) {
+; CHECK-LABEL: vmaxv_s_v16i8_i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: mvn r0, #127
+; CHECK-NEXT: vmaxv.s8 r0, q0
+; CHECK-NEXT: bx lr
+ %r = call i8 @llvm.experimental.vector.reduce.smax.v16i8(<16 x i8> %s1)
+ ret i8 %r
+}
+
+define arm_aapcs_vfpcc i16 @vmaxv_s_v8i16_i32(<8 x i16> %s1) {
+; CHECK-LABEL: vmaxv_s_v8i16_i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movw r0, #32768
+; CHECK-NEXT: movt r0, #65535
+; CHECK-NEXT: vmaxv.s16 r0, q0
+; CHECK-NEXT: bx lr
+ %r = call i16 @llvm.experimental.vector.reduce.smax.v8i16(<8 x i16> %s1)
+ ret i16 %r
+}
+
+define arm_aapcs_vfpcc i32 @vmaxv_s_v4i32_i32(<4 x i32> %s1) {
+; CHECK-LABEL: vmaxv_s_v4i32_i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: mov.w r0, #-2147483648
+; CHECK-NEXT: vmaxv.s32 r0, q0
+; CHECK-NEXT: bx lr
+ %r = call i32 @llvm.experimental.vector.reduce.smax.v4i32(<4 x i32> %s1)
+ ret i32 %r
+}
+
+define arm_aapcs_vfpcc i8 @vmaxv_u_v16i8_i32(<16 x i8> %s1) {
+; CHECK-LABEL: vmaxv_u_v16i8_i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movs r0, #0
+; CHECK-NEXT: vmaxv.u8 r0, q0
+; CHECK-NEXT: bx lr
+ %r = call i8 @llvm.experimental.vector.reduce.umax.v16i8(<16 x i8> %s1)
+ ret i8 %r
+}
+
+define arm_aapcs_vfpcc i16 @vmaxv_u_v8i16_i32(<8 x i16> %s1) {
+; CHECK-LABEL: vmaxv_u_v8i16_i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movs r0, #0
+; CHECK-NEXT: vmaxv.u16 r0, q0
+; CHECK-NEXT: bx lr
+ %r = call i16 @llvm.experimental.vector.reduce.umax.v8i16(<8 x i16> %s1)
+ ret i16 %r
+}
+
+define arm_aapcs_vfpcc i32 @vmaxv_u_v4i32_i32(<4 x i32> %s1) {
+; CHECK-LABEL: vmaxv_u_v4i32_i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movs r0, #0
+; CHECK-NEXT: vmaxv.u32 r0, q0
+; CHECK-NEXT: bx lr
+ %r = call i32 @llvm.experimental.vector.reduce.umax.v4i32(<4 x i32> %s1)
+ ret i32 %r
+}
+
+define arm_aapcs_vfpcc i8 @vminv_s_v16i8_i32(<16 x i8> %s1) {
+; CHECK-LABEL: vminv_s_v16i8_i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movs r0, #127
+; CHECK-NEXT: vminv.s8 r0, q0
+; CHECK-NEXT: bx lr
+ %r = call i8 @llvm.experimental.vector.reduce.smin.v16i8(<16 x i8> %s1)
+ ret i8 %r
+}
+
+define arm_aapcs_vfpcc i16 @vminv_s_v8i16_i32(<8 x i16> %s1) {
+; CHECK-LABEL: vminv_s_v8i16_i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movw r0, #32767
+; CHECK-NEXT: vminv.s16 r0, q0
+; CHECK-NEXT: bx lr
+ %r = call i16 @llvm.experimental.vector.reduce.smin.v8i16(<8 x i16> %s1)
+ ret i16 %r
+}
+
+define arm_aapcs_vfpcc i32 @vminv_s_v4i32_i32(<4 x i32> %s1) {
+; CHECK-LABEL: vminv_s_v4i32_i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: mvn r0, #-2147483648
+; CHECK-NEXT: vminv.s32 r0, q0
+; CHECK-NEXT: bx lr
+ %r = call i32 @llvm.experimental.vector.reduce.smin.v4i32(<4 x i32> %s1)
+ ret i32 %r
+}
+
+define arm_aapcs_vfpcc i8 @vminv_u_v16i8_i32(<16 x i8> %s1) {
+; CHECK-LABEL: vminv_u_v16i8_i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movs r0, #255
+; CHECK-NEXT: vminv.u8 r0, q0
+; CHECK-NEXT: bx lr
+ %r = call i8 @llvm.experimental.vector.reduce.umin.v16i8(<16 x i8> %s1)
+ ret i8 %r
+}
+
+define arm_aapcs_vfpcc i16 @vminv_u_v8i16_i32(<8 x i16> %s1) {
+; CHECK-LABEL: vminv_u_v8i16_i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movw r0, #65535
+; CHECK-NEXT: vminv.u16 r0, q0
+; CHECK-NEXT: bx lr
+ %r = call i16 @llvm.experimental.vector.reduce.umin.v8i16(<8 x i16> %s1)
+ ret i16 %r
+}
+
+define arm_aapcs_vfpcc i32 @vminv_u_v4i32_i32(<4 x i32> %s1) {
+; CHECK-LABEL: vminv_u_v4i32_i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: mov.w r0, #-1
+; CHECK-NEXT: vminv.u32 r0, q0
+; CHECK-NEXT: bx lr
+ %r = call i32 @llvm.experimental.vector.reduce.umin.v4i32(<4 x i32> %s1)
+ ret i32 %r
+}
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