[PATCH] D67513: [PowerPC] Remove the SPE4RC register class and instead add f32 to the GPRC register class.

Thu Sep 12 13:23:46 PDT 2019

craig.topper marked an inline comment as done.
craig.topper added a comment.

In D67513#1668369 <https://reviews.llvm.org/D67513#1668369>, @jhibbits wrote:

> Thanks for getting rid of SPE4RC, I really did not like it, but couldn't think of a better way.  Glad you did.
>
> It looks like you're changing more than just removing SPE4RC in this diff.  Do the tests really change because of the removal?

Test changes are because the GPRC_GPRC_NOR0 register class was being inferred by tablegen, but was not inheriting the AltOrder from GPRC/GPRC_NOR0. Now its inherited and this causes R2 <https://reviews.llvm.org/source/clang-tools-extra/> to be at the end of the allocation order list. This caused different registers to be used and removed the spill and restore of R2 <https://reviews.llvm.org/source/clang-tools-extra/>.

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Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:2457
-       PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
-       PPC::SPILLTOVSR_LD}};

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jhibbits wrote:
> Is this an extra change?  Doesn't look to be needed for the SPE4RC removal.
This is related to the removal of SOK_SPE4Spill which caused SOK_LastOpcodeSpill to become one less so the entry in the array needed to be removed.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67513/new/

https://reviews.llvm.org/D67513