[PATCH] D67444: [ARM] Add isVectorReduction MCInstrDesc flag

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer added a comment.

> I agree that this could be implemented solely in the backend. The problem I see, however, is what happens when adding new reduction instructions, as someone adding a new tablegen def won't know to add it to where these instructions are checked. Adding the flag to tablegen makes it easier to spot and add.

Yes, I see that...but designing things for the future that may or may not happen at all is a bit tricky. As it's such a simple opcode check, I don't see why we should make things more complicated now for a thing that may never happen. And if it happens, it's not that we need to do a complete redesign of a tricky bit of logic. If it happens, then it will be pretty obvious from the codegen that new opcodes were not added to the TTI->isMVEReductionStmt hook, and then a decision can be made I guess.


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https://reviews.llvm.org/D67444