[PATCH] D61884: [RISCV] Support stack offset exceed 32-bit for RV64

[Shiva Chen via Phabricator via llvm-commits]

shiva0217 updated this revision to Diff 219922.
shiva0217 added a comment.

Choosing virtual register as temp register.

I thought to choose a virtual register may cause spill, but I was wrong. After dumping the liveness info in Scavenger, LLVM could know caller saved register which is not using for parameter passing could be used. If the shrink wrap didn't occur, the caller saved registers which not used for parameter passing should always free to use for prologue and epilogue. And Scavenger will follow the AllocationOrder for the backend. So choosing a virtual register will be more reasonable. Thanks for @asb and @lenary comments, I got your point now :)


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D61884/new/

https://reviews.llvm.org/D61884

Files:
  lib/Target/RISCV/RISCVFrameLowering.cpp
  lib/Target/RISCV/RISCVInstrInfo.cpp
  lib/Target/RISCV/RISCVInstrInfo.h
  lib/Target/RISCV/RISCVRegisterInfo.cpp
  test/CodeGen/RISCV/rv64-large-stack.ll
  test/CodeGen/RISCV/stack-realignment.ll

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