[PATCH] D66210: [RFC/WIP][RISCV] Enable the machine outliner for RISC-V

Wed Sep 11 11:08:26 PDT 2019

paquette added inline comments.

================
Comment at: llvm/test/CodeGen/RISCV/machineoutliner.mir:1-2
+# RUN: llc -march riscv32 -x mir < %s | FileCheck -check-prefix=RV32I %s
+# RUN: llc -march riscv32 -x mir -enable-machine-outliner < %s \
+# RUN: | FileCheck -check-prefix=RV32I-MO %s
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lewis-revill wrote:
> paquette wrote:
> > You probably want -verify-machineinstrs on each of these.
> I think there is some issue with the generation of MIR, at least for RISC-V... If I do IR -> MIR -> Assembly with -verify-machineinstrs, I get the error: 'Function has NoVRegs property but there are VReg operands'. I don't get it for IR -> Assembly with -verify-machineinstrs, and I'm not at all sure what to do about it.
The verifier should tell you which pass is causing this to happen, and in which function.

What is probably happening is that it's because you're using `-enable-machine-outliner`. This is probably running passes you don't expect. Since this output was generated by `-stop-before=machine-outliner`, these passes are probably doing weird things.

What you probably want is one of these:

 - `-run-pass=machine-outliner`: Only run the outliner, and produce MIR output
 - `-start-before=machine-outliner`: Run the outliner and all following passes, and produce assembly output

I think that using `-run-pass` is usually better for these kinds of tests. The reason being that it localizes the test to a single pass, rather than several. The outliner is an extremely late pass though, so using `-start-before` is probably fine.

If you use `-run-pass`, you'll have to rewrite your CHECK lines as MIR though.

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D66210/new/

https://reviews.llvm.org/D66210