[PATCH] D61884: [RISCV] Support stack offset exceed 32-bit for RV64

[Sam Elliott via Phabricator via llvm-commits]

lenary added a comment.

Nice, this is looking a lot better.

I chatted to @asb about this this morning, and he's not sure of the value of using `t1` (if it's free) instead of any general-purpose-register. This is going to compromise how many of these instructions we can compress when the C extension is enabled. If you use a virtual register, then the register allocator can use `a0-5` if it wishes, which can be compressed, unlike `t1`. Do you have a justification for explicitly choosing `t1`?


Repository:
  rL LLVM

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  https://reviews.llvm.org/D61884/new/

https://reviews.llvm.org/D61884