[PATCH] D66210: [RFC/WIP][RISCV] Enable the machine outliner for RISC-V

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill planned changes to this revision.
lewis-revill marked an inline comment as done.
lewis-revill added a comment.

I've been testing this on the Embench set of benchmarks (https://github.com/embench/embench-iot), and it appears that some programs cause execution failures with this enabled, which is a little concerning... I'm going to look into this and then also update the tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66210/new/

https://reviews.llvm.org/D66210