[PATCH] D67423: [RISCV] Consistently use Register arithmetic

[Luís Marques via Phabricator via llvm-commits]

luismarques marked an inline comment as done.
luismarques added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2116
         // Second half of f64 is passed in another GPR.
+        assert(RegLo < RISCV::X31 && "Invalid register pair");
         Register RegHigh = RegLo + 1;
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jrtc27 wrote:
> For completeness you probably want to prepend `RegLo >= RISCV::X0` (or `>` I guess... though at that point you could then argue for `>= RISCV::X10` so I'd just say go with `>= RISCV::X0` as the simplest thing that's clearly just an "is this a GPR" check).
That wasn't a check for GPRness, but instead that the `+ 1` didn't overflow the register class (if you were implementing some weird ABI, I guess).


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https://reviews.llvm.org/D67423