[PATCH] D67423: [RISCV] Consistently use Register arithmetic

[James Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2116
         // Second half of f64 is passed in another GPR.
+        assert(RegLo < RISCV::X31 && "Invalid register pair");
         Register RegHigh = RegLo + 1;
----------------
For completeness you probably want to prepend `RegLo >= RISCV::X0` (or `>` I guess... though at that point you could then argue for `>= RISCV::X10` so I'd just say go with `>= RISCV::X0` as the simplest thing that's clearly just an "is this a GPR" check).


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67423/new/

https://reviews.llvm.org/D67423