[llvm] r371467 - AMDGPU/GlobalISel: Rename MIRBuilder to B. NFC
Austin Kerbow via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 9 16:06:13 PDT 2019
Author: kerbowa
Date: Mon Sep 9 16:06:13 2019
New Revision: 371467
URL: http://llvm.org/viewvc/llvm-project?rev=371467&view=rev
Log:
AMDGPU/GlobalISel: Rename MIRBuilder to B. NFC
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67374
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.h
llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.cpp?rev=371467&r1=371466&r2=371467&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.cpp Mon Sep 9 16:06:13 2019
@@ -31,9 +31,9 @@ using namespace llvm;
namespace {
struct OutgoingValueHandler : public CallLowering::ValueHandler {
- OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
+ OutgoingValueHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
MachineInstrBuilder MIB, CCAssignFn *AssignFn)
- : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
+ : ValueHandler(B, MRI, AssignFn), MIB(MIB) {}
MachineInstrBuilder MIB;
@@ -73,9 +73,9 @@ struct OutgoingValueHandler : public Cal
struct IncomingArgHandler : public CallLowering::ValueHandler {
uint64_t StackUsed = 0;
- IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
+ IncomingArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
CCAssignFn *AssignFn)
- : ValueHandler(MIRBuilder, MRI, AssignFn) {}
+ : ValueHandler(B, MRI, AssignFn) {}
Register getStackAddress(uint64_t Size, int64_t Offset,
MachinePointerInfo &MPO) override {
@@ -133,9 +133,9 @@ struct IncomingArgHandler : public CallL
};
struct FormalArgHandler : public IncomingArgHandler {
- FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
+ FormalArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
CCAssignFn *AssignFn)
- : IncomingArgHandler(MIRBuilder, MRI, AssignFn) {}
+ : IncomingArgHandler(B, MRI, AssignFn) {}
void markPhysRegUsed(unsigned PhysReg) override {
MIRBuilder.getMBB().addLiveIn(PhysReg);
@@ -213,14 +213,14 @@ static LLT getMultipleType(LLT OrigTy, i
}
// TODO: Move to generic code
-static void unpackRegsToOrigType(MachineIRBuilder &MIRBuilder,
+static void unpackRegsToOrigType(MachineIRBuilder &B,
ArrayRef<Register> DstRegs,
Register SrcReg,
LLT SrcTy,
LLT PartTy) {
assert(DstRegs.size() > 1 && "Nothing to unpack");
- MachineFunction &MF = MIRBuilder.getMF();
+ MachineFunction &MF = B.getMF();
MachineRegisterInfo &MRI = MF.getRegInfo();
const unsigned SrcSize = SrcTy.getSizeInBits();
@@ -229,40 +229,40 @@ static void unpackRegsToOrigType(Machine
if (SrcTy.isVector() && !PartTy.isVector() &&
PartSize > SrcTy.getElementType().getSizeInBits()) {
// Vector was scalarized, and the elements extended.
- auto UnmergeToEltTy = MIRBuilder.buildUnmerge(SrcTy.getElementType(),
+ auto UnmergeToEltTy = B.buildUnmerge(SrcTy.getElementType(),
SrcReg);
for (int i = 0, e = DstRegs.size(); i != e; ++i)
- MIRBuilder.buildAnyExt(DstRegs[i], UnmergeToEltTy.getReg(i));
+ B.buildAnyExt(DstRegs[i], UnmergeToEltTy.getReg(i));
return;
}
if (SrcSize % PartSize == 0) {
- MIRBuilder.buildUnmerge(DstRegs, SrcReg);
+ B.buildUnmerge(DstRegs, SrcReg);
return;
}
const int NumRoundedParts = (SrcSize + PartSize - 1) / PartSize;
LLT BigTy = getMultipleType(PartTy, NumRoundedParts);
- auto ImpDef = MIRBuilder.buildUndef(BigTy);
+ auto ImpDef = B.buildUndef(BigTy);
Register BigReg = MRI.createGenericVirtualRegister(BigTy);
- MIRBuilder.buildInsert(BigReg, ImpDef.getReg(0), SrcReg, 0).getReg(0);
+ B.buildInsert(BigReg, ImpDef.getReg(0), SrcReg, 0).getReg(0);
int64_t Offset = 0;
for (unsigned i = 0, e = DstRegs.size(); i != e; ++i, Offset += PartSize)
- MIRBuilder.buildExtract(DstRegs[i], BigReg, Offset);
+ B.buildExtract(DstRegs[i], BigReg, Offset);
}
/// Lower the return value for the already existing \p Ret. This assumes that
-/// \p MIRBuilder's insertion point is correct.
-bool AMDGPUCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
+/// \p B's insertion point is correct.
+bool AMDGPUCallLowering::lowerReturnVal(MachineIRBuilder &B,
const Value *Val, ArrayRef<Register> VRegs,
MachineInstrBuilder &Ret) const {
if (!Val)
return true;
- auto &MF = MIRBuilder.getMF();
+ auto &MF = B.getMF();
const auto &F = MF.getFunction();
const DataLayout &DL = MF.getDataLayout();
@@ -277,69 +277,69 @@ bool AMDGPUCallLowering::lowerReturnVal(
splitToValueTypes(
OrigRetInfo, SplitRetInfos, DL, MRI, CC,
[&](ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT, int VTSplitIdx) {
- unpackRegsToOrigType(MIRBuilder, Regs, VRegs[VTSplitIdx], LLTy, PartLLT);
+ unpackRegsToOrigType(B, Regs, VRegs[VTSplitIdx], LLTy, PartLLT);
});
CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(CC, F.isVarArg());
- OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret, AssignFn);
- return handleAssignments(MIRBuilder, SplitRetInfos, RetHandler);
+ OutgoingValueHandler RetHandler(B, MF.getRegInfo(), Ret, AssignFn);
+ return handleAssignments(B, SplitRetInfos, RetHandler);
}
-bool AMDGPUCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
+bool AMDGPUCallLowering::lowerReturn(MachineIRBuilder &B,
const Value *Val,
ArrayRef<Register> VRegs) const {
- MachineFunction &MF = MIRBuilder.getMF();
+ MachineFunction &MF = B.getMF();
MachineRegisterInfo &MRI = MF.getRegInfo();
SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
MFI->setIfReturnsVoid(!Val);
assert(!Val == VRegs.empty() && "Return value without a vreg");
- CallingConv::ID CC = MIRBuilder.getMF().getFunction().getCallingConv();
+ CallingConv::ID CC = B.getMF().getFunction().getCallingConv();
const bool IsShader = AMDGPU::isShader(CC);
const bool IsWaveEnd = (IsShader && MFI->returnsVoid()) ||
AMDGPU::isKernel(CC);
if (IsWaveEnd) {
- MIRBuilder.buildInstr(AMDGPU::S_ENDPGM)
+ B.buildInstr(AMDGPU::S_ENDPGM)
.addImm(0);
return true;
}
- auto const &ST = MIRBuilder.getMF().getSubtarget<GCNSubtarget>();
+ auto const &ST = B.getMF().getSubtarget<GCNSubtarget>();
unsigned ReturnOpc =
IsShader ? AMDGPU::SI_RETURN_TO_EPILOG : AMDGPU::S_SETPC_B64_return;
- auto Ret = MIRBuilder.buildInstrNoInsert(ReturnOpc);
+ auto Ret = B.buildInstrNoInsert(ReturnOpc);
Register ReturnAddrVReg;
if (ReturnOpc == AMDGPU::S_SETPC_B64_return) {
ReturnAddrVReg = MRI.createVirtualRegister(&AMDGPU::CCR_SGPR_64RegClass);
Ret.addUse(ReturnAddrVReg);
}
- if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret))
+ if (!lowerReturnVal(B, Val, VRegs, Ret))
return false;
if (ReturnOpc == AMDGPU::S_SETPC_B64_return) {
const SIRegisterInfo *TRI = ST.getRegisterInfo();
Register LiveInReturn = MF.addLiveIn(TRI->getReturnAddressReg(MF),
&AMDGPU::SGPR_64RegClass);
- MIRBuilder.buildCopy(ReturnAddrVReg, LiveInReturn);
+ B.buildCopy(ReturnAddrVReg, LiveInReturn);
}
// TODO: Handle CalleeSavedRegsViaCopy.
- MIRBuilder.insertInstr(Ret);
+ B.insertInstr(Ret);
return true;
}
-Register AMDGPUCallLowering::lowerParameterPtr(MachineIRBuilder &MIRBuilder,
+Register AMDGPUCallLowering::lowerParameterPtr(MachineIRBuilder &B,
Type *ParamTy,
uint64_t Offset) const {
- MachineFunction &MF = MIRBuilder.getMF();
+ MachineFunction &MF = B.getMF();
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
MachineRegisterInfo &MRI = MF.getRegInfo();
const Function &F = MF.getFunction();
@@ -352,24 +352,24 @@ Register AMDGPUCallLowering::lowerParame
Register KernArgSegmentVReg = MRI.getLiveInVirtReg(KernArgSegmentPtr);
Register OffsetReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
- MIRBuilder.buildConstant(OffsetReg, Offset);
+ B.buildConstant(OffsetReg, Offset);
- MIRBuilder.buildGEP(DstReg, KernArgSegmentVReg, OffsetReg);
+ B.buildGEP(DstReg, KernArgSegmentVReg, OffsetReg);
return DstReg;
}
-void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &MIRBuilder,
+void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B,
Type *ParamTy, uint64_t Offset,
unsigned Align,
Register DstReg) const {
- MachineFunction &MF = MIRBuilder.getMF();
+ MachineFunction &MF = B.getMF();
const Function &F = MF.getFunction();
const DataLayout &DL = F.getParent()->getDataLayout();
PointerType *PtrTy = PointerType::get(ParamTy, AMDGPUAS::CONSTANT_ADDRESS);
MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
unsigned TypeSize = DL.getTypeStoreSize(ParamTy);
- Register PtrReg = lowerParameterPtr(MIRBuilder, ParamTy, Offset);
+ Register PtrReg = lowerParameterPtr(B, ParamTy, Offset);
MachineMemOperand *MMO =
MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOLoad |
@@ -377,12 +377,12 @@ void AMDGPUCallLowering::lowerParameter(
MachineMemOperand::MOInvariant,
TypeSize, Align);
- MIRBuilder.buildLoad(DstReg, PtrReg, *MMO);
+ B.buildLoad(DstReg, PtrReg, *MMO);
}
// Allocate special inputs passed in user SGPRs.
static void allocateHSAUserSGPRs(CCState &CCInfo,
- MachineIRBuilder &MIRBuilder,
+ MachineIRBuilder &B,
MachineFunction &MF,
const SIRegisterInfo &TRI,
SIMachineFunctionInfo &Info) {
@@ -411,8 +411,8 @@ static void allocateHSAUserSGPRs(CCState
const LLT P4 = LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64);
Register VReg = MRI.createGenericVirtualRegister(P4);
MRI.addLiveIn(InputPtrReg, VReg);
- MIRBuilder.getMBB().addLiveIn(InputPtrReg);
- MIRBuilder.buildCopy(VReg, InputPtrReg);
+ B.getMBB().addLiveIn(InputPtrReg);
+ B.buildCopy(VReg, InputPtrReg);
CCInfo.AllocateReg(InputPtrReg);
}
@@ -433,9 +433,9 @@ static void allocateHSAUserSGPRs(CCState
}
bool AMDGPUCallLowering::lowerFormalArgumentsKernel(
- MachineIRBuilder &MIRBuilder, const Function &F,
+ MachineIRBuilder &B, const Function &F,
ArrayRef<ArrayRef<Register>> VRegs) const {
- MachineFunction &MF = MIRBuilder.getMF();
+ MachineFunction &MF = B.getMF();
const GCNSubtarget *Subtarget = &MF.getSubtarget<GCNSubtarget>();
MachineRegisterInfo &MRI = MF.getRegInfo();
SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
@@ -447,7 +447,7 @@ bool AMDGPUCallLowering::lowerFormalArgu
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
- allocateHSAUserSGPRs(CCInfo, MIRBuilder, MF, *TRI, *Info);
+ allocateHSAUserSGPRs(CCInfo, B, MF, *TRI, *Info);
unsigned i = 0;
const unsigned KernArgBaseAlign = 16;
@@ -473,9 +473,9 @@ bool AMDGPUCallLowering::lowerFormalArgu
: MRI.createGenericVirtualRegister(getLLTForType(*ArgTy, DL));
unsigned Align = MinAlign(KernArgBaseAlign, ArgOffset);
ArgOffset = alignTo(ArgOffset, DL.getABITypeAlignment(ArgTy));
- lowerParameter(MIRBuilder, ArgTy, ArgOffset, Align, ArgReg);
+ lowerParameter(B, ArgTy, ArgOffset, Align, ArgReg);
if (OrigArgRegs.size() > 1)
- unpackRegs(OrigArgRegs, ArgReg, ArgTy, MIRBuilder);
+ unpackRegs(OrigArgRegs, ArgReg, ArgTy, B);
++i;
}
@@ -485,13 +485,13 @@ bool AMDGPUCallLowering::lowerFormalArgu
}
// TODO: Move this to generic code
-static void packSplitRegsToOrigType(MachineIRBuilder &MIRBuilder,
+static void packSplitRegsToOrigType(MachineIRBuilder &B,
ArrayRef<Register> OrigRegs,
ArrayRef<Register> Regs,
LLT LLTy,
LLT PartLLT) {
if (!LLTy.isVector() && !PartLLT.isVector()) {
- MIRBuilder.buildMerge(OrigRegs[0], Regs);
+ B.buildMerge(OrigRegs[0], Regs);
return;
}
@@ -501,15 +501,15 @@ static void packSplitRegsToOrigType(Mach
int DstElts = LLTy.getNumElements();
int PartElts = PartLLT.getNumElements();
if (DstElts % PartElts == 0)
- MIRBuilder.buildConcatVectors(OrigRegs[0], Regs);
+ B.buildConcatVectors(OrigRegs[0], Regs);
else {
// Deal with v3s16 split into v2s16
assert(PartElts == 2 && DstElts % 2 != 0);
int RoundedElts = PartElts * ((DstElts + PartElts - 1) / PartElts);
LLT RoundedDestTy = LLT::vector(RoundedElts, PartLLT.getElementType());
- auto RoundedConcat = MIRBuilder.buildConcatVectors(RoundedDestTy, Regs);
- MIRBuilder.buildExtract(OrigRegs[0], RoundedConcat, 0);
+ auto RoundedConcat = B.buildConcatVectors(RoundedDestTy, Regs);
+ B.buildExtract(OrigRegs[0], RoundedConcat, 0);
}
return;
@@ -520,7 +520,7 @@ static void packSplitRegsToOrigType(Mach
LLT DstEltTy = LLTy.getElementType();
if (DstEltTy == PartLLT) {
// Vector was trivially scalarized.
- MIRBuilder.buildBuildVector(OrigRegs[0], Regs);
+ B.buildBuildVector(OrigRegs[0], Regs);
} else if (DstEltTy.getSizeInBits() > PartLLT.getSizeInBits()) {
// Deal with vector with 64-bit elements decomposed to 32-bit
// registers. Need to create intermediate 64-bit elements.
@@ -530,23 +530,23 @@ static void packSplitRegsToOrigType(Mach
assert(DstEltTy.getSizeInBits() % PartLLT.getSizeInBits() == 0);
for (int I = 0, NumElts = LLTy.getNumElements(); I != NumElts; ++I) {
- auto Merge = MIRBuilder.buildMerge(DstEltTy,
+ auto Merge = B.buildMerge(DstEltTy,
Regs.take_front(PartsPerElt));
EltMerges.push_back(Merge.getReg(0));
Regs = Regs.drop_front(PartsPerElt);
}
- MIRBuilder.buildBuildVector(OrigRegs[0], EltMerges);
+ B.buildBuildVector(OrigRegs[0], EltMerges);
} else {
// Vector was split, and elements promoted to a wider type.
LLT BVType = LLT::vector(LLTy.getNumElements(), PartLLT);
- auto BV = MIRBuilder.buildBuildVector(BVType, Regs);
- MIRBuilder.buildTrunc(OrigRegs[0], BV);
+ auto BV = B.buildBuildVector(BVType, Regs);
+ B.buildTrunc(OrigRegs[0], BV);
}
}
bool AMDGPUCallLowering::lowerFormalArguments(
- MachineIRBuilder &MIRBuilder, const Function &F,
+ MachineIRBuilder &B, const Function &F,
ArrayRef<ArrayRef<Register>> VRegs) const {
CallingConv::ID CC = F.getCallingConv();
@@ -554,13 +554,13 @@ bool AMDGPUCallLowering::lowerFormalArgu
// useless for kernels. We want to avoid any kind of legalization or argument
// splitting.
if (CC == CallingConv::AMDGPU_KERNEL)
- return lowerFormalArgumentsKernel(MIRBuilder, F, VRegs);
+ return lowerFormalArgumentsKernel(B, F, VRegs);
const bool IsShader = AMDGPU::isShader(CC);
const bool IsEntryFunc = AMDGPU::isEntryFunctionCC(CC);
- MachineFunction &MF = MIRBuilder.getMF();
- MachineBasicBlock &MBB = MIRBuilder.getMBB();
+ MachineFunction &MF = B.getMF();
+ MachineBasicBlock &MBB = B.getMBB();
MachineRegisterInfo &MRI = MF.getRegInfo();
SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>();
@@ -576,7 +576,7 @@ bool AMDGPUCallLowering::lowerFormalArgu
Register LiveInReturn = MF.addLiveIn(ReturnAddrReg,
&AMDGPU::SGPR_64RegClass);
MBB.addLiveIn(ReturnAddrReg);
- MIRBuilder.buildCopy(LiveInReturn, ReturnAddrReg);
+ B.buildCopy(LiveInReturn, ReturnAddrReg);
}
if (Info->hasImplicitBufferPtr()) {
@@ -619,7 +619,7 @@ bool AMDGPUCallLowering::lowerFormalArgu
if (SkipArg) {
for (int I = 0, E = VRegs[Idx].size(); I != E; ++I)
- MIRBuilder.buildUndef(VRegs[Idx][I]);
+ B.buildUndef(VRegs[Idx][I]);
++Idx;
continue;
@@ -634,7 +634,7 @@ bool AMDGPUCallLowering::lowerFormalArgu
// FIXME: We should probably be passing multiple registers to
// handleAssignments to do this
[&](ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT, int VTSplitIdx) {
- packSplitRegsToOrigType(MIRBuilder, VRegs[Idx][VTSplitIdx], Regs,
+ packSplitRegsToOrigType(B, VRegs[Idx][VTSplitIdx], Regs,
LLTy, PartLLT);
});
@@ -686,10 +686,10 @@ bool AMDGPUCallLowering::lowerFormalArgu
CCAssignFn *AssignFn = TLI.CCAssignFnForCall(CC, F.isVarArg());
if (!MBB.empty())
- MIRBuilder.setInstr(*MBB.begin());
+ B.setInstr(*MBB.begin());
- FormalArgHandler Handler(MIRBuilder, MRI, AssignFn);
- if (!handleAssignments(CCInfo, ArgLocs, MIRBuilder, SplitArgs, Handler))
+ FormalArgHandler Handler(B, MRI, AssignFn);
+ if (!handleAssignments(CCInfo, ArgLocs, B, SplitArgs, Handler))
return false;
if (!IsEntryFunc) {
@@ -708,7 +708,7 @@ bool AMDGPUCallLowering::lowerFormalArgu
}
// Move back to the end of the basic block.
- MIRBuilder.setMBB(MBB);
+ B.setMBB(MBB);
return true;
}
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.h?rev=371467&r1=371466&r2=371467&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.h Mon Sep 9 16:06:13 2019
@@ -23,12 +23,11 @@ class AMDGPUTargetLowering;
class MachineInstrBuilder;
class AMDGPUCallLowering: public CallLowering {
- Register lowerParameterPtr(MachineIRBuilder &MIRBuilder, Type *ParamTy,
+ Register lowerParameterPtr(MachineIRBuilder &B, Type *ParamTy,
uint64_t Offset) const;
- void lowerParameter(MachineIRBuilder &MIRBuilder, Type *ParamTy,
- uint64_t Offset, unsigned Align,
- Register DstReg) const;
+ void lowerParameter(MachineIRBuilder &B, Type *ParamTy, uint64_t Offset,
+ unsigned Align, Register DstReg) const;
/// A function of this type is used to perform value split action.
using SplitArgTy = std::function<void(ArrayRef<Register>, LLT, LLT, int)>;
@@ -39,21 +38,19 @@ class AMDGPUCallLowering: public CallLow
CallingConv::ID CallConv,
SplitArgTy SplitArg) const;
- bool lowerReturnVal(MachineIRBuilder &MIRBuilder,
- const Value *Val, ArrayRef<Register> VRegs,
- MachineInstrBuilder &Ret) const;
+ bool lowerReturnVal(MachineIRBuilder &B, const Value *Val,
+ ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const;
public:
AMDGPUCallLowering(const AMDGPUTargetLowering &TLI);
- bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
+ bool lowerReturn(MachineIRBuilder &B, const Value *Val,
ArrayRef<Register> VRegs) const override;
- bool lowerFormalArgumentsKernel(MachineIRBuilder &MIRBuilder,
- const Function &F,
+ bool lowerFormalArgumentsKernel(MachineIRBuilder &B, const Function &F,
ArrayRef<ArrayRef<Register>> VRegs) const;
- bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
+ bool lowerFormalArguments(MachineIRBuilder &B, const Function &F,
ArrayRef<ArrayRef<Register>> VRegs) const override;
static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=371467&r1=371466&r2=371467&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Mon Sep 9 16:06:13 2019
@@ -823,35 +823,35 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
bool AMDGPULegalizerInfo::legalizeCustom(MachineInstr &MI,
MachineRegisterInfo &MRI,
- MachineIRBuilder &MIRBuilder,
+ MachineIRBuilder &B,
GISelChangeObserver &Observer) const {
switch (MI.getOpcode()) {
case TargetOpcode::G_ADDRSPACE_CAST:
- return legalizeAddrSpaceCast(MI, MRI, MIRBuilder);
+ return legalizeAddrSpaceCast(MI, MRI, B);
case TargetOpcode::G_FRINT:
- return legalizeFrint(MI, MRI, MIRBuilder);
+ return legalizeFrint(MI, MRI, B);
case TargetOpcode::G_FCEIL:
- return legalizeFceil(MI, MRI, MIRBuilder);
+ return legalizeFceil(MI, MRI, B);
case TargetOpcode::G_INTRINSIC_TRUNC:
- return legalizeIntrinsicTrunc(MI, MRI, MIRBuilder);
+ return legalizeIntrinsicTrunc(MI, MRI, B);
case TargetOpcode::G_SITOFP:
- return legalizeITOFP(MI, MRI, MIRBuilder, true);
+ return legalizeITOFP(MI, MRI, B, true);
case TargetOpcode::G_UITOFP:
- return legalizeITOFP(MI, MRI, MIRBuilder, false);
+ return legalizeITOFP(MI, MRI, B, false);
case TargetOpcode::G_FMINNUM:
case TargetOpcode::G_FMAXNUM:
case TargetOpcode::G_FMINNUM_IEEE:
case TargetOpcode::G_FMAXNUM_IEEE:
- return legalizeMinNumMaxNum(MI, MRI, MIRBuilder);
+ return legalizeMinNumMaxNum(MI, MRI, B);
case TargetOpcode::G_EXTRACT_VECTOR_ELT:
- return legalizeExtractVectorElt(MI, MRI, MIRBuilder);
+ return legalizeExtractVectorElt(MI, MRI, B);
case TargetOpcode::G_INSERT_VECTOR_ELT:
- return legalizeInsertVectorElt(MI, MRI, MIRBuilder);
+ return legalizeInsertVectorElt(MI, MRI, B);
case TargetOpcode::G_FSIN:
case TargetOpcode::G_FCOS:
- return legalizeSinCos(MI, MRI, MIRBuilder);
+ return legalizeSinCos(MI, MRI, B);
case TargetOpcode::G_GLOBAL_VALUE:
- return legalizeGlobalValue(MI, MRI, MIRBuilder);
+ return legalizeGlobalValue(MI, MRI, B);
default:
return false;
}
@@ -862,8 +862,8 @@ bool AMDGPULegalizerInfo::legalizeCustom
Register AMDGPULegalizerInfo::getSegmentAperture(
unsigned AS,
MachineRegisterInfo &MRI,
- MachineIRBuilder &MIRBuilder) const {
- MachineFunction &MF = MIRBuilder.getMF();
+ MachineIRBuilder &B) const {
+ MachineFunction &MF = B.getMF();
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
const LLT S32 = LLT::scalar(32);
@@ -884,13 +884,13 @@ Register AMDGPULegalizerInfo::getSegment
Register ApertureReg = MRI.createGenericVirtualRegister(S32);
Register GetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
- MIRBuilder.buildInstr(AMDGPU::S_GETREG_B32)
+ B.buildInstr(AMDGPU::S_GETREG_B32)
.addDef(GetReg)
.addImm(Encoding);
MRI.setType(GetReg, S32);
- auto ShiftAmt = MIRBuilder.buildConstant(S32, WidthM1 + 1);
- MIRBuilder.buildInstr(TargetOpcode::G_SHL)
+ auto ShiftAmt = B.buildConstant(S32, WidthM1 + 1);
+ B.buildInstr(TargetOpcode::G_SHL)
.addDef(ApertureReg)
.addUse(GetReg)
.addUse(ShiftAmt.getReg(0));
@@ -902,7 +902,7 @@ Register AMDGPULegalizerInfo::getSegment
LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
- if (!loadInputValue(QueuePtr, MIRBuilder, &MFI->getArgInfo().QueuePtr))
+ if (!loadInputValue(QueuePtr, B, &MFI->getArgInfo().QueuePtr))
return Register();
// Offset into amd_queue_t for group_segment_aperture_base_hi /
@@ -926,17 +926,17 @@ Register AMDGPULegalizerInfo::getSegment
Register LoadResult = MRI.createGenericVirtualRegister(S32);
Register LoadAddr;
- MIRBuilder.materializeGEP(LoadAddr, QueuePtr, LLT::scalar(64), StructOffset);
- MIRBuilder.buildLoad(LoadResult, LoadAddr, *MMO);
+ B.materializeGEP(LoadAddr, QueuePtr, LLT::scalar(64), StructOffset);
+ B.buildLoad(LoadResult, LoadAddr, *MMO);
return LoadResult;
}
bool AMDGPULegalizerInfo::legalizeAddrSpaceCast(
MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineIRBuilder &MIRBuilder) const {
- MachineFunction &MF = MIRBuilder.getMF();
+ MachineIRBuilder &B) const {
+ MachineFunction &MF = B.getMF();
- MIRBuilder.setInstr(MI);
+ B.setInstr(MI);
const LLT S32 = LLT::scalar(32);
Register Dst = MI.getOperand(0).getReg();
@@ -956,13 +956,13 @@ bool AMDGPULegalizerInfo::legalizeAddrSp
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
if (ST.getTargetLowering()->isNoopAddrSpaceCast(SrcAS, DestAS)) {
- MI.setDesc(MIRBuilder.getTII().get(TargetOpcode::G_BITCAST));
+ MI.setDesc(B.getTII().get(TargetOpcode::G_BITCAST));
return true;
}
if (DestAS == AMDGPUAS::CONSTANT_ADDRESS_32BIT) {
// Truncate.
- MIRBuilder.buildExtract(Dst, Src, 0);
+ B.buildExtract(Dst, Src, 0);
MI.eraseFromParent();
return true;
}
@@ -974,9 +974,9 @@ bool AMDGPULegalizerInfo::legalizeAddrSp
// FIXME: This is a bit ugly due to creating a merge of 2 pointers to
// another. Merge operands are required to be the same type, but creating an
// extra ptrtoint would be kind of pointless.
- auto HighAddr = MIRBuilder.buildConstant(
+ auto HighAddr = B.buildConstant(
LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS_32BIT, 32), AddrHiVal);
- MIRBuilder.buildMerge(Dst, {Src, HighAddr.getReg(0)});
+ B.buildMerge(Dst, {Src, HighAddr.getReg(0)});
MI.eraseFromParent();
return true;
}
@@ -986,17 +986,17 @@ bool AMDGPULegalizerInfo::legalizeAddrSp
DestAS == AMDGPUAS::PRIVATE_ADDRESS);
unsigned NullVal = TM.getNullPointerValue(DestAS);
- auto SegmentNull = MIRBuilder.buildConstant(DstTy, NullVal);
- auto FlatNull = MIRBuilder.buildConstant(SrcTy, 0);
+ auto SegmentNull = B.buildConstant(DstTy, NullVal);
+ auto FlatNull = B.buildConstant(SrcTy, 0);
Register PtrLo32 = MRI.createGenericVirtualRegister(DstTy);
// Extract low 32-bits of the pointer.
- MIRBuilder.buildExtract(PtrLo32, Src, 0);
+ B.buildExtract(PtrLo32, Src, 0);
Register CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1));
- MIRBuilder.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, FlatNull.getReg(0));
- MIRBuilder.buildSelect(Dst, CmpRes, PtrLo32, SegmentNull.getReg(0));
+ B.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, FlatNull.getReg(0));
+ B.buildSelect(Dst, CmpRes, PtrLo32, SegmentNull.getReg(0));
MI.eraseFromParent();
return true;
@@ -1009,29 +1009,29 @@ bool AMDGPULegalizerInfo::legalizeAddrSp
return false;
auto SegmentNull =
- MIRBuilder.buildConstant(SrcTy, TM.getNullPointerValue(SrcAS));
+ B.buildConstant(SrcTy, TM.getNullPointerValue(SrcAS));
auto FlatNull =
- MIRBuilder.buildConstant(DstTy, TM.getNullPointerValue(DestAS));
+ B.buildConstant(DstTy, TM.getNullPointerValue(DestAS));
- Register ApertureReg = getSegmentAperture(DestAS, MRI, MIRBuilder);
+ Register ApertureReg = getSegmentAperture(DestAS, MRI, B);
if (!ApertureReg.isValid())
return false;
Register CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1));
- MIRBuilder.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, SegmentNull.getReg(0));
+ B.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, SegmentNull.getReg(0));
Register BuildPtr = MRI.createGenericVirtualRegister(DstTy);
// Coerce the type of the low half of the result so we can use merge_values.
Register SrcAsInt = MRI.createGenericVirtualRegister(S32);
- MIRBuilder.buildInstr(TargetOpcode::G_PTRTOINT)
+ B.buildInstr(TargetOpcode::G_PTRTOINT)
.addDef(SrcAsInt)
.addUse(Src);
// TODO: Should we allow mismatched types but matching sizes in merges to
// avoid the ptrtoint?
- MIRBuilder.buildMerge(BuildPtr, {SrcAsInt, ApertureReg});
- MIRBuilder.buildSelect(Dst, CmpRes, BuildPtr, FlatNull.getReg(0));
+ B.buildMerge(BuildPtr, {SrcAsInt, ApertureReg});
+ B.buildSelect(Dst, CmpRes, BuildPtr, FlatNull.getReg(0));
MI.eraseFromParent();
return true;
@@ -1039,8 +1039,8 @@ bool AMDGPULegalizerInfo::legalizeAddrSp
bool AMDGPULegalizerInfo::legalizeFrint(
MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineIRBuilder &MIRBuilder) const {
- MIRBuilder.setInstr(MI);
+ MachineIRBuilder &B) const {
+ B.setInstr(MI);
Register Src = MI.getOperand(1).getReg();
LLT Ty = MRI.getType(Src);
@@ -1049,18 +1049,18 @@ bool AMDGPULegalizerInfo::legalizeFrint(
APFloat C1Val(APFloat::IEEEdouble(), "0x1.0p+52");
APFloat C2Val(APFloat::IEEEdouble(), "0x1.fffffffffffffp+51");
- auto C1 = MIRBuilder.buildFConstant(Ty, C1Val);
- auto CopySign = MIRBuilder.buildFCopysign(Ty, C1, Src);
+ auto C1 = B.buildFConstant(Ty, C1Val);
+ auto CopySign = B.buildFCopysign(Ty, C1, Src);
// TODO: Should this propagate fast-math-flags?
- auto Tmp1 = MIRBuilder.buildFAdd(Ty, Src, CopySign);
- auto Tmp2 = MIRBuilder.buildFSub(Ty, Tmp1, CopySign);
+ auto Tmp1 = B.buildFAdd(Ty, Src, CopySign);
+ auto Tmp2 = B.buildFSub(Ty, Tmp1, CopySign);
- auto C2 = MIRBuilder.buildFConstant(Ty, C2Val);
- auto Fabs = MIRBuilder.buildFAbs(Ty, Src);
+ auto C2 = B.buildFConstant(Ty, C2Val);
+ auto Fabs = B.buildFAbs(Ty, Src);
- auto Cond = MIRBuilder.buildFCmp(CmpInst::FCMP_OGT, LLT::scalar(1), Fabs, C2);
- MIRBuilder.buildSelect(MI.getOperand(0).getReg(), Cond, Src, Tmp2);
+ auto Cond = B.buildFCmp(CmpInst::FCMP_OGT, LLT::scalar(1), Fabs, C2);
+ B.buildSelect(MI.getOperand(0).getReg(), Cond, Src, Tmp2);
return true;
}
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.h?rev=371467&r1=371466&r2=371467&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.h Mon Sep 9 16:06:13 2019
@@ -32,34 +32,34 @@ public:
const GCNTargetMachine &TM);
bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineIRBuilder &MIRBuilder,
+ MachineIRBuilder &B,
GISelChangeObserver &Observer) const override;
Register getSegmentAperture(unsigned AddrSpace,
MachineRegisterInfo &MRI,
- MachineIRBuilder &MIRBuilder) const;
+ MachineIRBuilder &B) const;
bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineIRBuilder &MIRBuilder) const;
+ MachineIRBuilder &B) const;
bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineIRBuilder &MIRBuilder) const;
+ MachineIRBuilder &B) const;
bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineIRBuilder &MIRBuilder) const;
+ MachineIRBuilder &B) const;
bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineIRBuilder &MIRBuilder) const;
+ MachineIRBuilder &B) const;
bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineIRBuilder &MIRBuilder, bool Signed) const;
+ MachineIRBuilder &B, bool Signed) const;
bool legalizeMinNumMaxNum(MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineIRBuilder &MIRBuilder) const;
+ MachineIRBuilder &B) const;
bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineIRBuilder &MIRBuilder) const;
+ MachineIRBuilder &B) const;
bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineIRBuilder &MIRBuilder) const;
+ MachineIRBuilder &B) const;
bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineIRBuilder &MIRBuilder) const;
+ MachineIRBuilder &B) const;
bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineIRBuilder &MIRBuilder) const;
+ MachineIRBuilder &B) const;
Register getLiveInRegister(MachineRegisterInfo &MRI,
Register Reg, LLT Ty) const;
@@ -78,7 +78,7 @@ public:
bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B, unsigned AddrSpace) const;
bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
- MachineIRBuilder &MIRBuilder) const override;
+ MachineIRBuilder &B) const override;
};
} // End llvm namespace.
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