[llvm] r371438 - AMDGPU: Make VReg_1 size be 1
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 9 11:43:29 PDT 2019
Author: arsenm
Date: Mon Sep 9 11:43:29 2019
New Revision: 371438
URL: http://llvm.org/viewvc/llvm-project?rev=371438&view=rev
Log:
AMDGPU: Make VReg_1 size be 1
This was getting chosen as the preferred 32-bit register class based
on how TableGen selects subregister classes.
Modified:
llvm/trunk/lib/Target/AMDGPU/SILowerI1Copies.cpp
llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td
llvm/trunk/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir
llvm/trunk/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
llvm/trunk/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
Modified: llvm/trunk/lib/Target/AMDGPU/SILowerI1Copies.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SILowerI1Copies.cpp?rev=371438&r1=371437&r2=371438&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SILowerI1Copies.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SILowerI1Copies.cpp Mon Sep 9 11:43:29 2019
@@ -489,6 +489,15 @@ bool SILowerI1Copies::runOnMachineFuncti
return true;
}
+#ifndef NDEBUG
+static bool isVRegCompatibleReg(const SIRegisterInfo &TRI,
+ const MachineRegisterInfo &MRI,
+ Register Reg) {
+ unsigned Size = TRI.getRegSizeInBits(Reg, MRI);
+ return Size == 1 || Size == 32;
+}
+#endif
+
void SILowerI1Copies::lowerCopiesFromI1() {
SmallVector<MachineInstr *, 4> DeadCopies;
@@ -509,7 +518,7 @@ void SILowerI1Copies::lowerCopiesFromI1(
LLVM_DEBUG(dbgs() << "Lower copy from i1: " << MI);
DebugLoc DL = MI.getDebugLoc();
- assert(TII->getRegisterInfo().getRegSizeInBits(DstReg, *MRI) == 32);
+ assert(isVRegCompatibleReg(TII->getRegisterInfo(), *MRI, DstReg));
assert(!MI.getOperand(0).getSubReg());
ConstrainRegs.insert(SrcReg);
Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=371438&r1=371437&r2=371438&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp Mon Sep 9 11:43:29 2019
@@ -1438,8 +1438,6 @@ const TargetRegisterClass *SIRegisterInf
// TargetRegisterClass to mark which classes are VGPRs to make this trivial.
bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
unsigned Size = getRegSizeInBits(*RC);
- if (Size < 32)
- return false;
switch (Size) {
case 32:
return getCommonSubClass(&AMDGPU::VGPR_32RegClass, RC) != nullptr;
@@ -1457,8 +1455,11 @@ bool SIRegisterInfo::hasVGPRs(const Targ
return getCommonSubClass(&AMDGPU::VReg_512RegClass, RC) != nullptr;
case 1024:
return getCommonSubClass(&AMDGPU::VReg_1024RegClass, RC) != nullptr;
+ case 1:
+ return getCommonSubClass(&AMDGPU::VReg_1RegClass, RC) != nullptr;
default:
- llvm_unreachable("Invalid register class size");
+ assert(Size < 32 && "Invalid register class size");
+ return false;
}
}
@@ -1506,6 +1507,8 @@ const TargetRegisterClass *SIRegisterInf
return &AMDGPU::VReg_512RegClass;
case 1024:
return &AMDGPU::VReg_1024RegClass;
+ case 1:
+ return &AMDGPU::VReg_1RegClass;
default:
llvm_unreachable("Invalid register class size");
}
Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td?rev=371438&r1=371437&r2=371438&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td Mon Sep 9 11:43:29 2019
@@ -682,7 +682,7 @@ def AReg_1024 : RegisterClass<"AMDGPU",
}
def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> {
- let Size = 32;
+ let Size = 1;
}
def VS_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
Modified: llvm/trunk/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir?rev=371438&r1=371437&r2=371438&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir Mon Sep 9 11:43:29 2019
@@ -69,7 +69,7 @@ body: |
%25:vgpr_32 = V_AND_B32_e32 target-flags(amdgpu-gotprel32-hi) 1, %10.sub2, implicit $exec
%26:sreg_64 = V_CMP_EQ_U32_e64 1, %25, implicit $exec
%27:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- %28:vreg_1 = COPY %27
+ %28:vgpr_32 = COPY %27
%29:sreg_64 = COPY $exec, implicit-def $exec
%30:sreg_64 = S_AND_B64 %29, %26, implicit-def dead $scc
$exec = S_MOV_B64_term %30
@@ -81,7 +81,7 @@ body: |
%31:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN undef %32:vgpr_32, undef %33:sreg_128, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from constant-pool, align 1, addrspace 4)
%34:sreg_64_xexec = V_CMP_NE_U32_e64 0, %31, implicit $exec
%35:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, -1, %34, implicit $exec
- %28:vreg_1 = COPY %35
+ %28:vgpr_32 = COPY %35
S_BRANCH %bb.10
bb.9:
@@ -91,7 +91,7 @@ body: |
bb.10:
successors: %bb.9
$exec = S_OR_B64 $exec, %29, implicit-def $scc
- %36:vreg_1 = COPY %28
+ %36:vgpr_32 = COPY %28
%37:sreg_64_xexec = V_CMP_NE_U32_e64 0, %36, implicit $exec
%38:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %37, implicit $exec
%39:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
Modified: llvm/trunk/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir?rev=371438&r1=371437&r2=371438&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir Mon Sep 9 11:43:29 2019
@@ -84,8 +84,8 @@ body: |
%38:vreg_128 = IMPLICIT_DEF
%39:vreg_128 = IMPLICIT_DEF
%40:vgpr_32 = IMPLICIT_DEF
- %41:vreg_1 = COPY killed %35
- %42:vreg_1 = COPY killed %34
+ %41:vgpr_32 = COPY killed %35
+ %42:vgpr_32 = COPY killed %34
%43:sreg_64 = COPY $exec, implicit-def $exec
%44:sreg_64 = S_AND_B64 %43, %30, implicit-def dead $scc
%45:sreg_64 = S_XOR_B64 %44, %43, implicit-def dead $scc
@@ -96,7 +96,7 @@ body: |
bb.5:
successors: %bb.9(0x80000000)
$exec = S_OR_B64 $exec, %46, implicit-def $scc
- %47:vreg_1 = COPY killed %48
+ %47:vgpr_32 = COPY killed %48
%49:vgpr_32 = COPY killed %50
%51:vreg_128 = COPY killed %52
%53:vreg_128 = COPY killed %54
@@ -109,8 +109,8 @@ body: |
%38:vreg_128 = COPY killed %59
%39:vreg_128 = COPY killed %51
%40:vgpr_32 = COPY killed %49
- %41:vreg_1 = COPY killed %47
- %42:vreg_1 = COPY killed %58
+ %41:vgpr_32 = COPY killed %47
+ %42:vgpr_32 = COPY killed %58
S_BRANCH %bb.9
bb.6:
@@ -118,7 +118,7 @@ body: |
$exec = S_OR_B64 $exec, killed %60, implicit-def $scc
%61:sreg_64 = V_CMP_NE_U32_e64 0, killed %62, implicit $exec
%63:vreg_128 = COPY killed %64
- %65:vreg_1 = COPY killed %66
+ %65:vgpr_32 = COPY killed %66
%67:sreg_64 = COPY $exec, implicit-def $exec
%68:sreg_64 = S_AND_B64 %67, %61, implicit-def dead $scc
$exec = S_MOV_B64_term killed %68
@@ -130,7 +130,7 @@ body: |
%69:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
%70:vreg_128 = COPY killed %33
%63:vreg_128 = COPY killed %70
- %65:vreg_1 = COPY killed %69
+ %65:vgpr_32 = COPY killed %69
S_BRANCH %bb.13
bb.8:
@@ -145,8 +145,8 @@ body: |
bb.9:
successors: %bb.6(0x04000000), %bb.4(0x7c000000)
$exec = S_OR_B64 $exec, %45, implicit-def $scc
- %62:vreg_1 = COPY killed %42
- %66:vreg_1 = COPY killed %41
+ %62:vgpr_32 = COPY killed %42
+ %66:vgpr_32 = COPY killed %41
%76:vgpr_32 = COPY killed %40
%77:vreg_128 = COPY killed %39
%64:vreg_128 = COPY killed %38
@@ -193,7 +193,7 @@ body: |
%54:vreg_128 = COPY killed %23
%52:vreg_128 = IMPLICIT_DEF
%50:vgpr_32 = IMPLICIT_DEF
- %48:vreg_1 = COPY killed %88
+ %48:vgpr_32 = COPY killed %88
%89:sreg_64 = COPY $exec, implicit-def $exec
%90:sreg_64 = S_AND_B64 %89, %87, implicit-def dead $scc
%46:sreg_64 = S_XOR_B64 %90, %89, implicit-def dead $scc
@@ -204,7 +204,7 @@ body: |
bb.13:
successors: %bb.14(0x40000000), %bb.16(0x40000000)
$exec = S_OR_B64 $exec, killed %67, implicit-def $scc
- %91:vreg_1 = COPY killed %65
+ %91:vgpr_32 = COPY killed %65
%92:vreg_128 = COPY killed %63
%93:sreg_64 = V_CMP_NE_U32_e64 0, killed %91, implicit $exec
%94:vreg_128 = COPY killed %78
@@ -231,7 +231,7 @@ body: |
%54:vreg_128 = COPY killed %101
%52:vreg_128 = COPY %59
%50:vgpr_32 = COPY killed %102
- %48:vreg_1 = COPY killed %98
+ %48:vgpr_32 = COPY killed %98
S_BRANCH %bb.5
bb.16:
Modified: llvm/trunk/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir?rev=371438&r1=371437&r2=371438&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir Mon Sep 9 11:43:29 2019
@@ -60,7 +60,7 @@ body: |
bb.3:
successors: %bb.6(0x80000000)
%15:vreg_128 = IMPLICIT_DEF
- %16:vreg_1 = COPY killed %14
+ %16:vgpr_32 = COPY killed %14
S_BRANCH %bb.6
bb.4:
@@ -83,7 +83,7 @@ body: |
bb.6:
successors: %bb.8(0x40000000), %bb.10(0x40000000)
- %25:vreg_1 = COPY killed %16
+ %25:vgpr_32 = COPY killed %16
%26:vreg_128 = COPY killed %15
%27:sreg_64 = V_CMP_NE_U32_e64 0, killed %25, implicit $exec
%28:sreg_64 = S_AND_B64 $exec, killed %27, implicit-def dead $scc
@@ -97,7 +97,7 @@ body: |
$exec = S_OR_B64 $exec, killed %23, implicit-def $scc
%30:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%15:vreg_128 = COPY %13
- %16:vreg_1 = COPY killed %30
+ %16:vgpr_32 = COPY killed %30
S_BRANCH %bb.6
bb.8:
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