[llvm] r371395 - [ARM][MVE] VCTP instruction selection

[Sam Parker via llvm-commits]

Author: sam_parker
Date: Mon Sep  9 05:54:47 2019
New Revision: 371395

URL: http://llvm.org/viewvc/llvm-project?rev=371395&view=rev
Log:
[ARM][MVE] VCTP instruction selection
    
Add codegen support for vctp{8,16,32}.

Differential Revision: https://reviews.llvm.org/D67344

Added:
    llvm/trunk/test/CodeGen/Thumb2/mve-vctp.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrMVE.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrMVE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrMVE.td?rev=371395&r1=371394&r2=371395&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrMVE.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrMVE.td Mon Sep  9 05:54:47 2019
@@ -3944,6 +3944,15 @@ def MVE_VCTP16 : MVE_VCTP<"16", 0b01>;
 def MVE_VCTP32 : MVE_VCTP<"32", 0b10>;
 def MVE_VCTP64 : MVE_VCTP<"64", 0b11>;
 
+let Predicates = [HasMVEInt] in {
+  def : Pat<(int_arm_vctp8 rGPR:$Rn),
+            (v16i1 (MVE_VCTP8 rGPR:$Rn))>;
+  def : Pat<(int_arm_vctp16 rGPR:$Rn),
+            (v8i1 (MVE_VCTP16 rGPR:$Rn))>;
+  def : Pat<(int_arm_vctp32 rGPR:$Rn),
+            (v4i1 (MVE_VCTP32 rGPR:$Rn))>;
+}
+
 // end of mve_qDest_rSrc
 
 // start of coproc mov

Added: llvm/trunk/test/CodeGen/Thumb2/mve-vctp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-vctp.ll?rev=371395&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-vctp.ll (added)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-vctp.ll Mon Sep  9 05:54:47 2019
@@ -0,0 +1,54 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve --verify-machineinstrs %s -o - | FileCheck %s
+
+define void @vctp8(i32 %arg, <16 x i8> *%in, <16 x i8>* %out) {
+; CHECK-LABEL: vctp8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vldrw.u32 q1, [r1]
+; CHECK-NEXT:    vctp.8 r0
+; CHECK-NEXT:    vmov.i32 q0, #0x0
+; CHECK-NEXT:    vpsel q0, q1, q0
+; CHECK-NEXT:    vstrw.32 q0, [r2]
+; CHECK-NEXT:    bx lr
+  %pred = call <16 x i1> @llvm.arm.vctp8(i32 %arg)
+  %ld = load <16 x i8>, <16 x i8>* %in
+  %res = select <16 x i1> %pred, <16 x i8> %ld, <16 x i8> zeroinitializer
+  store <16 x i8> %res, <16 x i8>* %out
+  ret void
+}
+
+define void @vctp16(i32 %arg, <8 x i16> *%in, <8 x i16>* %out) {
+; CHECK-LABEL: vctp16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vldrw.u32 q1, [r1]
+; CHECK-NEXT:    vctp.16 r0
+; CHECK-NEXT:    vmov.i32 q0, #0x0
+; CHECK-NEXT:    vpsel q0, q1, q0
+; CHECK-NEXT:    vstrw.32 q0, [r2]
+; CHECK-NEXT:    bx lr
+  %pred = call <8 x i1> @llvm.arm.vctp16(i32 %arg)
+  %ld = load <8 x i16>, <8 x i16>* %in
+  %res = select <8 x i1> %pred, <8 x i16> %ld, <8 x i16> zeroinitializer
+  store <8 x i16> %res, <8 x i16>* %out
+  ret void
+}
+
+define void @vctp32(i32 %arg, <4 x i32> *%in, <4 x i32>* %out) {
+; CHECK-LABEL: vctp32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vldrw.u32 q1, [r1]
+; CHECK-NEXT:    vctp.32 r0
+; CHECK-NEXT:    vmov.i32 q0, #0x0
+; CHECK-NEXT:    vpsel q0, q1, q0
+; CHECK-NEXT:    vstrw.32 q0, [r2]
+; CHECK-NEXT:    bx lr
+  %pred = call <4 x i1> @llvm.arm.vctp32(i32 %arg)
+  %ld = load <4 x i32>, <4 x i32>* %in
+  %res = select <4 x i1> %pred, <4 x i32> %ld, <4 x i32> zeroinitializer
+  store <4 x i32> %res, <4 x i32>* %out
+  ret void
+}
+
+declare <16 x i1> @llvm.arm.vctp8(i32)
+declare <8 x i1> @llvm.arm.vctp16(i32)
+declare <4 x i1> @llvm.arm.vctp32(i32)