[PATCH] D67344: [ARM][MVE] VCTP instruction selection

[Sam Parker via Phabricator via llvm-commits]

samparker created this revision.
samparker added reviewers: dmgreen, simon_tatham, SjoerdMeijer.
Herald added a subscriber: kristof.beyls.

Add codegen support for vctp{8,16,32}.


https://reviews.llvm.org/D67344

Files:
  lib/Target/ARM/ARMInstrMVE.td
  test/CodeGen/Thumb2/mve-vctp.ll


Index: test/CodeGen/Thumb2/mve-vctp.ll
===================================================================
--- /dev/null
+++ test/CodeGen/Thumb2/mve-vctp.ll
@@ -0,0 +1,29 @@
+; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve %s -o - | FileCheck %s
+
+; CHECK-LABEL: vctp8
+; CHECK: vctp.8 r1
+; CHECK: vstr p0, [r0]
+define <16 x i1> @vctp8(i32 %arg) {
+  %res = call <16 x i1> @llvm.arm.vctp8(i32 %arg)
+  ret <16 x i1> %res
+}
+
+; CHECK-LABEL: vctp16
+; CHECK: vctp.16 r1
+; CHECK: vstr p0, [r0]
+define <8 x i1> @vctp16(i32 %arg) {
+  %res = call <8 x i1> @llvm.arm.vctp16(i32 %arg)
+  ret <8 x i1> %res
+}
+
+; CHECK-LABEL: vctp32
+; CHECK: vctp.32 r1
+; CHECK: vstr p0, [r0]
+define <4 x i1> @vctp32(i32 %arg) {
+  %res = call <4 x i1> @llvm.arm.vctp32(i32 %arg)
+  ret <4 x i1> %res
+}
+
+declare <16 x i1> @llvm.arm.vctp8(i32)
+declare <8 x i1> @llvm.arm.vctp16(i32)
+declare <4 x i1> @llvm.arm.vctp32(i32)
Index: lib/Target/ARM/ARMInstrMVE.td
===================================================================
--- lib/Target/ARM/ARMInstrMVE.td
+++ lib/Target/ARM/ARMInstrMVE.td
@@ -3942,6 +3942,15 @@
 def MVE_VCTP32 : MVE_VCTP<"32", 0b10>;
 def MVE_VCTP64 : MVE_VCTP<"64", 0b11>;
 
+let Predicates = [HasMVEInt] in {
+def : Pat<(int_arm_vctp8 rGPR:$Rn),
+          (v16i1 (MVE_VCTP8 rGPR:$Rn))>;
+def : Pat<(int_arm_vctp16 rGPR:$Rn),
+          (v8i1 (MVE_VCTP16 rGPR:$Rn))>;
+def : Pat<(int_arm_vctp32 rGPR:$Rn),
+          (v4i1 (MVE_VCTP32 rGPR:$Rn))>;
+}
+
 // end of mve_qDest_rSrc
 
 // start of coproc mov


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