[llvm] r370745 - [ARM] Ignore Implicit CPSR regs when lowering from Machine to MC operands
David Green via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 3 04:30:54 PDT 2019
Author: dmgreen
Date: Tue Sep 3 04:30:54 2019
New Revision: 370745
URL: http://llvm.org/viewvc/llvm-project?rev=370745&view=rev
Log:
[ARM] Ignore Implicit CPSR regs when lowering from Machine to MC operands
The code here seems to date back to r134705, when tablegen lowering was first
being added. I don't believe that we need to include CPSR implicit operands on
the MCInst. This now works more like other backends (like AArch64), where all
implicit registers are skipped.
This allows the AliasInst for CSEL's to match correctly, as can be seen in the
test changes.
Differential revision: https://reviews.llvm.org/D66703
Modified:
llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp
llvm/trunk/test/CodeGen/Thumb2/csel.ll
llvm/trunk/test/CodeGen/Thumb2/mve-abs.ll
llvm/trunk/test/CodeGen/Thumb2/mve-fmath.ll
llvm/trunk/test/CodeGen/Thumb2/mve-minmax.ll
llvm/trunk/test/CodeGen/Thumb2/mve-pred-and.ll
llvm/trunk/test/CodeGen/Thumb2/mve-pred-bitcast.ll
llvm/trunk/test/CodeGen/Thumb2/mve-pred-build-var.ll
llvm/trunk/test/CodeGen/Thumb2/mve-pred-ext.ll
llvm/trunk/test/CodeGen/Thumb2/mve-pred-loadstore.ll
llvm/trunk/test/CodeGen/Thumb2/mve-pred-not.ll
llvm/trunk/test/CodeGen/Thumb2/mve-pred-or.ll
llvm/trunk/test/CodeGen/Thumb2/mve-pred-xor.ll
llvm/trunk/test/CodeGen/Thumb2/mve-vcmp.ll
llvm/trunk/test/CodeGen/Thumb2/mve-vcmpf.ll
llvm/trunk/test/CodeGen/Thumb2/mve-vcmpfr.ll
llvm/trunk/test/CodeGen/Thumb2/mve-vcmpfz.ll
llvm/trunk/test/CodeGen/Thumb2/mve-vcmpr.ll
llvm/trunk/test/CodeGen/Thumb2/mve-vcmpz.ll
llvm/trunk/test/MC/ARM/thumbv8.1m.s
Modified: llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp?rev=370745&r1=370744&r2=370745&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp Tue Sep 3 04:30:54 2019
@@ -74,8 +74,8 @@ bool ARMAsmPrinter::lowerOperand(const M
switch (MO.getType()) {
default: llvm_unreachable("unknown operand type");
case MachineOperand::MO_Register:
- // Ignore all non-CPSR implicit register operands.
- if (MO.isImplicit() && MO.getReg() != ARM::CPSR)
+ // Ignore all implicit register operands.
+ if (MO.isImplicit())
return false;
assert(!MO.getSubReg() && "Subregs should be eliminated!");
MCOp = MCOperand::createReg(MO.getReg());
Modified: llvm/trunk/test/CodeGen/Thumb2/csel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/csel.ll?rev=370745&r1=370744&r2=370745&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/csel.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/csel.ll Tue Sep 3 04:30:54 2019
@@ -6,7 +6,7 @@ define i32 @csinc_const_65(i32 %a) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #5
; CHECK-NEXT: cmp r0, #45
-; CHECK-NEXT: csinc r0, r1, r1, le
+; CHECK-NEXT: cinc r0, r1, gt
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
@@ -19,7 +19,7 @@ define i32 @csinc_const_56(i32 %a) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #5
; CHECK-NEXT: cmp r0, #45
-; CHECK-NEXT: csinc r0, r1, r1, gt
+; CHECK-NEXT: cinc r0, r1, le
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
@@ -31,7 +31,7 @@ define i32 @csinc_const_zext(i32 %a) {
; CHECK-LABEL: csinc_const_zext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #45
-; CHECK-NEXT: csinc r0, zr, zr, le
+; CHECK-NEXT: cset r0, gt
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
@@ -44,7 +44,7 @@ define i32 @csinv_const_56(i32 %a) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #5
; CHECK-NEXT: cmp r0, #45
-; CHECK-NEXT: csinv r0, r1, r1, le
+; CHECK-NEXT: cinv r0, r1, gt
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
@@ -57,7 +57,7 @@ define i32 @csinv_const_65(i32 %a) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #5
; CHECK-NEXT: cmp r0, #45
-; CHECK-NEXT: csinv r0, r1, r1, gt
+; CHECK-NEXT: cinv r0, r1, le
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
@@ -69,7 +69,7 @@ define i32 @csinv_const_sext(i32 %a) {
; CHECK-LABEL: csinv_const_sext:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #45
-; CHECK-NEXT: csinv r0, zr, zr, le
+; CHECK-NEXT: csetm r0, gt
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
@@ -82,7 +82,7 @@ define i32 @csneg_const(i32 %a) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #1
; CHECK-NEXT: cmp r0, #45
-; CHECK-NEXT: csneg r0, r1, r1, gt
+; CHECK-NEXT: cneg r0, r1, le
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
@@ -95,7 +95,7 @@ define i32 @csneg_const_r(i32 %a) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #1
; CHECK-NEXT: cmp r0, #45
-; CHECK-NEXT: csneg r0, r1, r1, le
+; CHECK-NEXT: cneg r0, r1, gt
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %a, 45
@@ -316,7 +316,7 @@ define i32 @csinc_inplace(i32 %a, i32 %b
; CHECK-LABEL: csinc_inplace:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r1, #45
-; CHECK-NEXT: csinc r0, r0, r0, le
+; CHECK-NEXT: cinc r0, r0, gt
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %b, 45
@@ -329,7 +329,7 @@ define i32 @csinv_inplace(i32 %a, i32 %b
; CHECK-LABEL: csinv_inplace:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r1, #45
-; CHECK-NEXT: csinv r0, r0, r0, le
+; CHECK-NEXT: cinv r0, r0, gt
; CHECK-NEXT: bx lr
entry:
%cmp = icmp sgt i32 %b, 45
Modified: llvm/trunk/test/CodeGen/Thumb2/mve-abs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-abs.ll?rev=370745&r1=370744&r2=370745&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-abs.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-abs.ll Tue Sep 3 04:30:54 2019
@@ -49,7 +49,7 @@ define arm_aapcs_vfpcc <2 x i64> @abs_v2
; CHECK-NEXT: rsbs.w r3, lr, #0
; CHECK-NEXT: sbc.w r2, r12, r0
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csinc r1, zr, zr, pl
+; CHECK-NEXT: cset r1, mi
; CHECK-NEXT: ands r1, r1, #1
; CHECK-NEXT: itt eq
; CHECK-NEXT: moveq r2, r0
@@ -61,7 +61,7 @@ define arm_aapcs_vfpcc <2 x i64> @abs_v2
; CHECK-NEXT: rsbs.w r2, lr, #0
; CHECK-NEXT: sbc.w r3, r12, r0
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csinc r1, zr, zr, pl
+; CHECK-NEXT: cset r1, mi
; CHECK-NEXT: ands r1, r1, #1
; CHECK-NEXT: it eq
; CHECK-NEXT: moveq r2, lr
Modified: llvm/trunk/test/CodeGen/Thumb2/mve-fmath.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-fmath.ll?rev=370745&r1=370744&r2=370745&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-fmath.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-fmath.ll Tue Sep 3 04:30:54 2019
@@ -1329,14 +1329,14 @@ define arm_aapcs_vfpcc <8 x half> @copys
; CHECK-NEXT: ldrb.w r1, [sp, #25]
; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vabs.f16 s8, s1
-; CHECK-NEXT: csinc r0, zr, zr, eq
+; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s4, s4, s6
; CHECK-NEXT: tst.w r1, #128
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vmovx.f16 s4, s0
-; CHECK-NEXT: csinc r1, zr, zr, eq
+; CHECK-NEXT: cset r1, ne
; CHECK-NEXT: vabs.f16 s4, s4
; CHECK-NEXT: vneg.f16 s6, s4
; CHECK-NEXT: lsls r1, r1, #31
@@ -1348,7 +1348,7 @@ define arm_aapcs_vfpcc <8 x half> @copys
; CHECK-NEXT: vmov.16 q1[1], r1
; CHECK-NEXT: vabs.f16 s0, s0
; CHECK-NEXT: tst.w r0, #128
-; CHECK-NEXT: csinc r0, zr, zr, eq
+; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vmov r0, s8
@@ -1358,7 +1358,7 @@ define arm_aapcs_vfpcc <8 x half> @copys
; CHECK-NEXT: vabs.f16 s8, s8
; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vneg.f16 s10, s8
-; CHECK-NEXT: csinc r0, zr, zr, eq
+; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vmov r0, s8
@@ -1367,7 +1367,7 @@ define arm_aapcs_vfpcc <8 x half> @copys
; CHECK-NEXT: ldrb.w r0, [sp, #13]
; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: tst.w r0, #128
-; CHECK-NEXT: csinc r0, zr, zr, eq
+; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vmov r0, s8
@@ -1378,7 +1378,7 @@ define arm_aapcs_vfpcc <8 x half> @copys
; CHECK-NEXT: vneg.f16 s2, s0
; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vneg.f16 s10, s8
-; CHECK-NEXT: csinc r0, zr, zr, eq
+; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vmov r0, s8
@@ -1387,14 +1387,14 @@ define arm_aapcs_vfpcc <8 x half> @copys
; CHECK-NEXT: ldrb.w r0, [sp, #5]
; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: tst.w r0, #128
-; CHECK-NEXT: csinc r0, zr, zr, eq
+; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q1[6], r0
; CHECK-NEXT: ldrb.w r0, [sp, #1]
; CHECK-NEXT: tst.w r0, #128
-; CHECK-NEXT: csinc r0, zr, zr, eq
+; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s0, s0, s2
; CHECK-NEXT: vmov r0, s0
Modified: llvm/trunk/test/CodeGen/Thumb2/mve-minmax.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-minmax.ll?rev=370745&r1=370744&r2=370745&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-minmax.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-minmax.ll Tue Sep 3 04:30:54 2019
@@ -55,13 +55,13 @@ define arm_aapcs_vfpcc <2 x i64> @smin_v
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: csinv r1, zr, zr, eq
+; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: subs r2, r3, r2
; CHECK-NEXT: sbcs.w r2, lr, r12
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov.32 q2[2], r1
@@ -129,13 +129,13 @@ define arm_aapcs_vfpcc <2 x i64> @umin_v
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r1, #1
; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: csinv r1, zr, zr, eq
+; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: subs r2, r3, r2
; CHECK-NEXT: sbcs.w r2, lr, r12
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov.32 q2[2], r1
@@ -204,13 +204,13 @@ define arm_aapcs_vfpcc <2 x i64> @smax_v
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: csinv r1, zr, zr, eq
+; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: subs r2, r3, r2
; CHECK-NEXT: sbcs.w r2, lr, r12
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov.32 q2[2], r1
@@ -278,13 +278,13 @@ define arm_aapcs_vfpcc <2 x i64> @umax_v
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r1, #1
; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: csinv r1, zr, zr, eq
+; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: subs r2, r3, r2
; CHECK-NEXT: sbcs.w r2, lr, r12
; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov.32 q2[2], r1
@@ -386,14 +386,14 @@ define arm_aapcs_vfpcc <2 x double> @max
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csinv r4, zr, zr, eq
+; CHECK-NEXT: csetm r4, ne
; CHECK-NEXT: mov r0, r12
; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q0[0], r0
; CHECK-NEXT: vmov.32 q0[1], r0
; CHECK-NEXT: vmov.32 q0[2], r4
Modified: llvm/trunk/test/CodeGen/Thumb2/mve-pred-and.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-pred-and.ll?rev=370745&r1=370744&r2=370745&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-pred-and.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-pred-and.ll Tue Sep 3 04:30:54 2019
@@ -612,16 +612,16 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz
; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s10
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s11
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vbic q1, q1, q3
@@ -648,9 +648,9 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s7
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s11
@@ -659,24 +659,24 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_
; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s0
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vand q2, q2, q3
@@ -700,9 +700,9 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqr
; CHECK-NEXT: eors r2, r1
; CHECK-NEXT: eors r3, r0
; CHECK-NEXT: orrs r2, r3
-; CHECK-NEXT: csinc r2, zr, zr, ne
+; CHECK-NEXT: cset r2, eq
; CHECK-NEXT: tst.w r2, #1
-; CHECK-NEXT: csinv r2, zr, zr, eq
+; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: vmov.32 q2[0], r2
; CHECK-NEXT: vmov.32 q2[1], r2
; CHECK-NEXT: vmov r2, s7
@@ -711,24 +711,24 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqr
; CHECK-NEXT: eors r0, r2
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s0
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vand q2, q3, q2
Modified: llvm/trunk/test/CodeGen/Thumb2/mve-pred-bitcast.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-pred-bitcast.ll?rev=370745&r1=370744&r2=370745&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-pred-bitcast.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-pred-bitcast.ll Tue Sep 3 04:30:54 2019
@@ -155,9 +155,9 @@ define arm_aapcs_vfpcc i2 @bitcast_from_
; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s3
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: orrs r1, r2
-; CHECK-NEXT: csinc r1, zr, zr, ne
+; CHECK-NEXT: cset r1, eq
; CHECK-NEXT: ands r1, r1, #1
; CHECK-NEXT: it ne
; CHECK-NEXT: mvnne r1, #1
Modified: llvm/trunk/test/CodeGen/Thumb2/mve-pred-build-var.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-pred-build-var.ll?rev=370745&r1=370744&r2=370745&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-pred-build-var.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-pred-build-var.ll Tue Sep 3 04:30:54 2019
@@ -7,7 +7,7 @@ define arm_aapcs_vfpcc <4 x i32> @build_
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r1, #0
-; CHECK-NEXT: csinc r0, zr, zr, hs
+; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #0, #4
@@ -26,7 +26,7 @@ define arm_aapcs_vfpcc <4 x i32> @build_
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r1, #0
-; CHECK-NEXT: csinc r0, zr, zr, hs
+; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #12, #4
@@ -45,7 +45,7 @@ define arm_aapcs_vfpcc <4 x i32> @build_
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r1, #0
-; CHECK-NEXT: csinc r0, zr, zr, hs
+; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #0, #4
@@ -69,7 +69,7 @@ define arm_aapcs_vfpcc <8 x i16> @build_
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r1, #0
-; CHECK-NEXT: csinc r0, zr, zr, hs
+; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #0, #2
@@ -88,7 +88,7 @@ define arm_aapcs_vfpcc <8 x i16> @build_
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r1, #0
-; CHECK-NEXT: csinc r0, zr, zr, hs
+; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #6, #2
@@ -107,7 +107,7 @@ define arm_aapcs_vfpcc <8 x i16> @build_
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r1, #0
-; CHECK-NEXT: csinc r0, zr, zr, hs
+; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #0, #2
@@ -135,7 +135,7 @@ define arm_aapcs_vfpcc <16 x i8> @build_
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r1, #0
-; CHECK-NEXT: csinc r0, zr, zr, hs
+; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #0, #1
@@ -154,7 +154,7 @@ define arm_aapcs_vfpcc <16 x i8> @build_
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r1, #0
-; CHECK-NEXT: csinc r0, zr, zr, hs
+; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #3, #1
@@ -173,7 +173,7 @@ define arm_aapcs_vfpcc <16 x i8> @build_
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r1, #0
-; CHECK-NEXT: csinc r0, zr, zr, hs
+; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #0, #1
@@ -208,7 +208,7 @@ define arm_aapcs_vfpcc <2 x i64> @build_
; CHECK-LABEL: build_var0_v2i1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
-; CHECK-NEXT: csinc r0, zr, zr, hs
+; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: vmov s8, r0
@@ -234,7 +234,7 @@ define arm_aapcs_vfpcc <2 x i64> @build_
; CHECK-LABEL: build_var1_v2i1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
-; CHECK-NEXT: csinc r0, zr, zr, hs
+; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: vmov s10, r0
@@ -260,7 +260,7 @@ define arm_aapcs_vfpcc <2 x i64> @build_
; CHECK-LABEL: build_varN_v2i1:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1
-; CHECK-NEXT: csinc r0, zr, zr, hs
+; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: vdup.32 q2, r0
Modified: llvm/trunk/test/CodeGen/Thumb2/mve-pred-ext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-pred-ext.ll?rev=370745&r1=370744&r2=370745&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-pred-ext.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-pred-ext.ll Tue Sep 3 04:30:54 2019
@@ -57,13 +57,13 @@ define arm_aapcs_vfpcc <2 x i64> @sext_v
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: sbcs.w r1, r2, r1
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r2, #1
; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: csinv r1, zr, zr, eq
+; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov.32 q0[0], r1
; CHECK-NEXT: vmov.32 q0[1], r1
; CHECK-NEXT: vmov.32 q0[2], r0
@@ -134,13 +134,13 @@ define arm_aapcs_vfpcc <2 x i64> @zext_v
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: csinv r1, zr, zr, eq
+; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: sbcs.w r2, r0, r2
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q0[0], r0
; CHECK-NEXT: vmov.32 q0[2], r1
; CHECK-NEXT: vand q0, q0, q1
Modified: llvm/trunk/test/CodeGen/Thumb2/mve-pred-loadstore.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-pred-loadstore.ll?rev=370745&r1=370744&r2=370745&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-pred-loadstore.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-pred-loadstore.ll Tue Sep 3 04:30:54 2019
@@ -167,9 +167,9 @@ define arm_aapcs_vfpcc void @store_v2i1(
; CHECK-LE-NEXT: vmov r3, s2
; CHECK-LE-NEXT: orrs r1, r2
; CHECK-LE-NEXT: vmov r2, s3
-; CHECK-LE-NEXT: csinc r1, zr, zr, ne
+; CHECK-LE-NEXT: cset r1, eq
; CHECK-LE-NEXT: orrs r2, r3
-; CHECK-LE-NEXT: csinc r2, zr, zr, ne
+; CHECK-LE-NEXT: cset r2, eq
; CHECK-LE-NEXT: ands r2, r2, #1
; CHECK-LE-NEXT: it ne
; CHECK-LE-NEXT: mvnne r2, #1
@@ -186,9 +186,9 @@ define arm_aapcs_vfpcc void @store_v2i1(
; CHECK-BE-NEXT: vmov r3, s5
; CHECK-BE-NEXT: orrs r1, r2
; CHECK-BE-NEXT: vmov r2, s4
-; CHECK-BE-NEXT: csinc r1, zr, zr, ne
+; CHECK-BE-NEXT: cset r1, eq
; CHECK-BE-NEXT: orrs r2, r3
-; CHECK-BE-NEXT: csinc r2, zr, zr, ne
+; CHECK-BE-NEXT: cset r2, eq
; CHECK-BE-NEXT: ands r2, r2, #1
; CHECK-BE-NEXT: it ne
; CHECK-BE-NEXT: mvnne r2, #1
Modified: llvm/trunk/test/CodeGen/Thumb2/mve-pred-not.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-pred-not.ll?rev=370745&r1=370744&r2=370745&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-pred-not.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-pred-not.ll Tue Sep 3 04:30:54 2019
@@ -327,16 +327,16 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vbic q0, q0, q2
@@ -357,16 +357,16 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vbic q0, q0, q2
Modified: llvm/trunk/test/CodeGen/Thumb2/mve-pred-or.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-pred-or.ll?rev=370745&r1=370744&r2=370745&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-pred-or.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-pred-or.ll Tue Sep 3 04:30:54 2019
@@ -425,32 +425,32 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz
; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s6
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s0
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vorr q2, q3, q2
@@ -478,9 +478,9 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s7
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s11
@@ -489,24 +489,24 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_
; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s0
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vorr q2, q2, q3
Modified: llvm/trunk/test/CodeGen/Thumb2/mve-pred-xor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-pred-xor.ll?rev=370745&r1=370744&r2=370745&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-pred-xor.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-pred-xor.ll Tue Sep 3 04:30:54 2019
@@ -461,32 +461,32 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeqz
; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s6
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s0
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: veor q2, q3, q2
@@ -514,9 +514,9 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s7
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s11
@@ -525,24 +525,24 @@ define arm_aapcs_vfpcc <2 x i64> @cmpeq_
; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s0
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: veor q2, q2, q3
Modified: llvm/trunk/test/CodeGen/Thumb2/mve-vcmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-vcmp.ll?rev=370745&r1=370744&r2=370745&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-vcmp.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-vcmp.ll Tue Sep 3 04:30:54 2019
@@ -378,9 +378,9 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_e
; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s3
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q4[0], r0
; CHECK-NEXT: vmov.32 q4[1], r0
; CHECK-NEXT: vmov r0, s7
@@ -388,9 +388,9 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_e
; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q4[2], r0
; CHECK-NEXT: vmov.32 q4[3], r0
; CHECK-NEXT: vbic q0, q3, q4
@@ -418,9 +418,9 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_e
; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s3
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q4[0], r0
; CHECK-NEXT: vmov.32 q4[1], r0
; CHECK-NEXT: vmov r0, s7
@@ -428,9 +428,9 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_e
; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q4[2], r0
; CHECK-NEXT: vmov.32 q4[3], r0
; CHECK-NEXT: vbic q0, q3, q4
@@ -457,16 +457,16 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_m
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vbic q0, q2, q3
@@ -479,7 +479,7 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_m
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: csinv r1, zr, zr, eq
+; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov.32 q3[0], r1
; CHECK-NEXT: vmov.32 q3[1], r1
; CHECK-NEXT: vmov r1, s2
@@ -489,33 +489,33 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_m
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp.w lr, #0
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
-; CHECK-NEXT: csinc r0, zr, zr, eq
+; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: vmov.32 q4[0], r0
; CHECK-NEXT: vmov.32 q4[1], r0
-; CHECK-NEXT: csinc r0, zr, zr, eq
+; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q4[2], r0
; CHECK-NEXT: vmov.32 q4[3], r0
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csinc r0, zr, zr, eq
+; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q5[0], r0
; CHECK-NEXT: vmov.32 q5[1], r0
; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csinc r0, zr, zr, eq
+; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q5[2], r0
; CHECK-NEXT: vmov.32 q5[3], r0
; CHECK-NEXT: vand q1, q5, q4
Modified: llvm/trunk/test/CodeGen/Thumb2/mve-vcmpf.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-vcmpf.ll?rev=370745&r1=370744&r2=370745&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-vcmpf.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-vcmpf.ll Tue Sep 3 04:30:54 2019
@@ -12,27 +12,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s1, s5
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -69,7 +69,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
@@ -78,7 +78,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1
@@ -87,14 +87,14 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s7
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -129,27 +129,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -181,27 +181,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -233,27 +233,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -285,27 +285,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -342,7 +342,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
@@ -351,7 +351,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r3, #1
@@ -360,14 +360,14 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s7
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -401,27 +401,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s1, s5
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -453,27 +453,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -506,27 +506,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -559,27 +559,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -612,27 +612,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -665,27 +665,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -720,27 +720,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -780,7 +780,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -791,7 +791,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
@@ -806,7 +806,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
@@ -819,7 +819,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -832,7 +832,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15
@@ -846,7 +846,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -859,7 +859,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
@@ -868,7 +868,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1
@@ -905,7 +905,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
@@ -919,7 +919,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
@@ -937,7 +937,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
; CHECK-MVE-NEXT: vmov r1, s20
@@ -952,7 +952,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
@@ -968,7 +968,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10
; CHECK-MVE-NEXT: vmov r1, s20
@@ -983,7 +983,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
@@ -999,7 +999,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -1009,7 +1009,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov.16 q4[6], r1
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
@@ -1047,7 +1047,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -1058,7 +1058,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmpe.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
@@ -1073,7 +1073,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
@@ -1086,7 +1086,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -1099,7 +1099,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15
@@ -1113,7 +1113,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -1126,7 +1126,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
@@ -1135,7 +1135,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1
@@ -1171,7 +1171,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -1182,7 +1182,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmpe.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
@@ -1197,7 +1197,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
@@ -1210,7 +1210,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -1223,7 +1223,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15
@@ -1237,7 +1237,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -1250,7 +1250,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
@@ -1259,7 +1259,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1
@@ -1295,7 +1295,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -1306,7 +1306,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmpe.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
@@ -1321,7 +1321,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
@@ -1334,7 +1334,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -1347,7 +1347,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15
@@ -1361,7 +1361,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -1374,7 +1374,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
@@ -1383,7 +1383,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1
@@ -1419,7 +1419,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -1430,7 +1430,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmpe.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
@@ -1445,7 +1445,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
@@ -1458,7 +1458,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -1471,7 +1471,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15
@@ -1485,7 +1485,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -1498,7 +1498,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
@@ -1507,7 +1507,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1
@@ -1544,7 +1544,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
@@ -1558,7 +1558,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
@@ -1576,7 +1576,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
; CHECK-MVE-NEXT: vmov r1, s20
@@ -1591,7 +1591,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
@@ -1607,7 +1607,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10
; CHECK-MVE-NEXT: vmov r1, s20
@@ -1622,7 +1622,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
@@ -1638,7 +1638,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -1648,7 +1648,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov.16 q4[6], r1
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
@@ -1685,7 +1685,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -1696,7 +1696,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
@@ -1711,7 +1711,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
@@ -1724,7 +1724,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -1737,7 +1737,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15
@@ -1751,7 +1751,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -1764,7 +1764,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
@@ -1773,7 +1773,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1
@@ -1809,7 +1809,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -1820,7 +1820,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmpe.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
@@ -1835,7 +1835,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
@@ -1848,7 +1848,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -1861,7 +1861,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15
@@ -1875,7 +1875,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -1888,7 +1888,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
@@ -1897,7 +1897,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1
@@ -1934,7 +1934,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -1945,7 +1945,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmpe.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
@@ -1960,7 +1960,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
@@ -1973,7 +1973,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -1986,7 +1986,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15
@@ -2000,7 +2000,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -2013,7 +2013,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
@@ -2022,7 +2022,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1
@@ -2059,7 +2059,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -2070,7 +2070,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmpe.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
@@ -2085,7 +2085,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
@@ -2098,7 +2098,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -2111,7 +2111,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15
@@ -2125,7 +2125,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -2138,7 +2138,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
@@ -2147,7 +2147,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1
@@ -2184,7 +2184,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -2195,7 +2195,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmpe.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
@@ -2210,7 +2210,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
@@ -2223,7 +2223,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -2236,7 +2236,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15
@@ -2250,7 +2250,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -2263,7 +2263,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
@@ -2272,7 +2272,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1
@@ -2309,7 +2309,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -2320,7 +2320,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmpe.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
@@ -2335,7 +2335,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
@@ -2348,7 +2348,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -2361,7 +2361,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15
@@ -2375,7 +2375,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -2388,7 +2388,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
@@ -2397,7 +2397,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1
@@ -2436,7 +2436,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -2447,7 +2447,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmpe.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1
@@ -2462,7 +2462,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
@@ -2475,7 +2475,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -2488,7 +2488,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15
@@ -2502,7 +2502,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -2515,7 +2515,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11
@@ -2524,7 +2524,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1
Modified: llvm/trunk/test/CodeGen/Thumb2/mve-vcmpfr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-vcmpfr.ll?rev=370745&r1=370744&r2=370745&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-vcmpfr.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-vcmpfr.ll Tue Sep 3 04:30:54 2019
@@ -12,27 +12,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s1, s4
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -72,7 +72,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
@@ -81,7 +81,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1
@@ -90,14 +90,14 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s4
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -136,27 +136,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s4
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s4
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s4
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -191,27 +191,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s4
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s4
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s4
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -246,27 +246,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s4
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s4
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s4
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -302,27 +302,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s4
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s4
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s4
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -363,7 +363,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
@@ -372,7 +372,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r3, #1
@@ -381,14 +381,14 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s4
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -426,27 +426,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s1, s4
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -481,27 +481,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s4
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s4
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s4
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -538,27 +538,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s4
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s4
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s4
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -595,27 +595,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s4
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s4
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s4
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -651,27 +651,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s4
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s4
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s4
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -707,27 +707,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s4
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s4
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s4
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -766,27 +766,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s4
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s4
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s4
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -832,7 +832,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s16
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
@@ -841,7 +841,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, s16
@@ -856,7 +856,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18
@@ -868,7 +868,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s16
@@ -881,7 +881,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18
@@ -893,7 +893,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s16
@@ -906,7 +906,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -917,7 +917,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0
@@ -959,7 +959,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: mov.w r2, #0
@@ -971,7 +971,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s16
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
@@ -988,7 +988,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18
@@ -1003,7 +1003,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
@@ -1017,7 +1017,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18
@@ -1032,7 +1032,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -1048,7 +1048,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -1059,7 +1059,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0
@@ -1104,7 +1104,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
@@ -1113,7 +1113,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, s16
@@ -1128,7 +1128,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18
@@ -1140,7 +1140,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, s16
@@ -1153,7 +1153,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18
@@ -1165,7 +1165,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, s16
@@ -1178,7 +1178,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -1189,7 +1189,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0
@@ -1230,7 +1230,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
@@ -1239,7 +1239,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, s16
@@ -1254,7 +1254,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18
@@ -1266,7 +1266,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, s16
@@ -1279,7 +1279,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18
@@ -1291,7 +1291,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, s16
@@ -1304,7 +1304,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -1315,7 +1315,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0
@@ -1356,7 +1356,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
@@ -1365,7 +1365,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, s16
@@ -1380,7 +1380,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18
@@ -1392,7 +1392,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, s16
@@ -1405,7 +1405,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18
@@ -1417,7 +1417,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, s16
@@ -1430,7 +1430,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -1441,7 +1441,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0
@@ -1483,7 +1483,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
@@ -1492,7 +1492,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, s16
@@ -1507,7 +1507,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18
@@ -1519,7 +1519,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, s16
@@ -1532,7 +1532,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18
@@ -1544,7 +1544,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, s16
@@ -1557,7 +1557,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -1568,7 +1568,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0
@@ -1611,7 +1611,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: mov.w r2, #0
@@ -1623,7 +1623,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s16
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
@@ -1640,7 +1640,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18
@@ -1655,7 +1655,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
@@ -1669,7 +1669,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18
@@ -1684,7 +1684,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -1700,7 +1700,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -1711,7 +1711,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0
@@ -1755,7 +1755,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s16
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
@@ -1764,7 +1764,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, s16
@@ -1779,7 +1779,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18
@@ -1791,7 +1791,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s16
@@ -1804,7 +1804,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18
@@ -1816,7 +1816,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s16
@@ -1829,7 +1829,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -1840,7 +1840,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0
@@ -1881,7 +1881,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
@@ -1890,7 +1890,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, s16
@@ -1905,7 +1905,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18
@@ -1917,7 +1917,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, s16
@@ -1930,7 +1930,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18
@@ -1942,7 +1942,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, s16
@@ -1955,7 +1955,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -1966,7 +1966,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0
@@ -2009,7 +2009,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
@@ -2018,7 +2018,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, s16
@@ -2033,7 +2033,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18
@@ -2045,7 +2045,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, s16
@@ -2058,7 +2058,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18
@@ -2070,7 +2070,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, s16
@@ -2083,7 +2083,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -2094,7 +2094,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0
@@ -2137,7 +2137,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
@@ -2146,7 +2146,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, s16
@@ -2161,7 +2161,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18
@@ -2173,7 +2173,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, s16
@@ -2186,7 +2186,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18
@@ -2198,7 +2198,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, s16
@@ -2211,7 +2211,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -2222,7 +2222,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0
@@ -2264,7 +2264,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
@@ -2273,7 +2273,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, s16
@@ -2288,7 +2288,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18
@@ -2300,7 +2300,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, s16
@@ -2313,7 +2313,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18
@@ -2325,7 +2325,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, s16
@@ -2338,7 +2338,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -2349,7 +2349,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0
@@ -2391,7 +2391,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
@@ -2400,7 +2400,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, s16
@@ -2415,7 +2415,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18
@@ -2427,7 +2427,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, s16
@@ -2440,7 +2440,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18
@@ -2452,7 +2452,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, s16
@@ -2465,7 +2465,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -2476,7 +2476,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0
@@ -2521,7 +2521,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9
@@ -2530,7 +2530,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, s16
@@ -2545,7 +2545,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18
@@ -2557,7 +2557,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, s16
@@ -2570,7 +2570,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18
@@ -2582,7 +2582,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, s16
@@ -2595,7 +2595,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -2606,7 +2606,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0
Modified: llvm/trunk/test/CodeGen/Thumb2/mve-vcmpfz.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-vcmpfz.ll?rev=370745&r1=370744&r2=370745&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-vcmpfz.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-vcmpfz.ll Tue Sep 3 04:30:54 2019
@@ -12,27 +12,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -69,7 +69,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
@@ -78,7 +78,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1
@@ -87,14 +87,14 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -130,27 +130,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, #0
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, #0
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -182,27 +182,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, #0
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, #0
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -234,27 +234,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, #0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, #0
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -286,27 +286,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, #0
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, #0
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -343,7 +343,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: mov.w r2, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
@@ -352,7 +352,7 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: mov.w r3, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r3, #1
@@ -361,14 +361,14 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -403,27 +403,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -455,27 +455,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, #0
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, #0
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -508,27 +508,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, #0
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, #0
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -561,27 +561,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, #0
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, #0
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -614,27 +614,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, #0
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, #0
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -667,27 +667,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s1
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s2
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s3
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -723,27 +723,27 @@ define arm_aapcs_vfpcc <4 x float> @vcmp
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s1
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s2
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s3
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: csinc r3, zr, zr, eq
+; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31
@@ -784,7 +784,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
@@ -793,7 +793,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
@@ -808,7 +808,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
@@ -821,7 +821,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
@@ -834,7 +834,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16
@@ -846,7 +846,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
@@ -859,7 +859,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -868,7 +868,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1
@@ -905,7 +905,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -917,7 +917,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
@@ -935,7 +935,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16
@@ -950,7 +950,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
@@ -964,7 +964,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16
@@ -979,7 +979,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -995,7 +995,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -1005,7 +1005,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov.16 q3[6], r1
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
@@ -1044,7 +1044,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
@@ -1053,7 +1053,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, #0
@@ -1068,7 +1068,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
@@ -1081,7 +1081,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, #0
@@ -1094,7 +1094,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16
@@ -1106,7 +1106,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, #0
@@ -1119,7 +1119,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -1128,7 +1128,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1
@@ -1164,7 +1164,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
@@ -1173,7 +1173,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, #0
@@ -1188,7 +1188,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
@@ -1201,7 +1201,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, #0
@@ -1214,7 +1214,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16
@@ -1226,7 +1226,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, #0
@@ -1239,7 +1239,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -1248,7 +1248,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1
@@ -1284,7 +1284,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
@@ -1293,7 +1293,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, #0
@@ -1308,7 +1308,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
@@ -1321,7 +1321,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, #0
@@ -1334,7 +1334,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16
@@ -1346,7 +1346,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, #0
@@ -1359,7 +1359,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -1368,7 +1368,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1
@@ -1404,7 +1404,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
@@ -1413,7 +1413,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, #0
@@ -1428,7 +1428,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
@@ -1441,7 +1441,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, #0
@@ -1454,7 +1454,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16
@@ -1466,7 +1466,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, #0
@@ -1479,7 +1479,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -1488,7 +1488,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1
@@ -1525,7 +1525,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31
@@ -1537,7 +1537,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
@@ -1555,7 +1555,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16
@@ -1570,7 +1570,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
@@ -1584,7 +1584,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16
@@ -1599,7 +1599,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -1615,7 +1615,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -1625,7 +1625,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov.16 q3[6], r1
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
@@ -1663,7 +1663,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
@@ -1672,7 +1672,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
@@ -1687,7 +1687,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
@@ -1700,7 +1700,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
@@ -1713,7 +1713,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16
@@ -1725,7 +1725,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
@@ -1738,7 +1738,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -1747,7 +1747,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1
@@ -1783,7 +1783,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
@@ -1792,7 +1792,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, #0
@@ -1807,7 +1807,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
@@ -1820,7 +1820,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, #0
@@ -1833,7 +1833,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16
@@ -1845,7 +1845,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, #0
@@ -1858,7 +1858,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -1867,7 +1867,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1
@@ -1904,7 +1904,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
@@ -1913,7 +1913,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, #0
@@ -1928,7 +1928,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
@@ -1941,7 +1941,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, #0
@@ -1954,7 +1954,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16
@@ -1966,7 +1966,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, #0
@@ -1979,7 +1979,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -1988,7 +1988,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1
@@ -2025,7 +2025,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
@@ -2034,7 +2034,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, #0
@@ -2049,7 +2049,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
@@ -2062,7 +2062,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, #0
@@ -2075,7 +2075,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16
@@ -2087,7 +2087,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, #0
@@ -2100,7 +2100,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -2109,7 +2109,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1
@@ -2146,7 +2146,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
@@ -2155,7 +2155,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, #0
@@ -2170,7 +2170,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
@@ -2183,7 +2183,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, #0
@@ -2196,7 +2196,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16
@@ -2208,7 +2208,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, #0
@@ -2221,7 +2221,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -2230,7 +2230,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1
@@ -2267,7 +2267,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
@@ -2276,7 +2276,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, s1
@@ -2291,7 +2291,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
@@ -2304,7 +2304,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, s2
@@ -2317,7 +2317,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16
@@ -2329,7 +2329,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, s3
@@ -2342,7 +2342,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -2351,7 +2351,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1
@@ -2391,7 +2391,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0
@@ -2400,7 +2400,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: csinc r2, zr, zr, eq
+; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, s1
@@ -2415,7 +2415,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
@@ -2428,7 +2428,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, s2
@@ -2441,7 +2441,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16
@@ -2453,7 +2453,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, s3
@@ -2466,7 +2466,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: csinc r1, zr, zr, eq
+; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11
@@ -2475,7 +2475,7 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: csinc r0, zr, zr, eq
+; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1
Modified: llvm/trunk/test/CodeGen/Thumb2/mve-vcmpr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-vcmpr.ll?rev=370745&r1=370744&r2=370745&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-vcmpr.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-vcmpr.ll Tue Sep 3 04:30:54 2019
@@ -444,9 +444,9 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_e
; CHECK-NEXT: eors r2, r1
; CHECK-NEXT: eors r3, r0
; CHECK-NEXT: orrs r2, r3
-; CHECK-NEXT: csinc r2, zr, zr, ne
+; CHECK-NEXT: cset r2, eq
; CHECK-NEXT: tst.w r2, #1
-; CHECK-NEXT: csinv r2, zr, zr, eq
+; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: vmov.32 q3[0], r2
; CHECK-NEXT: vmov.32 q3[1], r2
; CHECK-NEXT: vmov r2, s3
@@ -454,9 +454,9 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_e
; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: eors r0, r2
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vbic q0, q2, q3
@@ -479,9 +479,9 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_e
; CHECK-NEXT: eors r2, r1
; CHECK-NEXT: eors r3, r0
; CHECK-NEXT: orrs r2, r3
-; CHECK-NEXT: csinc r2, zr, zr, ne
+; CHECK-NEXT: cset r2, eq
; CHECK-NEXT: tst.w r2, #1
-; CHECK-NEXT: csinv r2, zr, zr, eq
+; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: vmov.32 q3[0], r2
; CHECK-NEXT: vmov.32 q3[1], r2
; CHECK-NEXT: vmov r2, s3
@@ -489,9 +489,9 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_e
; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: eors r0, r2
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vbic q0, q2, q3
@@ -519,16 +519,16 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_m
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vbic q0, q2, q3
@@ -541,7 +541,7 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_m
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: csinv r1, zr, zr, eq
+; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov.32 q3[0], r1
; CHECK-NEXT: vmov.32 q3[1], r1
; CHECK-NEXT: vmov r1, s2
@@ -551,33 +551,33 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_m
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp.w lr, #0
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
-; CHECK-NEXT: csinc r0, zr, zr, eq
+; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: vmov.32 q4[0], r0
; CHECK-NEXT: vmov.32 q4[1], r0
-; CHECK-NEXT: csinc r0, zr, zr, eq
+; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q4[2], r0
; CHECK-NEXT: vmov.32 q4[3], r0
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csinc r0, zr, zr, eq
+; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q5[0], r0
; CHECK-NEXT: vmov.32 q5[1], r0
; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csinc r0, zr, zr, eq
+; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q5[2], r0
; CHECK-NEXT: vmov.32 q5[3], r0
; CHECK-NEXT: vand q1, q5, q4
Modified: llvm/trunk/test/CodeGen/Thumb2/mve-vcmpz.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/mve-vcmpz.ll?rev=370745&r1=370744&r2=370745&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/mve-vcmpz.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/mve-vcmpz.ll Tue Sep 3 04:30:54 2019
@@ -365,16 +365,16 @@ define arm_aapcs_vfpcc <2 x i64> @vcmp_e
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vbic q0, q2, q3
@@ -394,16 +394,16 @@ define arm_aapcs_vfpcc <2 x i32> @vcmp_e
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1
-; CHECK-NEXT: csinc r0, zr, zr, ne
+; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1
-; CHECK-NEXT: csinv r0, zr, zr, eq
+; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vbic q0, q2, q3
Modified: llvm/trunk/test/MC/ARM/thumbv8.1m.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumbv8.1m.s?rev=370745&r1=370744&r2=370745&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumbv8.1m.s (original)
+++ llvm/trunk/test/MC/ARM/thumbv8.1m.s Tue Sep 3 04:30:54 2019
@@ -1119,21 +1119,33 @@ csel r0, r0, r1, eq
// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14
csel sp, r0, r1, eq
+// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14
+csel pc, r0, r1, eq
// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
csel r0, sp, r1, eq
+// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
+csel r0, pc, r1, eq
// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
csinc r0, sp, r1, eq
+// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
+csinc r0, pc, r1, eq
// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
csinv r0, sp, r1, eq
+// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
+csinv r0, pc, r1, eq
// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
csneg r0, sp, r1, eq
+// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
+csneg r0, pc, r1, eq
// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
csel r0, r0, sp, eq
+// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
+csel r0, r0, pc, eq
// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instructions in IT block must be predicable
it eq
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