[PATCH] D67036: [CodeGen] Use FSHR in DAGTypeLegalizer::ExpandIntRes_MULFIX

[Bjorn Pettersson via Phabricator via llvm-commits]

bjope created this revision.
bjope added reviewers: leonardchan, RKSimon.
Herald added subscribers: pzheng, s.egerton, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, asb, hiraditya.
Herald added a project: LLVM.

Simplify the right shift of the intermediate result (given
in four parts) by using funnel shift.

There are some impact on lit tests, but that seems to be
related to register allocation differences due to how FSHR
is expanded on X86 (giving a slightly different operand order
for the explicit OR operations compared to the old code).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D67036

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/test/CodeGen/RISCV/addcarry.ll
  llvm/test/CodeGen/X86/smul_fix.ll
  llvm/test/CodeGen/X86/smul_fix_sat.ll
  llvm/test/CodeGen/X86/umul_fix.ll

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