[PATCH] D67027: [AArch64][GlobalISel] Don't import i64imm_32bit pattern at -O0

[Jessica Paquette via Phabricator via llvm-commits]

paquette created this revision.
paquette added a reviewer: aemerson.
Herald added subscribers: Petar.Avramovic, hiraditya, kristof.beyls, javed.absar, rovka.
Herald added a project: LLVM.

This pattern, when imported at -O0 adds an extra copy via the SUBREG_TO_REG.

This is because the copy from the SUBREG_TO_REG is not eliminated. At all other opt levels, it is eliminated.

This is a 1% geomean code size savings at -O0 on CTMark.

Also I tried my hardest to make that predicate fit into 80 columns, but it wasn't meant to be. If you do that, it will not be properly imported into AArch64GenDAGISel.inc.

E.g. if you do this:

  def OptimizedGISelOrOtherSelector : Predicate<[{
    !MF->getFunction().hasOptNone() ||
    MF->getProperties().hasProperty(MachineFunctionProperties::Property::FailedISel) ||
    !MF->getProperties().hasProperty(MachineFunctionProperties::Property::Legalized)
  }]>;

You get amazing things like this in AArch64GenDAGISel.inc:

  /* 63221*/        OPC_CheckPatternPredicate, 21, // (
      !MF->getFunction().hasOptNone() ||
      MF->getProperties().hasProperty(MachineFunctionProperties::Property::FailedISel) ||
      !MF->getProperties().hasProperty(MachineFunctionProperties::Property::Legalized)
    )




https://reviews.llvm.org/D67027

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir


Index: llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
@@ -13,6 +13,9 @@
   define i64 @fconst_s64() { ret i64 1234567890123 }
   define float @fconst_s32_0() { ret float 0.0 }
   define double @fconst_s64_0() { ret double 0.0 }
+
+  define void @optnone_i64() optnone noinline { ret void }
+  define void @opt_i64() { ret void }
 ...
 
 ---
@@ -140,3 +143,32 @@
     %0(s64) = G_FCONSTANT double 0.0
     $x0 = COPY %0(s64)
 ...
+---
+name:            optnone_i64
+legalized:       true
+regBankSelected: true
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: optnone_i64
+    ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 42
+    ; CHECK: $x0 = COPY [[MOVi64imm]]
+    ; CHECK: RET_ReallyLR implicit $x0
+    %0:gpr(s64) = G_CONSTANT i64 42
+    $x0 = COPY %0(s64)
+    RET_ReallyLR implicit $x0
+...
+---
+name:            opt_i64
+legalized:       true
+regBankSelected: true
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: opt_i64
+    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
+    ; CHECK: $x0 = COPY [[SUBREG_TO_REG]]
+    ; CHECK: RET_ReallyLR implicit $x0
+    %0:gpr(s64) = G_CONSTANT i64 42
+    $x0 = COPY %0(s64)
+    RET_ReallyLR implicit $x0
+...
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -437,6 +437,13 @@
 
   def UseBTI : Predicate<[{ MF->getFunction().hasFnAttribute("branch-target-enforcement") }]>;
   def NotUseBTI : Predicate<[{ !MF->getFunction().hasFnAttribute("branch-target-enforcement") }]>;
+
+  // Toggles patterns which aren't beneficial in GlobalISel when we aren't
+  // optimizing. This allows us to selectively use patterns without impacting
+  // SelectionDAG's behaviour.
+  // FIXME: One day there will probably be a nicer way to check for this, but
+  // today is not that day.
+  def OptimizedGISelOrOtherSelector : Predicate<"!MF->getFunction().hasOptNone() || MF->getProperties().hasProperty(MachineFunctionProperties::Property::FailedISel) || !MF->getProperties().hasProperty(MachineFunctionProperties::Property::Legalized)">;
 }
 
 include "AArch64InstrFormats.td"
@@ -940,8 +947,12 @@
 def gi_trunc_imm : GICustomOperandRenderer<"renderTruncImm">,
   GISDNodeXFormEquiv<trunc_imm>;
 
+let Predicates = [OptimizedGISelOrOtherSelector] in {
+// The SUBREG_TO_REG isn't eliminated at -O0, which can result in pointless
+// copies.
 def : Pat<(i64 i64imm_32bit:$src),
           (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
+}
 
 // Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model).
 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{


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