[PATCH] D67021: [DAGCombiner] improve throughput of shift+logic+shift

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: lebedev.ri, RKSimon, craig.topper.
Herald added subscribers: hiraditya, kristof.beyls, javed.absar, mcrosier.
Herald added a project: LLVM.

The motivating case for this is a long way from here:
https://bugs.llvm.org/show_bug.cgi?id=43146
...but I think this is where we have to start.

We need to canonicalize/optimize sequences of shift and logic to ease pattern matching for things like bswap and improve perf in general. But without the artificial limit of '!LegalTypes' (early combining), there are a lot of test diffs, and not all are good.

In the minimal tests added for this proposal, x86 should have better throughput in all cases. AArch64 is neutral because it can fold shifts into bitwise logic ops.

There are 3 shift opcodes and 3 logic opcodes for a total of 9 possible patterns:
https://rise4fun.com/Alive/VlI
https://rise4fun.com/Alive/n1m
https://rise4fun.com/Alive/1Vn


https://reviews.llvm.org/D67021

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/bitfield-insert.ll
  llvm/test/CodeGen/AArch64/shift-logic.ll
  llvm/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll
  llvm/test/CodeGen/X86/shift-logic.ll

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