[PATCH] D66801: [X86][BtVer2] Fix latency and throughput of conditional SIMD store instructions.

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb updated this revision to Diff 218122.
andreadb added a comment.
Herald added a reviewer: lebedev.ri.
Herald added a subscriber: lebedev.ri.

Patch updated.

Address review comments.

This patch replaces the existing writes for conditional SIMD stores (i.e. WriteFMaskedStore, and WriteFMaskedStoreY) with the following new writes:

- WriteFMaskedStore32     [ XMM Packed Single ]
- WriteFMaskedStore32Y   [ YMM Packed Single ]
- WriteFMaskedStore64     [ XMM Packed Double ]
- WriteFMaskedStore64T   [ YMM Packed Double ]

Added a wrapper class named X86SchedWriteMaskMove in X86Schedule.td to describe both RM and MR variants for conditional SIMD moves in a single tablegen definition.
Instances of that class are then passed in input to multiclass avx_movmask_rm when constructing MASKMOVPS/PD definitions.

Since this patch introduces new writes, I had to update all the X86 scheduling models.

This patch is a NFC for all x86 models except BtVer2.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66801/new/

https://reviews.llvm.org/D66801

Files:
  lib/Target/X86/X86InstrSSE.td
  lib/Target/X86/X86SchedBroadwell.td
  lib/Target/X86/X86SchedHaswell.td
  lib/Target/X86/X86SchedSandyBridge.td
  lib/Target/X86/X86SchedSkylakeClient.td
  lib/Target/X86/X86SchedSkylakeServer.td
  lib/Target/X86/X86Schedule.td
  lib/Target/X86/X86ScheduleAtom.td
  lib/Target/X86/X86ScheduleBdVer2.td
  lib/Target/X86/X86ScheduleBtVer2.td
  lib/Target/X86/X86ScheduleSLM.td
  lib/Target/X86/X86ScheduleZnver1.td
  test/tools/llvm-mca/X86/BtVer2/resources-avx1.s
  test/tools/llvm-mca/X86/BtVer2/resources-sse2.s

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