[PATCH] D67003: AMDGPU: Don't put constants in .text for Mesa

Connor Abbott via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Aug 30 06:26:24 PDT 2019


cwabbott created this revision.
cwabbott added reviewers: nhaehnle, arsenm.
Herald added subscribers: hiraditya, t-tye, tpr, dstuttard, yaxunl, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.

In Mesa we'd like to start creating constant globals. These should be in
the CONSTANT address space to let us use scalar loads where possible.
However, we also have to support pasting multiple text sections
together for RadeonSI, which means that we need to have constants in a
separate .rodata section so that they can get relocated after all the
pasted-together .text sections. We don't need this for radv, but it
shouldn't hurt either.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D67003

Files:
  llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
  llvm/test/CodeGen/AMDGPU/global-constant.ll


Index: llvm/test/CodeGen/AMDGPU/global-constant.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/global-constant.ll
+++ llvm/test/CodeGen/AMDGPU/global-constant.ll
@@ -1,5 +1,6 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOHSA %s
-; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA %s
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NONE %s
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=MESAHSA %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=MESAHSA -check-prefix=HSA %s
 
 @private1 = private unnamed_addr addrspace(4) constant [4 x float] [float 0.0, float 1.0, float 2.0, float 3.0]
 @private2 = private unnamed_addr addrspace(4) constant [4 x float] [float 4.0, float 5.0, float 6.0, float 7.0]
@@ -8,23 +9,23 @@
 ; GCN-LABEL: {{^}}private_test:
 ; GCN: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}}
 
-; Non-HSA OSes use fixup into .text section.
-; NOHSA: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1
-; NOHSA: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], 0
+; Non-HSA or Mesa OSes use fixup into .text section.
+; NONE: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1
+; NONE: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], 0
 
-; HSA OSes use relocations.
-; HSA: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1 at rel32@lo+4
-; HSA: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], private1 at rel32@hi+4
+; HSA and Mesa use relocations.
+; MESAHSA: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1 at rel32@lo+4
+; MESAHSA: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], private1 at rel32@hi+4
 
 ; GCN: s_getpc_b64 s{{\[}}[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]{{\]}}
 
-; Non-HSA OSes use fixup into .text section.
-; NOHSA: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2
-; NOHSA: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], 0
+; Non-HSA or Mesa OSes use fixup into .text section.
+; NONE: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2
+; NONE: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], 0
 
-; HSA OSes use relocations.
-; HSA: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2 at rel32@lo+4
-; HSA: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], private2 at rel32@hi+4
+; HSA and Mesa use relocations.
+; MESAHSA: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2 at rel32@lo+4
+; MESAHSA: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], private2 at rel32@hi+4
 
 define amdgpu_kernel void @private_test(i32 %index, float addrspace(1)* %out) {
   %ptr = getelementptr [4 x float], [4 x float] addrspace(4) * @private1, i32 0, i32 %index
Index: llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -514,7 +514,7 @@
 }
 
 bool shouldEmitConstantsToTextSection(const Triple &TT) {
-  return TT.getOS() != Triple::AMDHSA;
+  return TT.getOS() != Triple::AMDHSA && TT.getOS() != Triple::Mesa3D;
 }
 
 int getIntegerAttribute(const Function &F, StringRef Name, int Default) {


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