[llvm] r370378 - [AArch64][GlobalISel] Select @llvm.aarch64.ldxr.* intrinsics
Jessica Paquette via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 29 09:33:01 PDT 2019
Author: paquette
Date: Thu Aug 29 09:33:01 2019
New Revision: 370378
URL: http://llvm.org/viewvc/llvm-project?rev=370378&view=rev
Log:
[AArch64][GlobalISel] Select @llvm.aarch64.ldxr.* intrinsics
Same thing as D66897, but for ldxr.* instead. Add a GISelPredicateCode to the
ldxr_* definitions, which allows us to import them.
Add select-ldxr-intrin.mir, and update arm64-ldxr-stxr.ll.
Differential Revision: https://reviews.llvm.org/D66898
Added:
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstrAtomics.td
llvm/trunk/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrAtomics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrAtomics.td?rev=370378&r1=370377&r2=370378&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrAtomics.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrAtomics.td Thu Aug 29 09:33:01 2019
@@ -204,19 +204,27 @@ def : Pat<(relaxed_store<atomic_store_64
def ldxr_1 : PatFrag<(ops node:$ptr), (int_aarch64_ldxr node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
-}]>;
+}]> {
+ let GISelPredicateCode = [{ return isLoadStoreOfNumBytes(MI, 1); }];
+}
def ldxr_2 : PatFrag<(ops node:$ptr), (int_aarch64_ldxr node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
-}]>;
+}]> {
+ let GISelPredicateCode = [{ return isLoadStoreOfNumBytes(MI, 2); }];
+}
def ldxr_4 : PatFrag<(ops node:$ptr), (int_aarch64_ldxr node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
-}]>;
+}]> {
+ let GISelPredicateCode = [{ return isLoadStoreOfNumBytes(MI, 4); }];
+}
def ldxr_8 : PatFrag<(ops node:$ptr), (int_aarch64_ldxr node:$ptr), [{
return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
-}]>;
+}]> {
+ let GISelPredicateCode = [{ return isLoadStoreOfNumBytes(MI, 8); }];
+}
def : Pat<(ldxr_1 GPR64sp:$addr),
(SUBREG_TO_REG (i64 0), (LDXRB GPR64sp:$addr), sub_32)>;
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir?rev=370378&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir Thu Aug 29 09:33:01 2019
@@ -0,0 +1,95 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+ define void @test_load_i8(i8* %addr) { ret void }
+ define void @test_load_i16(i16* %addr) { ret void }
+ define void @test_load_i32(i32* %addr) { ret void }
+ define void @test_load_i64(i64* %addr) { ret void }
+...
+---
+name: test_load_i8
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_load_i8
+ ; CHECK: liveins: $x0
+ ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK: [[LDXRB:%[0-9]+]]:gpr32 = LDXRB [[COPY]] :: (volatile load 1 from %ir.addr)
+ ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDXRB]], %subreg.sub_32
+ ; CHECK: $x1 = COPY [[SUBREG_TO_REG]]
+ ; CHECK: RET_ReallyLR implicit $x1
+ %0:gpr(p0) = COPY $x0
+ %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load 1 from %ir.addr)
+ $x1 = COPY %1(s64)
+ RET_ReallyLR implicit $x1
+
+...
+---
+name: test_load_i16
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_load_i16
+ ; CHECK: liveins: $x0
+ ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK: [[LDXRH:%[0-9]+]]:gpr32 = LDXRH [[COPY]] :: (volatile load 2 from %ir.addr)
+ ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDXRH]], %subreg.sub_32
+ ; CHECK: $x1 = COPY [[SUBREG_TO_REG]]
+ ; CHECK: RET_ReallyLR implicit $x1
+ %0:gpr(p0) = COPY $x0
+ %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load 2 from %ir.addr)
+ $x1 = COPY %1(s64)
+ RET_ReallyLR implicit $x1
+
+...
+---
+name: test_load_i32
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_load_i32
+ ; CHECK: liveins: $x0
+ ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK: [[LDXRW:%[0-9]+]]:gpr32 = LDXRW [[COPY]] :: (volatile load 4 from %ir.addr)
+ ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDXRW]], %subreg.sub_32
+ ; CHECK: $x1 = COPY [[SUBREG_TO_REG]]
+ ; CHECK: RET_ReallyLR implicit $x1
+ %0:gpr(p0) = COPY $x0
+ %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load 4 from %ir.addr)
+ $x1 = COPY %1(s64)
+ RET_ReallyLR implicit $x1
+
+
+...
+---
+name: test_load_i64
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_load_i64
+ ; CHECK: liveins: $x0
+ ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+ ; CHECK: [[LDXRX:%[0-9]+]]:gpr64 = LDXRX [[COPY]] :: (volatile load 8 from %ir.addr)
+ ; CHECK: $x1 = COPY [[LDXRX]]
+ ; CHECK: RET_ReallyLR implicit $x1
+ %0:gpr(p0) = COPY $x0
+ %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldxr), %0(p0) :: (volatile load 8 from %ir.addr)
+ $x1 = COPY %1(s64)
+ RET_ReallyLR implicit $x1
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-ldxr-stxr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-ldxr-stxr.ll?rev=370378&r1=370377&r2=370378&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-ldxr-stxr.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-ldxr-stxr.ll Thu Aug 29 09:33:01 2019
@@ -33,6 +33,7 @@ declare i32 @llvm.aarch64.stxp(i64, i64,
@var = global i64 0, align 8
+; FALLBACK-NOT: remark:{{.*}}test_load_i8
define void @test_load_i8(i8* %addr) {
; CHECK-LABEL: test_load_i8:
; CHECK: ldxrb w[[LOADVAL:[0-9]+]], [x0]
@@ -40,6 +41,12 @@ define void @test_load_i8(i8* %addr) {
; CHECK-NOT: and
; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
+; FIXME: GlobalISel doesn't fold ands/adds into load/store addressing modes
+; right now/ So, we won't get the :lo12:var.
+; GISEL-LABEL: test_load_i8:
+; GISEL: ldxrb w[[LOADVAL:[0-9]+]], [x0]
+; GISEL-NOT: uxtb
+; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}]
%val = call i64 @llvm.aarch64.ldxr.p0i8(i8* %addr)
%shortval = trunc i64 %val to i8
%extval = zext i8 %shortval to i64
@@ -47,6 +54,7 @@ define void @test_load_i8(i8* %addr) {
ret void
}
+; FALLBACK-NOT: remark:{{.*}}test_load_i16
define void @test_load_i16(i16* %addr) {
; CHECK-LABEL: test_load_i16:
; CHECK: ldxrh w[[LOADVAL:[0-9]+]], [x0]
@@ -54,6 +62,10 @@ define void @test_load_i16(i16* %addr) {
; CHECK-NOT: and
; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
+; GISEL-LABEL: test_load_i16:
+; GISEL: ldxrh w[[LOADVAL:[0-9]+]], [x0]
+; GISEL-NOT: uxtb
+; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}]
%val = call i64 @llvm.aarch64.ldxr.p0i16(i16* %addr)
%shortval = trunc i64 %val to i16
%extval = zext i16 %shortval to i64
@@ -61,6 +73,7 @@ define void @test_load_i16(i16* %addr) {
ret void
}
+; FALLBACK-NOT: remark:{{.*}}test_load_i32
define void @test_load_i32(i32* %addr) {
; CHECK-LABEL: test_load_i32:
; CHECK: ldxr w[[LOADVAL:[0-9]+]], [x0]
@@ -68,6 +81,10 @@ define void @test_load_i32(i32* %addr) {
; CHECK-NOT: and
; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
+; GISEL-LABEL: test_load_i32:
+; GISEL: ldxr w[[LOADVAL:[0-9]+]], [x0]
+; GISEL-NOT: uxtb
+; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}]
%val = call i64 @llvm.aarch64.ldxr.p0i32(i32* %addr)
%shortval = trunc i64 %val to i32
%extval = zext i32 %shortval to i64
@@ -75,11 +92,16 @@ define void @test_load_i32(i32* %addr) {
ret void
}
+; FALLBACK-NOT: remark:{{.*}}test_load_i64
define void @test_load_i64(i64* %addr) {
; CHECK-LABEL: test_load_i64:
; CHECK: ldxr x[[LOADVAL:[0-9]+]], [x0]
; CHECK: str x[[LOADVAL]], [{{x[0-9]+}}, :lo12:var]
+; GISEL-LABEL: test_load_i64:
+; GISEL: ldxr x[[LOADVAL:[0-9]+]], [x0]
+; GISEL-NOT: uxtb
+; GISEL: str x[[LOADVAL]], [{{x[0-9]+}}]
%val = call i64 @llvm.aarch64.ldxr.p0i64(i64* %addr)
store i64 %val, i64* @var, align 8
ret void
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