[llvm] r370203 - [X86] Add test for rotate combining when add X, X is used instead of shl X, 1. NFC

[Amaury Sechet via llvm-commits]

Author: deadalnix
Date: Wed Aug 28 06:52:32 2019
New Revision: 370203

URL: http://llvm.org/viewvc/llvm-project?rev=370203&view=rev
Log:
[X86] Add test for rotate combining when add X, X is used instead of shl X, 1. NFC

Modified:
    llvm/trunk/test/CodeGen/X86/rotate-extract-vector.ll
    llvm/trunk/test/CodeGen/X86/rotate-extract.ll

Modified: llvm/trunk/test/CodeGen/X86/rotate-extract-vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/rotate-extract-vector.ll?rev=370203&r1=370202&r2=370203&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/rotate-extract-vector.ll (original)
+++ llvm/trunk/test/CodeGen/X86/rotate-extract-vector.ll Wed Aug 28 06:52:32 2019
@@ -280,3 +280,17 @@ define <2 x i64> @no_extract_udiv(<2 x i
   %out = or <2 x i64> %lhs_shift, %rhs_div
   ret <2 x i64> %out
 }
+
+; DAGCombiner transforms shl X, 1 into add X, X.
+define <4 x i32> @extract_add_1(<4 x i32> %i) nounwind {
+; CHECK-LABEL: extract_add_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpaddd %xmm0, %xmm0, %xmm1
+; CHECK-NEXT:    vpsrld $31, %xmm0, %xmm0
+; CHECK-NEXT:    vpor %xmm0, %xmm1, %xmm0
+; CHECK-NEXT:    ret{{[l|q]}}
+  %ii = add <4 x i32> %i, %i
+  %rhs = lshr <4 x i32> %i, <i32 31, i32 31, i32 31, i32 31>
+  %out = or <4 x i32> %ii, %rhs
+  ret <4 x i32> %out
+}

Modified: llvm/trunk/test/CodeGen/X86/rotate-extract.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/rotate-extract.ll?rev=370203&r1=370202&r2=370203&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/rotate-extract.ll (original)
+++ llvm/trunk/test/CodeGen/X86/rotate-extract.ll Wed Aug 28 06:52:32 2019
@@ -265,3 +265,26 @@ define i8 @no_extract_udiv(i8 %i) nounwi
   %out = or i8 %lhs_shift, %rhs_div
   ret i8 %out
 }
+
+; DAGCombiner transforms shl X, 1 into add X, X.
+define i32 @extract_add_1(i32 %i) nounwind {
+; X86-LABEL: extract_add_1:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT:    leal (%ecx,%ecx), %eax
+; X86-NEXT:    shrl $31, %ecx
+; X86-NEXT:    orl %ecx, %eax
+; X86-NEXT:    retl
+;
+; X64-LABEL: extract_add_1:
+; X64:       # %bb.0:
+; X64-NEXT:    # kill: def $edi killed $edi def $rdi
+; X64-NEXT:    leal (%rdi,%rdi), %eax
+; X64-NEXT:    shrl $31, %edi
+; X64-NEXT:    orl %edi, %eax
+; X64-NEXT:    retq
+  %ii = add i32 %i, %i
+  %rhs = lshr i32 %i, 31
+  %out = or i32 %ii, %rhs
+  ret i32 %out
+}