[llvm] r370089 - AMDGPU: Add amdgpu-32bit-address-high-bits to MIR serialization
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 27 11:18:38 PDT 2019
Author: arsenm
Date: Tue Aug 27 11:18:38 2019
New Revision: 370089
URL: http://llvm.org/viewvc/llvm-project?rev=370089&view=rev
Log:
AMDGPU: Add amdgpu-32bit-address-high-bits to MIR serialization
Modified:
llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h
llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
Modified: llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp?rev=370089&r1=370088&r2=370089&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp Tue Aug 27 11:18:38 2019
@@ -486,6 +486,7 @@ yaml::SIMachineFunctionInfo::SIMachineFu
NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
MemoryBound(MFI.isMemoryBound()),
WaveLimiter(MFI.needsWaveLimiter()),
+ HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
ScratchWaveOffsetReg(regToString(MFI.getScratchWaveOffsetReg(), TRI)),
FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
@@ -502,6 +503,7 @@ bool SIMachineFunctionInfo::initializeBa
ExplicitKernArgSize = YamlMFI.ExplicitKernArgSize;
MaxKernArgAlign = YamlMFI.MaxKernArgAlign;
LDSSize = YamlMFI.LDSSize;
+ HighBitsOf32BitAddress = YamlMFI.HighBitsOf32BitAddress;
IsEntryFunction = YamlMFI.IsEntryFunction;
NoSignedZerosFPMath = YamlMFI.NoSignedZerosFPMath;
MemoryBound = YamlMFI.MemoryBound;
Modified: llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h?rev=370089&r1=370088&r2=370089&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h Tue Aug 27 11:18:38 2019
@@ -265,6 +265,7 @@ struct SIMachineFunctionInfo final : pub
bool NoSignedZerosFPMath = false;
bool MemoryBound = false;
bool WaveLimiter = false;
+ uint32_t HighBitsOf32BitAddress = 0;
StringValue ScratchRSrcReg = "$private_rsrc_reg";
StringValue ScratchWaveOffsetReg = "$scratch_wave_offset_reg";
@@ -302,6 +303,8 @@ template <> struct MappingTraits<SIMachi
StringValue("$sp_reg"));
YamlIO.mapOptional("argumentInfo", MFI.ArgInfo);
YamlIO.mapOptional("mode", MFI.Mode, SIMode());
+ YamlIO.mapOptional("highBitsOf32BitAddress",
+ MFI.HighBitsOf32BitAddress, 0u);
}
};
@@ -670,7 +673,7 @@ public:
return GITPtrHigh;
}
- unsigned get32BitAddressHighBits() const {
+ uint32_t get32BitAddressHighBits() const {
return HighBitsOf32BitAddress;
}
Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir?rev=370089&r1=370088&r2=370089&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir Tue Aug 27 11:18:38 2019
@@ -25,6 +25,7 @@
# FULL-NEXT: mode:
# FULL-NEXT: ieee: true
# FULL-NEXT: dx10-clamp: true
+# FULL-NEXT: highBitsOf32BitAddress: 0
# FULL-NEXT: body:
# SIMPLE: machineFunctionInfo:
@@ -91,6 +92,7 @@ body: |
# FULL-NEXT: mode:
# FULL-NEXT: ieee: true
# FULL-NEXT: dx10-clamp: true
+# FULL-NEXT: highBitsOf32BitAddress: 0
# FULL-NEXT: body:
# SIMPLE: machineFunctionInfo:
@@ -126,6 +128,7 @@ body: |
# FULL-NEXT: mode:
# FULL-NEXT: ieee: true
# FULL-NEXT: dx10-clamp: true
+# FULL-NEXT: highBitsOf32BitAddress: 0
# FULL-NEXT: body:
# SIMPLE: machineFunctionInfo:
@@ -162,6 +165,7 @@ body: |
# FULL-NEXT: mode:
# FULL-NEXT: ieee: true
# FULL-NEXT: dx10-clamp: true
+# FULL-NEXT: highBitsOf32BitAddress: 0
# FULL-NEXT: body:
# SIMPLE: machineFunctionInfo:
Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info.ll?rev=370089&r1=370088&r2=370089&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info.ll (original)
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/machine-function-info.ll Tue Aug 27 11:18:38 2019
@@ -28,6 +28,7 @@
; CHECK-NEXT: mode:
; CHECK-NEXT: ieee: true
; CHECK-NEXT: dx10-clamp: true
+; CHECK-NEXT: highBitsOf32BitAddress: 0
; CHECK-NEXT: body:
define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) {
%gep = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %arg0
@@ -54,6 +55,7 @@ define amdgpu_kernel void @kernel(i32 %a
; CHECK-NEXT: mode:
; CHECK-NEXT: ieee: false
; CHECK-NEXT: dx10-clamp: true
+; CHECK-NEXT: highBitsOf32BitAddress: 0
; CHECK-NEXT: body:
define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) {
ret void
@@ -78,6 +80,7 @@ define amdgpu_ps void @ps_shader(i32 %ar
; CHECK-NEXT: mode:
; CHECK-NEXT: ieee: true
; CHECK-NEXT: dx10-clamp: true
+; CHECK-NEXT: highBitsOf32BitAddress: 0
; CHECK-NEXT: body:
define void @function() {
ret void
@@ -102,6 +105,7 @@ define void @function() {
; CHECK-NEXT: mode:
; CHECK-NEXT: ieee: true
; CHECK-NEXT: dx10-clamp: true
+; CHECK-NEXT: highBitsOf32BitAddress: 0
; CHECK-NEXT: body:
define void @function_nsz() #0 {
ret void
@@ -131,8 +135,15 @@ define void @function_ieee_off_dx10_clam
ret void
}
-attributes #0 = { "no-signed-zeros-fp-math" = "true" }
+; CHECK-LABEL: {{^}}name: high_address_bits
+; CHECK: machineFunctionInfo:
+; CHECK: highBitsOf32BitAddress: 4294934528
+define amdgpu_ps void @high_address_bits() #4 {
+ ret void
+}
+attributes #0 = { "no-signed-zeros-fp-math" = "true" }
attributes #1 = { "amdgpu-dx10-clamp" = "false" }
attributes #2 = { "amdgpu-ieee" = "false" }
attributes #3 = { "amdgpu-dx10-clamp" = "false" "amdgpu-ieee" = "false" }
+attributes #4 = { "amdgpu-32bit-address-high-bits"="0xffff8000" }
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