[PATCH] D66805: [MIPS] For vectors, select `add %x, -1` as `sub %x, 1`

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

Thank you for taking a look.

In D66805#1647228 <https://reviews.llvm.org/D66805#1647228>, @Petar.Avramovic wrote:

> This patch targets very specific values(1,-1) but there are more. The trick for D62341 <https://reviews.llvm.org/D62341> is that msa vector add/sub imm accept 5 bit unsigned imm, so it is ok to switch from add imm to sub imm (also sub to add) if it changes imm form negative to positive.


Yeah, i have found that in ISA manual since posting the patch.

> I think it is cleanest to have some hook and ask target if it would like to transform sub into add (add to sub) with imm.

I understand where this is coming from but no, that will not be ok.
The whole point of D62341 <https://reviews.llvm.org/D62341> is that we **really** don't want `sub %x, C` in DAGCombine,
so while we could hide it behind target hook, that defies the whole purpose.
So this needs to be undone per-target in `*ISelDAGToDAG.cpp`.


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