[llvm] r370036 - AArch64: avoid creating cycle in DAG for post-increment NEON ops.

[Hans Wennborg via llvm-commits]

Merged to release_90 in r370063.

On Tue, Aug 27, 2019 at 12:19 PM Tim Northover via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
>
> Author: tnorthover
> Date: Tue Aug 27 03:21:11 2019
> New Revision: 370036
>
> URL: http://llvm.org/viewvc/llvm-project?rev=370036&view=rev
> Log:
> AArch64: avoid creating cycle in DAG for post-increment NEON ops.
>
> Inserting a value into Visited has the effect of terminating a search for
> predecessors if that node is seen. This is legitimate for the base address, and
> acts as a slight performance optimization, but the vector-building node can be
> paert of a legitimate cycle so we shouldn't stop searching there.
>
> PR43056.
>
> Modified:
>     llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
>     llvm/trunk/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=370036&r1=370035&r2=370036&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Tue Aug 27 03:21:11 2019
> @@ -10694,7 +10694,7 @@ static SDValue performPostLD1Combine(SDN
>      // are predecessors to each other or the Vector.
>      SmallPtrSet<const SDNode *, 32> Visited;
>      SmallVector<const SDNode *, 16> Worklist;
> -    Visited.insert(N);
> +    Visited.insert(Addr.getNode());
>      Worklist.push_back(User);
>      Worklist.push_back(LD);
>      Worklist.push_back(Vector.getNode());
>
> Modified: llvm/trunk/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll?rev=370036&r1=370035&r2=370036&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll (original)
> +++ llvm/trunk/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll Tue Aug 27 03:21:11 2019
> @@ -6319,3 +6319,22 @@ define void  @test_ld1lane_build_i8(i8*
>    store <8 x i8> %sub, <8 x i8>* %p
>    ret void
>  }
> +
> +define <4 x i32> @test_inc_cycle(<4 x i32> %vec, i32* %in) {
> +; CHECK-LABEL: test_inc_cycle:
> +; CHECK: ld1.s { v0 }[0], [x0]{{$}}
> +
> +  %elt = load i32, i32* %in
> +  %newvec = insertelement <4 x i32> %vec, i32 %elt, i32 0
> +
> +  ; %inc cannot be %elt directly because we check that the load is only
> +  ; used by the insert before trying to form post-inc.
> +  %inc.vec = bitcast <4 x i32> %newvec to <2 x i64>
> +  %inc = extractelement <2 x i64> %inc.vec, i32 0
> +  %newaddr = getelementptr i32, i32* %in, i64 %inc
> +  store i32* %newaddr, i32** @var
> +
> +  ret <4 x i32> %newvec
> +}
> +
> + at var = global i32* null
>
>
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