[PATCH] D66534: [ARM] MVE Masked loads and stores

[Sam Parker via Phabricator via llvm-commits]

samparker added a comment.

Sorry if I've missed it or misunderstood the tests, but are we testing the cases where we need to generated a vsel?



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Comment at: llvm/lib/Target/ARM/ARMInstrMVE.td:4991
+  // Masked stores
+  def : MVE_vector_maskedstore_typed<v16i8, MVE_VSTRBU8, maskedstore, 0>;
+  def : MVE_vector_maskedstore_typed<v8i16, MVE_VSTRHU16, alignedmaskedstore16, 1>;
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Aren't the aligned patterns the same for both LE and BE? If so, we can refactor this.


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https://reviews.llvm.org/D66534