[PATCH] D66687: [x86] try to form more bt/test + set out of shift+mask patterns

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:5225
+  //       compare in the source type.
+  unsigned ShiftAmt = Srl.getConstantOperandVal(1);
+  unsigned VTBits = VT.getSizeInBits();
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Is it possible for the shift to be on a type larger than 64 bits and have an absurdly out of bounds shift amount that we haven't collapsed to undef yet such that this asserts? Or for that matter a 64 bit shift amount that's larger than 0xffffffff and not been folded yet. Since we truncate a uint64_t to unsigned here.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66687/new/

https://reviews.llvm.org/D66687