[llvm] r369803 - Do a sweep of symbol internalization. NFC.
Benjamin Kramer via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 23 12:59:24 PDT 2019
Author: d0k
Date: Fri Aug 23 12:59:23 2019
New Revision: 369803
URL: http://llvm.org/viewvc/llvm-project?rev=369803&view=rev
Log:
Do a sweep of symbol internalization. NFC.
Modified:
llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/trunk/lib/CodeGen/TargetPassConfig.cpp
llvm/trunk/lib/IR/DIBuilder.cpp
llvm/trunk/lib/LTO/SummaryBasedOptimizations.cpp
llvm/trunk/lib/MC/MCDwarf.cpp
llvm/trunk/lib/Remarks/RemarkParser.cpp
llvm/trunk/lib/Support/FileCheck.cpp
llvm/trunk/lib/Target/AArch64/AArch64SpeculationHardening.cpp
llvm/trunk/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/trunk/lib/Target/X86/X86IndirectBranchTracking.cpp
llvm/trunk/lib/Transforms/Scalar/LoopFuse.cpp
Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=369803&r1=369802&r2=369803&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original)
+++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Fri Aug 23 12:59:23 2019
@@ -86,7 +86,7 @@ static cl::opt<unsigned>
cl::desc("Number of metadatas above which we emit an index "
"to enable lazy-loading"));
-cl::opt<bool> WriteRelBFToSummary(
+static cl::opt<bool> WriteRelBFToSummary(
"write-relbf-to-summary", cl::Hidden, cl::init(false),
cl::desc("Write relative block frequency to function summary "));
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=369803&r1=369802&r2=369803&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Fri Aug 23 12:59:23 2019
@@ -5327,8 +5327,9 @@ static SDValue ExpandPowI(const SDLoc &D
// getUnderlyingArgRegs - Find underlying registers used for a truncated,
// bitcasted, or split argument. Returns a list of <Register, size in bits>
-void getUnderlyingArgRegs(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
- const SDValue &N) {
+static void
+getUnderlyingArgRegs(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
+ const SDValue &N) {
switch (N.getOpcode()) {
case ISD::CopyFromReg: {
SDValue Op = N.getOperand(1);
Modified: llvm/trunk/lib/CodeGen/TargetPassConfig.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetPassConfig.cpp?rev=369803&r1=369802&r2=369803&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetPassConfig.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetPassConfig.cpp Fri Aug 23 12:59:23 2019
@@ -49,9 +49,10 @@
using namespace llvm;
-cl::opt<bool> EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
- cl::desc("Enable interprocedural register allocation "
- "to reduce load/store at procedure calls."));
+static cl::opt<bool>
+ EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
+ cl::desc("Enable interprocedural register allocation "
+ "to reduce load/store at procedure calls."));
static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
cl::desc("Disable Post Regalloc Scheduler"));
static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
@@ -152,8 +153,10 @@ static cl::opt<GlobalISelAbortMode> Enab
// substitutePass(&PostRASchedulerID, &PostMachineSchedulerID).
// Targets can return true in targetSchedulesPostRAScheduling() and
// insert a PostRA scheduling pass wherever it wants.
-cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
- cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
+static cl::opt<bool> MISchedPostRA(
+ "misched-postra", cl::Hidden,
+ cl::desc(
+ "Run MachineScheduler post regalloc (independent of preRA sched)"));
// Experimental option to run live interval analysis early.
static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
@@ -175,10 +178,10 @@ static cl::opt<CFLAAType> UseCFLAA(
/// Option names for limiting the codegen pipeline.
/// Those are used in error reporting and we didn't want
/// to duplicate their names all over the place.
-const char *StartAfterOptName = "start-after";
-const char *StartBeforeOptName = "start-before";
-const char *StopAfterOptName = "stop-after";
-const char *StopBeforeOptName = "stop-before";
+static const char *StartAfterOptName = "start-after";
+static const char *StartBeforeOptName = "start-before";
+static const char *StopAfterOptName = "stop-after";
+static const char *StopBeforeOptName = "stop-before";
static cl::opt<std::string>
StartAfterOpt(StringRef(StartAfterOptName),
Modified: llvm/trunk/lib/IR/DIBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/DIBuilder.cpp?rev=369803&r1=369802&r2=369803&view=diff
==============================================================================
--- llvm/trunk/lib/IR/DIBuilder.cpp (original)
+++ llvm/trunk/lib/IR/DIBuilder.cpp Fri Aug 23 12:59:23 2019
@@ -25,7 +25,7 @@
using namespace llvm;
using namespace llvm::dwarf;
-cl::opt<bool>
+static cl::opt<bool>
UseDbgAddr("use-dbg-addr",
llvm::cl::desc("Use llvm.dbg.addr for all local variables"),
cl::init(false), cl::Hidden);
Modified: llvm/trunk/lib/LTO/SummaryBasedOptimizations.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/LTO/SummaryBasedOptimizations.cpp?rev=369803&r1=369802&r2=369803&view=diff
==============================================================================
--- llvm/trunk/lib/LTO/SummaryBasedOptimizations.cpp (original)
+++ llvm/trunk/lib/LTO/SummaryBasedOptimizations.cpp Fri Aug 23 12:59:23 2019
@@ -18,7 +18,7 @@
using namespace llvm;
-cl::opt<bool> ThinLTOSynthesizeEntryCounts(
+static cl::opt<bool> ThinLTOSynthesizeEntryCounts(
"thinlto-synthesize-entry-counts", cl::init(false), cl::Hidden,
cl::desc("Synthesize entry counts based on the summary"));
Modified: llvm/trunk/lib/MC/MCDwarf.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=369803&r1=369802&r2=369803&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDwarf.cpp (original)
+++ llvm/trunk/lib/MC/MCDwarf.cpp Fri Aug 23 12:59:23 2019
@@ -544,8 +544,8 @@ Expected<unsigned> MCDwarfLineTable::try
FileNumber);
}
-bool isRootFile(const MCDwarfFile &RootFile, StringRef &Directory,
- StringRef &FileName, Optional<MD5::MD5Result> Checksum) {
+static bool isRootFile(const MCDwarfFile &RootFile, StringRef &Directory,
+ StringRef &FileName, Optional<MD5::MD5Result> Checksum) {
if (RootFile.Name.empty() || RootFile.Name != FileName.data())
return false;
return RootFile.Checksum == Checksum;
Modified: llvm/trunk/lib/Remarks/RemarkParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Remarks/RemarkParser.cpp?rev=369803&r1=369802&r2=369803&view=diff
==============================================================================
--- llvm/trunk/lib/Remarks/RemarkParser.cpp (original)
+++ llvm/trunk/lib/Remarks/RemarkParser.cpp Fri Aug 23 12:59:23 2019
@@ -105,6 +105,7 @@ llvm::remarks::createRemarkParserFromMet
llvm_unreachable("unhandled ParseFormat");
}
+namespace {
// Wrapper that holds the state needed to interact with the C API.
struct CParser {
std::unique_ptr<RemarkParser> TheParser;
@@ -120,6 +121,7 @@ struct CParser {
bool hasError() const { return Err.hasValue(); }
const char *getMessage() const { return Err ? Err->c_str() : nullptr; };
};
+} // namespace
// Create wrappers for C Binding types (see CBindingWrapping.h).
DEFINE_SIMPLE_CONVERSION_FUNCTIONS(CParser, LLVMRemarkParserRef)
Modified: llvm/trunk/lib/Support/FileCheck.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/FileCheck.cpp?rev=369803&r1=369802&r2=369803&view=diff
==============================================================================
--- llvm/trunk/lib/Support/FileCheck.cpp (original)
+++ llvm/trunk/lib/Support/FileCheck.cpp Fri Aug 23 12:59:23 2019
@@ -125,7 +125,7 @@ FileCheckPattern::parseVariable(StringRe
// StringRef holding all characters considered as horizontal whitespaces by
// FileCheck input canonicalization.
-StringRef SpaceChars = " \t";
+constexpr StringLiteral SpaceChars = " \t";
// Parsing helper function that strips the first character in S and returns it.
static char popFront(StringRef &S) {
Modified: llvm/trunk/lib/Target/AArch64/AArch64SpeculationHardening.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SpeculationHardening.cpp?rev=369803&r1=369802&r2=369803&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SpeculationHardening.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SpeculationHardening.cpp Fri Aug 23 12:59:23 2019
@@ -115,9 +115,9 @@ using namespace llvm;
#define AARCH64_SPECULATION_HARDENING_NAME "AArch64 speculation hardening pass"
-cl::opt<bool> HardenLoads("aarch64-slh-loads", cl::Hidden,
- cl::desc("Sanitize loads from memory."),
- cl::init(true));
+static cl::opt<bool> HardenLoads("aarch64-slh-loads", cl::Hidden,
+ cl::desc("Sanitize loads from memory."),
+ cl::init(true));
namespace {
Modified: llvm/trunk/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp?rev=369803&r1=369802&r2=369803&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp Fri Aug 23 12:59:23 2019
@@ -93,9 +93,9 @@ static cl::opt<bool> OnlyNonNestedMemmov
cl::Hidden, cl::init(true),
cl::desc("Only enable generating memmove in non-nested loops"));
-cl::opt<bool> HexagonVolatileMemcpy("disable-hexagon-volatile-memcpy",
- cl::Hidden, cl::init(false),
- cl::desc("Enable Hexagon-specific memcpy for volatile destination."));
+static cl::opt<bool> HexagonVolatileMemcpy(
+ "disable-hexagon-volatile-memcpy", cl::Hidden, cl::init(false),
+ cl::desc("Enable Hexagon-specific memcpy for volatile destination."));
static cl::opt<unsigned> SimplifyLimit("hlir-simplify-limit", cl::init(10000),
cl::Hidden, cl::desc("Maximum number of simplification steps in HLIR"));
Modified: llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp?rev=369803&r1=369802&r2=369803&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp Fri Aug 23 12:59:23 2019
@@ -57,9 +57,9 @@ static cl::opt<bool> DisablePacketizer("
cl::ZeroOrMore, cl::init(false),
cl::desc("Disable Hexagon packetizer pass"));
-cl::opt<bool> Slot1Store("slot1-store-slot0-load", cl::Hidden,
- cl::ZeroOrMore, cl::init(true),
- cl::desc("Allow slot1 store and slot0 load"));
+static cl::opt<bool> Slot1Store("slot1-store-slot0-load", cl::Hidden,
+ cl::ZeroOrMore, cl::init(true),
+ cl::desc("Allow slot1 store and slot0 load"));
static cl::opt<bool> PacketizeVolatiles("hexagon-packetize-volatiles",
cl::ZeroOrMore, cl::Hidden, cl::init(true),
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp?rev=369803&r1=369802&r2=369803&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp Fri Aug 23 12:59:23 2019
@@ -72,7 +72,6 @@ cl::opt<bool> MV65("mv65", cl::Hidden, c
cl::init(false));
cl::opt<bool> MV66("mv66", cl::Hidden, cl::desc("Build for Hexagon V66"),
cl::init(false));
-} // namespace
cl::opt<Hexagon::ArchEnum>
EnableHVX("mhvx",
@@ -86,6 +85,7 @@ cl::opt<Hexagon::ArchEnum>
clEnumValN(Hexagon::ArchEnum::Generic, "", "")),
// Sentinel for flag not present.
cl::init(Hexagon::ArchEnum::NoArch), cl::ValueOptional);
+} // namespace
static cl::opt<bool>
DisableHVX("mno-hvx", cl::Hidden,
Modified: llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp?rev=369803&r1=369802&r2=369803&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp Fri Aug 23 12:59:23 2019
@@ -744,7 +744,7 @@ public:
// Return the matching FPR64 register for the given FPR32.
// FIXME: Ideally this function could be removed in favour of using
// information from TableGen.
-Register convertFPR32ToFPR64(Register Reg) {
+static Register convertFPR32ToFPR64(Register Reg) {
switch (Reg) {
default:
llvm_unreachable("Not a recognised FPR32 register");
Modified: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp?rev=369803&r1=369802&r2=369803&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp Fri Aug 23 12:59:23 2019
@@ -1078,8 +1078,8 @@ unsigned RISCVTargetLowering::ComputeNum
return 1;
}
-MachineBasicBlock *emitReadCycleWidePseudo(MachineInstr &MI,
- MachineBasicBlock *BB) {
+static MachineBasicBlock *emitReadCycleWidePseudo(MachineInstr &MI,
+ MachineBasicBlock *BB) {
assert(MI.getOpcode() == RISCV::ReadCycleWide && "Unexpected instruction");
// To read the 64-bit cycle CSR on a 32-bit target, we read the two halves.
Modified: llvm/trunk/lib/Target/X86/X86IndirectBranchTracking.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86IndirectBranchTracking.cpp?rev=369803&r1=369802&r2=369803&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86IndirectBranchTracking.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86IndirectBranchTracking.cpp Fri Aug 23 12:59:23 2019
@@ -84,7 +84,7 @@ bool X86IndirectBranchTrackingPass::addE
return false;
}
-bool IsCallReturnTwice(llvm::MachineOperand &MOp) {
+static bool IsCallReturnTwice(llvm::MachineOperand &MOp) {
if (!MOp.isGlobal())
return false;
auto *CalleeFn = dyn_cast<Function>(MOp.getGlobal());
Modified: llvm/trunk/lib/Transforms/Scalar/LoopFuse.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopFuse.cpp?rev=369803&r1=369802&r2=369803&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopFuse.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopFuse.cpp Fri Aug 23 12:59:23 2019
@@ -110,6 +110,7 @@ static cl::opt<bool>
cl::Hidden, cl::init(false), cl::ZeroOrMore);
#endif
+namespace {
/// This class is used to represent a candidate for loop fusion. When it is
/// constructed, it checks the conditions for loop fusion to ensure that it
/// represents a valid candidate. It caches several parts of a loop that are
@@ -338,7 +339,6 @@ struct FusionCandidateCompare {
}
};
-namespace {
using LoopVector = SmallVector<Loop *, 4>;
// Set of Control Flow Equivalent (CFE) Fusion Candidates, sorted in dominance
@@ -353,7 +353,6 @@ using LoopVector = SmallVector<Loop *, 4
// keeps the FusionCandidateSet sorted will also simplify the implementation.
using FusionCandidateSet = std::set<FusionCandidate, FusionCandidateCompare>;
using FusionCandidateCollection = SmallVector<FusionCandidateSet, 4>;
-} // namespace
inline llvm::raw_ostream &operator<<(llvm::raw_ostream &OS,
const FusionCandidateSet &CandSet) {
@@ -1211,6 +1210,7 @@ struct LoopFuseLegacy : public FunctionP
return LF.fuseLoops(F);
}
};
+} // namespace
PreservedAnalyses LoopFusePass::run(Function &F, FunctionAnalysisManager &AM) {
auto &LI = AM.getResult<LoopAnalysis>(F);
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