[llvm] r369787 - [AMDGPU] Automatically generate various tests. NFC
Amaury Sechet via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 23 10:58:50 PDT 2019
Author: deadalnix
Date: Fri Aug 23 10:58:49 2019
New Revision: 369787
URL: http://llvm.org/viewvc/llvm-project?rev=369787&view=rev
Log:
[AMDGPU] Automatically generate various tests. NFC
Modified:
llvm/trunk/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
llvm/trunk/test/CodeGen/AMDGPU/copy-illegal-type.ll
llvm/trunk/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
llvm/trunk/test/CodeGen/AMDGPU/load-lo16.ll
llvm/trunk/test/CodeGen/AMDGPU/memory_clause.ll
llvm/trunk/test/CodeGen/AMDGPU/r600-export-fix.ll
Modified: llvm/trunk/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/chain-hi-to-lo.ll?rev=369787&r1=369786&r2=369787&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/chain-hi-to-lo.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/chain-hi-to-lo.ll Fri Aug 23 10:58:49 2019
@@ -1,10 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX900 %s
-; GCN-LABEL: {{^}}chain_hi_to_lo_private:
-; GCN: buffer_load_ushort [[DST:v[0-9]+]], off, [[RSRC:s\[[0-9]+:[0-9]+\]]], [[SOFF:s[0-9]+]] offset:2
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: buffer_load_short_d16_hi [[DST]], off, [[RSRC]], [[SOFF]]
define <2 x half> @chain_hi_to_lo_private() {
+; GCN-LABEL: chain_hi_to_lo_private:
+; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: buffer_load_ushort v0, off, s[0:3], s33 offset:2
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: buffer_load_short_d16_hi v0, off, s[0:3], s33
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
bb:
%gep_lo = getelementptr inbounds half, half addrspace(5)* null, i64 1
%load_lo = load half, half addrspace(5)* %gep_lo
@@ -17,11 +22,15 @@ bb:
ret <2 x half> %result
}
-; GCN-LABEL: {{^}}chain_hi_to_lo_private_different_bases:
-; GCN: buffer_load_ushort [[DST:v[0-9]+]], v{{[0-9]+}}, [[RSRC:s\[[0-9]+:[0-9]+\]]], [[SOFF:s[0-9]+]] offen
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: buffer_load_short_d16_hi [[DST]], v{{[0-9]+}}, [[RSRC]], [[SOFF]] offen
define <2 x half> @chain_hi_to_lo_private_different_bases(half addrspace(5)* %base_lo, half addrspace(5)* %base_hi) {
+; GCN-LABEL: chain_hi_to_lo_private_different_bases:
+; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: buffer_load_ushort v0, v0, s[0:3], s33 offen
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: buffer_load_short_d16_hi v0, v1, s[0:3], s33 offen
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
bb:
%load_lo = load half, half addrspace(5)* %base_lo
%load_hi = load half, half addrspace(5)* %base_hi
@@ -32,10 +41,15 @@ bb:
ret <2 x half> %result
}
-; GCN-LABEL: {{^}}chain_hi_to_lo_arithmatic:
-; GCN: v_add_f16_e32 [[DST:v[0-9]+]], 1.0, v{{[0-9]+}}
-; GCN-NEXT: buffer_load_short_d16_hi [[DST]], v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen
define <2 x half> @chain_hi_to_lo_arithmatic(half addrspace(5)* %base, half %in) {
+; GCN-LABEL: chain_hi_to_lo_arithmatic:
+; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_add_f16_e32 v1, 1.0, v1
+; GCN-NEXT: buffer_load_short_d16_hi v1, v0, s[0:3], s33 offen
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, v1
+; GCN-NEXT: s_setpc_b64 s[30:31]
bb:
%arith_lo = fadd half %in, 1.0
%load_hi = load half, half addrspace(5)* %base
@@ -46,11 +60,16 @@ bb:
ret <2 x half> %result
}
-; GCN-LABEL: {{^}}chain_hi_to_lo_group:
-; GCN: ds_read_u16 [[DST:v[0-9]+]], [[ADDR:v[0-9]+]] offset:2
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: ds_read_u16_d16_hi [[DST]], [[ADDR]]
define <2 x half> @chain_hi_to_lo_group() {
+; GCN-LABEL: chain_hi_to_lo_group:
+; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: ds_read_u16 v0, v1 offset:2
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: ds_read_u16_d16_hi v0, v1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
bb:
%gep_lo = getelementptr inbounds half, half addrspace(3)* null, i64 1
%load_lo = load half, half addrspace(3)* %gep_lo
@@ -63,11 +82,15 @@ bb:
ret <2 x half> %result
}
-; GCN-LABEL: {{^}}chain_hi_to_lo_group_different_bases:
-; GCN: ds_read_u16 [[DST:v[0-9]+]], v{{[0-9]+}}
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: ds_read_u16_d16_hi [[DST]], v{{[0-9]+}}
define <2 x half> @chain_hi_to_lo_group_different_bases(half addrspace(3)* %base_lo, half addrspace(3)* %base_hi) {
+; GCN-LABEL: chain_hi_to_lo_group_different_bases:
+; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: ds_read_u16 v0, v0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: ds_read_u16_d16_hi v0, v1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
bb:
%load_lo = load half, half addrspace(3)* %base_lo
%load_hi = load half, half addrspace(3)* %base_hi
@@ -78,10 +101,19 @@ bb:
ret <2 x half> %result
}
-; GCN-LABEL: {{^}}chain_hi_to_lo_global:
-; GCN: global_load_ushort [[DST:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, off
-; GCN: global_load_short_d16_hi [[DST]], v{{\[[0-9]+:[0-9]+\]}}, off
define <2 x half> @chain_hi_to_lo_global() {
+; GCN-LABEL: chain_hi_to_lo_global:
+; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, 2
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: global_load_ushort v0, v[0:1], off
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: v_mov_b32_e32 v2, 0
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: global_load_short_d16_hi v0, v[1:2], off
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
bb:
%gep_lo = getelementptr inbounds half, half addrspace(1)* null, i64 1
%load_lo = load half, half addrspace(1)* %gep_lo
@@ -94,11 +126,15 @@ bb:
ret <2 x half> %result
}
-; GCN-LABEL: {{^}}chain_hi_to_lo_global_different_bases:
-; GCN: global_load_ushort [[DST:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, off
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: global_load_short_d16_hi [[DST]], v{{\[[0-9]+:[0-9]+\]}}, off
define <2 x half> @chain_hi_to_lo_global_different_bases(half addrspace(1)* %base_lo, half addrspace(1)* %base_hi) {
+; GCN-LABEL: chain_hi_to_lo_global_different_bases:
+; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: global_load_ushort v0, v[0:1], off
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: global_load_short_d16_hi v0, v[2:3], off
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
bb:
%load_lo = load half, half addrspace(1)* %base_lo
%load_hi = load half, half addrspace(1)* %base_hi
@@ -109,10 +145,19 @@ bb:
ret <2 x half> %result
}
-; GCN-LABEL: {{^}}chain_hi_to_lo_flat:
-; GCN: flat_load_ushort [[DST:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}
-; GCN: flat_load_short_d16_hi [[DST]], v{{\[[0-9]+:[0-9]+\]}}
define <2 x half> @chain_hi_to_lo_flat() {
+; GCN-LABEL: chain_hi_to_lo_flat:
+; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, 2
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: flat_load_ushort v0, v[0:1]
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: v_mov_b32_e32 v2, 0
+; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GCN-NEXT: flat_load_short_d16_hi v0, v[1:2]
+; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
bb:
%gep_lo = getelementptr inbounds half, half* null, i64 1
%load_lo = load half, half* %gep_lo
@@ -125,11 +170,15 @@ bb:
ret <2 x half> %result
}
-; GCN-LABEL: {{^}}chain_hi_to_lo_flat_different_bases:
-; GCN: flat_load_ushort [[DST:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}
-; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN-NEXT: flat_load_short_d16_hi [[DST]], v{{\[[0-9]+:[0-9]+\]}}
define <2 x half> @chain_hi_to_lo_flat_different_bases(half* %base_lo, half* %base_hi) {
+; GCN-LABEL: chain_hi_to_lo_flat_different_bases:
+; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: flat_load_ushort v0, v[0:1]
+; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GCN-NEXT: flat_load_short_d16_hi v0, v[2:3]
+; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
bb:
%load_lo = load half, half* %base_lo
%load_hi = load half, half* %base_hi
@@ -141,15 +190,35 @@ bb:
}
; Make sure we don't lose any of the private stores.
-; GCN-LABEL: {{^}}vload2_private:
-; GCN: buffer_store_short v{{[0-9]+}}, off, s[0:3], s{{[0-9]+}} offset:4
-; GCN: buffer_store_short_d16_hi v{{[0-9]+}}, off, s[0:3], s{{[0-9]+}} offset:6
-; GCN: buffer_store_short v{{[0-9]+}}, off, s[0:3], s{{[0-9]+}} offset:8
-
-; GCN: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s{{[0-9]+}} offset:4
-; GCN: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s{{[0-9]+}} offset:6
-; GCN: buffer_load_short_d16_hi v{{[0-9]+}}, off, s[0:3], s{{[0-9]+}} offset:8
define amdgpu_kernel void @vload2_private(i16 addrspace(1)* nocapture readonly %in, <2 x i16> addrspace(1)* nocapture %out) #0 {
+; GCN-LABEL: vload2_private:
+; GCN: ; %bb.0: ; %entry
+; GCN-NEXT: s_add_u32 flat_scratch_lo, s6, s9
+; GCN-NEXT: s_addc_u32 flat_scratch_hi, s7, 0
+; GCN-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v2, s4
+; GCN-NEXT: v_mov_b32_e32 v3, s5
+; GCN-NEXT: global_load_dword v4, v[2:3], off
+; GCN-NEXT: global_load_ushort v2, v[2:3], off offset:4
+; GCN-NEXT: v_mov_b32_e32 v0, s6
+; GCN-NEXT: v_mov_b32_e32 v1, s7
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: buffer_store_short v4, off, s[0:3], s9 offset:4
+; GCN-NEXT: buffer_store_short_d16_hi v4, off, s[0:3], s9 offset:6
+; GCN-NEXT: s_waitcnt vmcnt(2)
+; GCN-NEXT: buffer_store_short v2, off, s[0:3], s9 offset:8
+; GCN-NEXT: buffer_load_ushort v2, off, s[0:3], s9 offset:4
+; GCN-NEXT: buffer_load_ushort v4, off, s[0:3], s9 offset:6
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v3, v4
+; GCN-NEXT: buffer_load_short_d16_hi v3, off, s[0:3], s9 offset:8
+; GCN-NEXT: v_lshl_or_b32 v2, v4, 16, v2
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
+; GCN-NEXT: s_endpgm
entry:
%loc = alloca [3 x i16], align 2, addrspace(5)
%loc.0.sroa_cast1 = bitcast [3 x i16] addrspace(5)* %loc to i8 addrspace(5)*
@@ -178,15 +247,17 @@ entry:
; There is another instruction between the misordered instruction and
; the value dependent load, so a simple operand check is insufficient.
-; GCN-LABEL: {{^}}chain_hi_to_lo_group_other_dep:
-; GFX900: ds_read_u16_d16_hi v1, v0
-; GFX900-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-NEXT: v_pk_sub_u16 v1, v1, -12 op_sel_hi:[1,0]
-; GFX900-NEXT: ds_read_u16_d16 v1, v0 offset:2
-; GFX900-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v0, v1
-; GFX900-NEXT: s_setpc_b64
define <2 x i16> @chain_hi_to_lo_group_other_dep(i16 addrspace(3)* %ptr) {
+; GCN-LABEL: chain_hi_to_lo_group_other_dep:
+; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: ds_read_u16_d16_hi v1, v0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: v_pk_sub_u16 v1, v1, -12 op_sel_hi:[1,0]
+; GCN-NEXT: ds_read_u16_d16 v1, v0 offset:2
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, v1
+; GCN-NEXT: s_setpc_b64 s[30:31]
bb:
%gep_lo = getelementptr inbounds i16, i16 addrspace(3)* %ptr, i64 1
%load_lo = load i16, i16 addrspace(3)* %gep_lo
@@ -199,15 +270,17 @@ bb:
}
; The volatile operations aren't put on the same chain
-; GCN-LABEL: {{^}}chain_hi_to_lo_group_other_dep_multi_chain:
-; GFX900: ds_read_u16 v1, v0 offset:2
-; GFX900-NEXT: ds_read_u16_d16_hi v0, v0
-; GFX900-NEXT: v_mov_b32_e32 [[MASK:v[0-9]+]], 0xffff
-; GFX900-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-NEXT: v_pk_sub_u16 v0, v0, -12 op_sel_hi:[1,0]
-; GFX900-NEXT: v_bfi_b32 v0, [[MASK]], v1, v0
-; GFX900-NEXT: s_setpc_b64
define <2 x i16> @chain_hi_to_lo_group_other_dep_multi_chain(i16 addrspace(3)* %ptr) {
+; GCN-LABEL: chain_hi_to_lo_group_other_dep_multi_chain:
+; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: ds_read_u16 v1, v0 offset:2
+; GCN-NEXT: ds_read_u16_d16_hi v0, v0
+; GCN-NEXT: v_mov_b32_e32 v2, 0xffff
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: v_pk_sub_u16 v0, v0, -12 op_sel_hi:[1,0]
+; GCN-NEXT: v_bfi_b32 v0, v2, v1, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
bb:
%gep_lo = getelementptr inbounds i16, i16 addrspace(3)* %ptr, i64 1
%load_lo = load volatile i16, i16 addrspace(3)* %gep_lo
@@ -219,15 +292,17 @@ bb:
ret <2 x i16> %result
}
-; GCN-LABEL: {{^}}chain_hi_to_lo_private_other_dep:
-; GFX900: buffer_load_short_d16_hi v1, v0, s[0:3], s33 offen
-; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_pk_sub_u16 v1, v1, -12 op_sel_hi:[1,0]
-; GFX900-NEXT: buffer_load_short_d16 v1, v0, s[0:3], s33 offen offset:2
-; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_mov_b32_e32 v0, v1
-; GFX900-NEXT: s_setpc_b64
define <2 x i16> @chain_hi_to_lo_private_other_dep(i16 addrspace(5)* %ptr) {
+; GCN-LABEL: chain_hi_to_lo_private_other_dep:
+; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: buffer_load_short_d16_hi v1, v0, s[0:3], s33 offen
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_pk_sub_u16 v1, v1, -12 op_sel_hi:[1,0]
+; GCN-NEXT: buffer_load_short_d16 v1, v0, s[0:3], s33 offen offset:2
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, v1
+; GCN-NEXT: s_setpc_b64 s[30:31]
bb:
%gep_lo = getelementptr inbounds i16, i16 addrspace(5)* %ptr, i64 1
%load_lo = load i16, i16 addrspace(5)* %gep_lo
@@ -239,15 +314,17 @@ bb:
ret <2 x i16> %result
}
-; GCN-LABEL: {{^}}chain_hi_to_lo_global_other_dep:
-; GFX900: global_load_ushort v2, v[0:1], off offset:2
-; GFX900-NEXT: global_load_short_d16_hi v0, v[0:1], off
-; GFX900-NEXT: v_mov_b32_e32 [[MASK:v[0-9]+]], 0xffff
-; GFX900-NEXT: s_waitcnt vmcnt(0)
-; GFX900-NEXT: v_pk_sub_u16 v0, v0, -12 op_sel_hi:[1,0]
-; GFX900-NEXT: v_bfi_b32 v0, [[MASK]], v2, v0
-; GFX900-NEXT: s_setpc_b64
define <2 x i16> @chain_hi_to_lo_global_other_dep(i16 addrspace(1)* %ptr) {
+; GCN-LABEL: chain_hi_to_lo_global_other_dep:
+; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: global_load_ushort v2, v[0:1], off offset:2
+; GCN-NEXT: global_load_short_d16_hi v0, v[0:1], off
+; GCN-NEXT: v_mov_b32_e32 v1, 0xffff
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_pk_sub_u16 v0, v0, -12 op_sel_hi:[1,0]
+; GCN-NEXT: v_bfi_b32 v0, v1, v2, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
bb:
%gep_lo = getelementptr inbounds i16, i16 addrspace(1)* %ptr, i64 1
%load_lo = load volatile i16, i16 addrspace(1)* %gep_lo
@@ -259,15 +336,17 @@ bb:
ret <2 x i16> %result
}
-; GCN-LABEL: {{^}}chain_hi_to_lo_flat_other_dep:
-; GFX900: flat_load_ushort v2, v[0:1] offset:2
-; GFX900-NEXT: flat_load_short_d16_hi v0, v[0:1]
-; GFX900-NEXT: v_mov_b32_e32 [[MASK:v[0-9]+]], 0xffff
-; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_pk_sub_u16 v0, v0, -12 op_sel_hi:[1,0]
-; GFX900-NEXT: v_bfi_b32 v0, v1, v2, v0
-; GFX900-NEXT: s_setpc_b64
define <2 x i16> @chain_hi_to_lo_flat_other_dep(i16 addrspace(0)* %ptr) {
+; GCN-LABEL: chain_hi_to_lo_flat_other_dep:
+; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: flat_load_ushort v2, v[0:1] offset:2
+; GCN-NEXT: flat_load_short_d16_hi v0, v[0:1]
+; GCN-NEXT: v_mov_b32_e32 v1, 0xffff
+; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_pk_sub_u16 v0, v0, -12 op_sel_hi:[1,0]
+; GCN-NEXT: v_bfi_b32 v0, v1, v2, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
bb:
%gep_lo = getelementptr inbounds i16, i16 addrspace(0)* %ptr, i64 1
%load_lo = load volatile i16, i16 addrspace(0)* %gep_lo
@@ -279,16 +358,18 @@ bb:
ret <2 x i16> %result
}
-; GCN-LABEL: {{^}}chain_hi_to_lo_group_may_alias_store:
-; GFX900: v_mov_b32_e32 [[K:v[0-9]+]], 0x7b
-; GFX900-NEXT: ds_read_u16 v2, v0
-; GFX900-NEXT: ds_write_b16 v1, [[K]]
-; GFX900-NEXT: ds_read_u16 v0, v0 offset:2
-; GFX900-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX900-NEXT: v_lshl_or_b32 v0, v2, 16, v0
-; GFX900-NEXT: s_setpc_b64
define <2 x i16> @chain_hi_to_lo_group_may_alias_store(i16 addrspace(3)* %ptr, i16 addrspace(3)* %may.alias) {
+; GCN-LABEL: chain_hi_to_lo_group_may_alias_store:
+; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v3, 0x7b
+; GCN-NEXT: ds_read_u16 v2, v0
+; GCN-NEXT: ds_write_b16 v1, v3
+; GCN-NEXT: ds_read_u16 v0, v0 offset:2
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GCN-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
bb:
%gep_lo = getelementptr inbounds i16, i16 addrspace(3)* %ptr, i64 1
%gep_hi = getelementptr inbounds i16, i16 addrspace(3)* %ptr, i64 0
Modified: llvm/trunk/test/CodeGen/AMDGPU/copy-illegal-type.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/copy-illegal-type.ll?rev=369787&r1=369786&r2=369787&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/copy-illegal-type.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/copy-illegal-type.ll Fri Aug 23 10:58:49 2019
@@ -1,14 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=tahiti < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-sdwa-peephole=0 < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone
-; FUNC-LABEL: {{^}}test_copy_v4i8:
-; GCN: {{buffer|flat}}_load_dword [[REG:v[0-9]+]]
-; GCN: buffer_store_dword [[REG]]
-; GCN: s_endpgm
define amdgpu_kernel void @test_copy_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) nounwind {
+; SI-LABEL: test_copy_v4i8:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s10, 0
+; SI-NEXT: s_mov_b32 s11, s7
+; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
+; SI-NEXT: v_mov_b32_e32 v1, 0
+; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_mov_b32 s4, s0
+; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: test_copy_v4i8:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: flat_load_dword v0, v[0:1]
+; VI-NEXT: s_mov_b32 s4, s0
+; VI-NEXT: s_mov_b32 s5, s1
+; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; VI-NEXT: s_endpgm
%tid.x = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid.x
%val = load <4 x i8>, <4 x i8> addrspace(1)* %gep, align 4
@@ -16,12 +47,48 @@ define amdgpu_kernel void @test_copy_v4i
ret void
}
-; FUNC-LABEL: {{^}}test_copy_v4i8_x2:
-; GCN: {{buffer|flat}}_load_dword [[REG:v[0-9]+]]
-; GCN: buffer_store_dword [[REG]]
-; GCN: buffer_store_dword [[REG]]
-; GCN: s_endpgm
define amdgpu_kernel void @test_copy_v4i8_x2(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %in) nounwind {
+; SI-LABEL: test_copy_v4i8_x2:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
+; SI-NEXT: s_mov_b32 s11, 0xf000
+; SI-NEXT: s_mov_b32 s2, 0
+; SI-NEXT: s_mov_b32 s3, s11
+; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; SI-NEXT: v_mov_b32_e32 v1, 0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
+; SI-NEXT: s_mov_b32 s10, -1
+; SI-NEXT: s_mov_b32 s8, s6
+; SI-NEXT: s_mov_b32 s9, s7
+; SI-NEXT: s_mov_b32 s6, s10
+; SI-NEXT: s_mov_b32 s7, s11
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: test_copy_v4i8_x2:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
+; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s0, s6
+; VI-NEXT: v_mov_b32_e32 v1, s9
+; VI-NEXT: v_add_u32_e32 v0, vcc, s8, v0
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: flat_load_dword v0, v[0:1]
+; VI-NEXT: s_mov_b32 s1, s7
+; VI-NEXT: s_mov_b32 s6, s2
+; VI-NEXT: s_mov_b32 s7, s3
+; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%tid.x = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid.x
%val = load <4 x i8>, <4 x i8> addrspace(1)* %gep, align 4
@@ -30,13 +97,57 @@ define amdgpu_kernel void @test_copy_v4i
ret void
}
-; FUNC-LABEL: {{^}}test_copy_v4i8_x3:
-; GCN: {{buffer|flat}}_load_dword [[REG:v[0-9]+]]
-; GCN: buffer_store_dword [[REG]]
-; GCN: buffer_store_dword [[REG]]
-; GCN: buffer_store_dword [[REG]]
-; GCN: s_endpgm
define amdgpu_kernel void @test_copy_v4i8_x3(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %out2, <4 x i8> addrspace(1)* %in) nounwind {
+; SI-LABEL: test_copy_v4i8_x3:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
+; SI-NEXT: s_mov_b32 s11, 0xf000
+; SI-NEXT: s_mov_b32 s14, 0
+; SI-NEXT: s_mov_b32 s15, s11
+; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b64 s[12:13], s[6:7]
+; SI-NEXT: v_mov_b32_e32 v1, 0
+; SI-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64
+; SI-NEXT: s_mov_b32 s10, -1
+; SI-NEXT: s_mov_b32 s8, s4
+; SI-NEXT: s_mov_b32 s9, s5
+; SI-NEXT: s_mov_b32 s4, s2
+; SI-NEXT: s_mov_b32 s5, s3
+; SI-NEXT: s_mov_b32 s6, s10
+; SI-NEXT: s_mov_b32 s7, s11
+; SI-NEXT: s_mov_b32 s2, s10
+; SI-NEXT: s_mov_b32 s3, s11
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: test_copy_v4i8_x3:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; VI-NEXT: s_mov_b32 s11, 0xf000
+; VI-NEXT: s_mov_b32 s10, -1
+; VI-NEXT: s_mov_b32 s14, s10
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s7
+; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v0
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: flat_load_dword v0, v[0:1]
+; VI-NEXT: s_mov_b32 s12, s2
+; VI-NEXT: s_mov_b32 s13, s3
+; VI-NEXT: s_mov_b32 s8, s4
+; VI-NEXT: s_mov_b32 s9, s5
+; VI-NEXT: s_mov_b32 s15, s11
+; VI-NEXT: s_mov_b32 s2, s10
+; VI-NEXT: s_mov_b32 s3, s11
+; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: buffer_store_dword v0, off, s[12:15], 0
+; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
+; VI-NEXT: s_endpgm
%tid.x = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid.x
%val = load <4 x i8>, <4 x i8> addrspace(1)* %gep, align 4
@@ -46,14 +157,65 @@ define amdgpu_kernel void @test_copy_v4i
ret void
}
-; FUNC-LABEL: {{^}}test_copy_v4i8_x4:
-; GCN: {{buffer|flat}}_load_dword [[REG:v[0-9]+]]
-; GCN: buffer_store_dword [[REG]]
-; GCN: buffer_store_dword [[REG]]
-; GCN: buffer_store_dword [[REG]]
-; GCN: buffer_store_dword [[REG]]
-; GCN: s_endpgm
define amdgpu_kernel void @test_copy_v4i8_x4(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %out2, <4 x i8> addrspace(1)* %out3, <4 x i8> addrspace(1)* %in) nounwind {
+; SI-LABEL: test_copy_v4i8_x4:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x11
+; SI-NEXT: s_mov_b32 s15, 0xf000
+; SI-NEXT: s_mov_b32 s10, 0
+; SI-NEXT: s_mov_b32 s11, s15
+; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; SI-NEXT: v_mov_b32_e32 v1, 0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
+; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
+; SI-NEXT: s_mov_b32 s14, -1
+; SI-NEXT: s_mov_b32 s18, s14
+; SI-NEXT: s_mov_b32 s19, s15
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b32 s12, s6
+; SI-NEXT: s_mov_b32 s13, s7
+; SI-NEXT: s_mov_b32 s16, s2
+; SI-NEXT: s_mov_b32 s17, s3
+; SI-NEXT: s_mov_b32 s6, s14
+; SI-NEXT: s_mov_b32 s7, s15
+; SI-NEXT: s_mov_b32 s2, s14
+; SI-NEXT: s_mov_b32 s3, s15
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: buffer_store_dword v0, off, s[16:19], 0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-NEXT: buffer_store_dword v0, off, s[12:15], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: test_copy_v4i8_x4:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x44
+; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
+; VI-NEXT: s_mov_b32 s11, 0xf000
+; VI-NEXT: s_mov_b32 s10, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s9
+; VI-NEXT: v_add_u32_e32 v0, vcc, s8, v0
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: flat_load_dword v0, v[0:1]
+; VI-NEXT: s_mov_b32 s8, s6
+; VI-NEXT: s_mov_b32 s9, s7
+; VI-NEXT: s_mov_b32 s12, s2
+; VI-NEXT: s_mov_b32 s13, s3
+; VI-NEXT: s_mov_b32 s6, s10
+; VI-NEXT: s_mov_b32 s7, s11
+; VI-NEXT: s_mov_b32 s14, s10
+; VI-NEXT: s_mov_b32 s15, s11
+; VI-NEXT: s_mov_b32 s2, s10
+; VI-NEXT: s_mov_b32 s3, s11
+; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: buffer_store_dword v0, off, s[12:15], 0
+; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
+; VI-NEXT: s_endpgm
%tid.x = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid.x
%val = load <4 x i8>, <4 x i8> addrspace(1)* %gep, align 4
@@ -64,16 +226,82 @@ define amdgpu_kernel void @test_copy_v4i
ret void
}
-; FUNC-LABEL: {{^}}test_copy_v4i8_extra_use:
-; GCN: {{buffer|flat}}_load_dword
-; GCN-DAG: v_lshrrev_b32
-; GCN: v_and_b32
-; GCN: v_or_b32
-; GCN-DAG: buffer_store_dword
-; GCN-DAG: buffer_store_dword
-
-; GCN: s_endpgm
define amdgpu_kernel void @test_copy_v4i8_extra_use(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %in) nounwind {
+; SI-LABEL: test_copy_v4i8_extra_use:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
+; SI-NEXT: s_mov_b32 s11, 0xf000
+; SI-NEXT: s_mov_b32 s2, 0
+; SI-NEXT: s_mov_b32 s3, s11
+; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; SI-NEXT: v_mov_b32_e32 v1, 0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64
+; SI-NEXT: s_mov_b32 s10, -1
+; SI-NEXT: s_mov_b32 s0, 0xff00
+; SI-NEXT: s_mov_b32 s8, s6
+; SI-NEXT: s_mov_b32 s9, s7
+; SI-NEXT: s_mov_b32 s6, s10
+; SI-NEXT: s_mov_b32 s7, s11
+; SI-NEXT: s_movk_i32 s1, 0xff
+; SI-NEXT: s_movk_i32 s2, 0x900
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-NEXT: v_and_b32_e32 v2, s0, v0
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_add_i32_e32 v0, vcc, 9, v0
+; SI-NEXT: v_and_b32_e32 v0, s1, v0
+; SI-NEXT: v_and_b32_e32 v3, s0, v1
+; SI-NEXT: v_add_i32_e32 v1, vcc, 9, v1
+; SI-NEXT: v_or_b32_e32 v0, v2, v0
+; SI-NEXT: v_and_b32_e32 v1, s1, v1
+; SI-NEXT: v_add_i32_e32 v0, vcc, s2, v0
+; SI-NEXT: v_or_b32_e32 v1, v3, v1
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x9000000, v0
+; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: test_copy_v4i8_extra_use:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
+; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; VI-NEXT: s_movk_i32 s10, 0xff00
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: flat_load_dword v0, v[0:1]
+; VI-NEXT: s_mov_b32 s0, s6
+; VI-NEXT: s_mov_b32 s1, s7
+; VI-NEXT: s_movk_i32 s8, 0xff
+; VI-NEXT: s_mov_b32 s6, s2
+; VI-NEXT: s_mov_b32 s7, s3
+; VI-NEXT: s_movk_i32 s9, 0x900
+; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; VI-NEXT: v_and_b32_e32 v3, s10, v1
+; VI-NEXT: v_add_u16_e32 v1, 9, v1
+; VI-NEXT: v_and_b32_e32 v1, s8, v1
+; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; VI-NEXT: v_and_b32_e32 v2, s10, v0
+; VI-NEXT: v_add_u16_e32 v0, 9, v0
+; VI-NEXT: v_and_b32_e32 v0, s8, v0
+; VI-NEXT: v_or_b32_e32 v1, v3, v1
+; VI-NEXT: v_or_b32_e32 v0, v2, v0
+; VI-NEXT: v_add_u16_e32 v1, s9, v1
+; VI-NEXT: v_add_u16_e32 v0, s9, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%tid.x = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid.x
%val = load <4 x i8>, <4 x i8> addrspace(1)* %gep, align 4
@@ -84,18 +312,88 @@ define amdgpu_kernel void @test_copy_v4i
}
; FIXME: Need to handle non-uniform case for function below (load without gep).
-; FUNC-LABEL: {{^}}test_copy_v4i8_x2_extra_use:
-; GCN: {{buffer|flat}}_load_dword
-; GCN-DAG: v_lshrrev_b32
-; SI-DAG: v_add_i32
-; VI-DAG: v_add_u16
-; GCN-DAG: v_and_b32
-; GCN-DAG: v_or_b32
-; GCN-DAG: {{buffer|flat}}_store_dword
-; GCN: {{buffer|flat}}_store_dword
-; GCN: {{buffer|flat}}_store_dword
-; GCN: s_endpgm
define amdgpu_kernel void @test_copy_v4i8_x2_extra_use(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %out2, <4 x i8> addrspace(1)* %in) nounwind {
+; SI-LABEL: test_copy_v4i8_x2_extra_use:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
+; SI-NEXT: s_mov_b32 s11, 0xf000
+; SI-NEXT: s_mov_b32 s14, 0
+; SI-NEXT: s_mov_b32 s15, s11
+; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b64 s[12:13], s[6:7]
+; SI-NEXT: v_mov_b32_e32 v1, 0
+; SI-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64
+; SI-NEXT: s_mov_b32 s16, 0xff00
+; SI-NEXT: s_movk_i32 s17, 0xff
+; SI-NEXT: s_movk_i32 s18, 0x900
+; SI-NEXT: s_mov_b32 s10, -1
+; SI-NEXT: s_mov_b32 s8, s4
+; SI-NEXT: s_mov_b32 s9, s5
+; SI-NEXT: s_mov_b32 s4, s2
+; SI-NEXT: s_mov_b32 s5, s3
+; SI-NEXT: s_mov_b32 s6, s10
+; SI-NEXT: s_mov_b32 s7, s11
+; SI-NEXT: s_mov_b32 s2, s10
+; SI-NEXT: s_mov_b32 s3, s11
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_add_i32_e32 v3, vcc, 9, v0
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; SI-NEXT: v_and_b32_e32 v4, s16, v1
+; SI-NEXT: v_add_i32_e32 v1, vcc, 9, v1
+; SI-NEXT: v_and_b32_e32 v2, s16, v0
+; SI-NEXT: v_and_b32_e32 v3, s17, v3
+; SI-NEXT: v_or_b32_e32 v2, v2, v3
+; SI-NEXT: v_and_b32_e32 v1, s17, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, s18, v2
+; SI-NEXT: v_or_b32_e32 v1, v4, v1
+; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_add_i32_e32 v1, vcc, 0x9000000, v1
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: test_copy_v4i8_x2_extra_use:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; VI-NEXT: s_movk_i32 s14, 0xff00
+; VI-NEXT: s_movk_i32 s12, 0xff
+; VI-NEXT: s_movk_i32 s13, 0x900
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s7
+; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v0
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: flat_load_dword v0, v[0:1]
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: s_mov_b32 s8, s2
+; VI-NEXT: s_mov_b32 s9, s3
+; VI-NEXT: s_mov_b32 s10, s6
+; VI-NEXT: s_mov_b32 s11, s7
+; VI-NEXT: s_mov_b32 s2, s6
+; VI-NEXT: s_mov_b32 s3, s7
+; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; VI-NEXT: v_and_b32_e32 v4, s14, v1
+; VI-NEXT: v_add_u16_e32 v1, 9, v1
+; VI-NEXT: v_add_u16_e32 v3, 9, v0
+; VI-NEXT: v_and_b32_e32 v1, s12, v1
+; VI-NEXT: v_or_b32_e32 v1, v4, v1
+; VI-NEXT: v_and_b32_e32 v2, s14, v0
+; VI-NEXT: v_and_b32_e32 v3, s12, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_add_u16_e32 v1, s13, v1
+; VI-NEXT: v_add_u16_e32 v2, s13, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: buffer_store_dword v1, off, s[8:11], 0
+; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; VI-NEXT: s_endpgm
%tid.x = call i32 @llvm.amdgcn.workitem.id.x()
%in.ptr = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid.x
%val = load <4 x i8>, <4 x i8> addrspace(1)* %in.ptr, align 4
@@ -106,12 +404,45 @@ define amdgpu_kernel void @test_copy_v4i
ret void
}
-; FUNC-LABEL: {{^}}test_copy_v3i8_align4:
-; GCN: {{buffer|flat}}_load_dword
-; GCN-DAG: buffer_store_short v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
-; GCN-DAG: buffer_store_byte v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:2{{$}}
-; GCN: s_endpgm
define amdgpu_kernel void @test_copy_v3i8_align4(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(1)* %in) nounwind {
+; SI-LABEL: test_copy_v3i8_align4:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s10, 0
+; SI-NEXT: s_mov_b32 s11, s7
+; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
+; SI-NEXT: v_mov_b32_e32 v1, 0
+; SI-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_mov_b32 s4, s0
+; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
+; SI-NEXT: buffer_store_byte v1, off, s[4:7], 0 offset:2
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: test_copy_v3i8_align4:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: flat_load_dword v0, v[0:1]
+; VI-NEXT: s_mov_b32 s4, s0
+; VI-NEXT: s_mov_b32 s5, s1
+; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_store_short v0, off, s[4:7], 0
+; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0 offset:2
+; VI-NEXT: s_endpgm
%tid.x = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr <3 x i8>, <3 x i8> addrspace(1)* %in, i32 %tid.x
%val = load <3 x i8>, <3 x i8> addrspace(1)* %gep, align 4
@@ -119,54 +450,185 @@ define amdgpu_kernel void @test_copy_v3i
ret void
}
-; FUNC-LABEL: {{^}}test_copy_v3i8_align2:
-; GCN-DAG: {{buffer|flat}}_load_ushort v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
-; GCN-DAG: {{buffer|flat}}_load_ubyte v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:2{{$}}
-; GCN-DAG: buffer_store_short v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
-; GCN-DAG: buffer_store_byte v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:2{{$}}
-; GCN: s_endpgm
define amdgpu_kernel void @test_copy_v3i8_align2(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(1)* %in) nounwind {
+; SI-LABEL: test_copy_v3i8_align2:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_mov_b32 s10, s2
+; SI-NEXT: s_mov_b32 s11, s3
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b32 s8, s6
+; SI-NEXT: s_mov_b32 s9, s7
+; SI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
+; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:2
+; SI-NEXT: s_mov_b32 s0, s4
+; SI-NEXT: s_mov_b32 s1, s5
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:2
+; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: test_copy_v3i8_align2:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_mov_b32 s10, s2
+; VI-NEXT: s_mov_b32 s11, s3
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s8, s6
+; VI-NEXT: s_mov_b32 s9, s7
+; VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
+; VI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:2
+; VI-NEXT: s_mov_b32 s0, s4
+; VI-NEXT: s_mov_b32 s1, s5
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:2
+; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%val = load <3 x i8>, <3 x i8> addrspace(1)* %in, align 2
store <3 x i8> %val, <3 x i8> addrspace(1)* %out, align 2
ret void
}
-; FUNC-LABEL: {{^}}test_copy_v3i8_align1:
-; GCN: {{buffer|flat}}_load_ubyte
-; GCN: {{buffer|flat}}_load_ubyte
-; GCN: {{buffer|flat}}_load_ubyte
-
-; GCN: buffer_store_byte
-; GCN: buffer_store_byte
-; GCN: buffer_store_byte
-; GCN: s_endpgm
define amdgpu_kernel void @test_copy_v3i8_align1(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(1)* %in) nounwind {
+; SI-LABEL: test_copy_v3i8_align1:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_mov_b32 s10, s2
+; SI-NEXT: s_mov_b32 s11, s3
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b32 s8, s6
+; SI-NEXT: s_mov_b32 s9, s7
+; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:1
+; SI-NEXT: buffer_load_ubyte v2, off, s[8:11], 0 offset:2
+; SI-NEXT: s_mov_b32 s0, s4
+; SI-NEXT: s_mov_b32 s1, s5
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:1
+; SI-NEXT: s_waitcnt vmcnt(2)
+; SI-NEXT: buffer_store_byte v2, off, s[0:3], 0 offset:2
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: test_copy_v3i8_align1:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_mov_b32 s10, s2
+; VI-NEXT: s_mov_b32 s11, s3
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s8, s6
+; VI-NEXT: s_mov_b32 s9, s7
+; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; VI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:1
+; VI-NEXT: buffer_load_ubyte v2, off, s[8:11], 0 offset:2
+; VI-NEXT: s_mov_b32 s0, s4
+; VI-NEXT: s_mov_b32 s1, s5
+; VI-NEXT: s_waitcnt vmcnt(2)
+; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0
+; VI-NEXT: s_waitcnt vmcnt(2)
+; VI-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:1
+; VI-NEXT: s_waitcnt vmcnt(2)
+; VI-NEXT: buffer_store_byte v2, off, s[0:3], 0 offset:2
+; VI-NEXT: s_endpgm
%val = load <3 x i8>, <3 x i8> addrspace(1)* %in, align 1
store <3 x i8> %val, <3 x i8> addrspace(1)* %out, align 1
ret void
}
-; FUNC-LABEL: {{^}}test_copy_v4i8_volatile_load:
-; GCN: {{buffer|flat}}_load_dword
-; GCN: buffer_store_dword
-; GCN: s_endpgm
define amdgpu_kernel void @test_copy_v4i8_volatile_load(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) nounwind {
+; SI-LABEL: test_copy_v4i8_volatile_load:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b32 s0, s4
+; SI-NEXT: s_mov_b32 s1, s5
+; SI-NEXT: s_mov_b32 s4, s6
+; SI-NEXT: s_mov_b32 s5, s7
+; SI-NEXT: s_mov_b32 s6, s2
+; SI-NEXT: s_mov_b32 s7, s3
+; SI-NEXT: buffer_load_dword v0, off, s[4:7], 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: test_copy_v4i8_volatile_load:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s0, s4
+; VI-NEXT: s_mov_b32 s1, s5
+; VI-NEXT: s_mov_b32 s4, s6
+; VI-NEXT: s_mov_b32 s5, s7
+; VI-NEXT: s_mov_b32 s6, s2
+; VI-NEXT: s_mov_b32 s7, s3
+; VI-NEXT: buffer_load_dword v0, off, s[4:7], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%val = load volatile <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
store <4 x i8> %val, <4 x i8> addrspace(1)* %out, align 4
ret void
}
-; FUNC-LABEL: {{^}}test_copy_v4i8_volatile_store:
-; GCN: {{buffer|flat}}_load_ubyte
-; GCN: {{buffer|flat}}_load_ubyte
-; GCN: {{buffer|flat}}_load_ubyte
-; GCN: {{buffer|flat}}_load_ubyte
-; GCN: buffer_store_byte
-; GCN: buffer_store_byte
-; GCN: buffer_store_byte
-; GCN: buffer_store_byte
-; GCN: s_endpgm
define amdgpu_kernel void @test_copy_v4i8_volatile_store(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) nounwind {
+; SI-LABEL: test_copy_v4i8_volatile_store:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_mov_b32 s10, s2
+; SI-NEXT: s_mov_b32 s11, s3
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b32 s8, s6
+; SI-NEXT: s_mov_b32 s9, s7
+; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:1
+; SI-NEXT: buffer_load_ubyte v2, off, s[8:11], 0 offset:2
+; SI-NEXT: buffer_load_ubyte v3, off, s[8:11], 0 offset:3
+; SI-NEXT: s_mov_b32 s0, s4
+; SI-NEXT: s_mov_b32 s1, s5
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: buffer_store_byte v3, off, s[0:3], 0 offset:3
+; SI-NEXT: buffer_store_byte v2, off, s[0:3], 0 offset:2
+; SI-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:1
+; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: test_copy_v4i8_volatile_store:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_mov_b32 s10, s2
+; VI-NEXT: s_mov_b32 s11, s3
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s8, s6
+; VI-NEXT: s_mov_b32 s9, s7
+; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; VI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:1
+; VI-NEXT: buffer_load_ubyte v2, off, s[8:11], 0 offset:2
+; VI-NEXT: buffer_load_ubyte v3, off, s[8:11], 0 offset:3
+; VI-NEXT: s_mov_b32 s0, s4
+; VI-NEXT: s_mov_b32 s1, s5
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_store_byte v3, off, s[0:3], 0 offset:3
+; VI-NEXT: buffer_store_byte v2, off, s[0:3], 0 offset:2
+; VI-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:1
+; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%val = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
store volatile <4 x i8> %val, <4 x i8> addrspace(1)* %out, align 4
ret void
Modified: llvm/trunk/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll?rev=369787&r1=369786&r2=369787&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll Fri Aug 23 10:58:49 2019
@@ -1,14 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
-; GCN-LABEL: {{^}}eq_t:
-; GCN-DAG: s_load_dword [[X:s[0-9]+]]
-; GCN: v_cmp_lt_f32_e{{32|64}} [[CC:s\[[0-9]+:[0-9]+\]|vcc]], [[X]], 1.0{{$}}
-; GCN-NOT: 0xddd5
-; GCN-NOT: v_cndmask_b32
-; GCN-NOT: v_cmp_eq_u32
-; GCN: v_cndmask_b32_e{{32|64}} [[RES:v[0-9]+]], 2.0, 4.0, [[CC]]
-; GCN: store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
define amdgpu_kernel void @eq_t(float %x) {
+; GCN-LABEL: eq_t:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dword s0, s[0:1], 0x24
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: v_cmp_lt_f32_e64 s[0:1], s0, 1.0
+; GCN-NEXT: v_cndmask_b32_e64 v0, 2.0, 4.0, s[0:1]
+; GCN-NEXT: flat_store_dword v[0:1], v0
+; GCN-NEXT: s_endpgm
%c1 = fcmp olt float %x, 1.0
%s1 = select i1 %c1, i32 56789, i32 1
%c2 = icmp eq i32 %s1, 56789
@@ -17,15 +18,15 @@ define amdgpu_kernel void @eq_t(float %x
ret void
}
-; GCN-LABEL: {{^}}ne_t:
-; GCN-DAG: s_load_dword [[X:s[0-9]+]]
-; GCN: v_cmp_lt_f32_e{{32|64}} [[CC:s\[[0-9]+:[0-9]+\]|vcc]], [[X]], 1.0{{$}}
-; GCN-NOT: 0xddd5
-; GCN-NOT: v_cndmask_b32
-; GCN-NOT: v_cmp_eq_u32
-; GCN: v_cndmask_b32_e{{32|64}} [[RES:v[0-9]+]], 4.0, 2.0, [[CC]]
-; GCN: store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
define amdgpu_kernel void @ne_t(float %x) {
+; GCN-LABEL: ne_t:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dword s0, s[0:1], 0x24
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: v_cmp_lt_f32_e64 s[0:1], s0, 1.0
+; GCN-NEXT: v_cndmask_b32_e64 v0, 4.0, 2.0, s[0:1]
+; GCN-NEXT: flat_store_dword v[0:1], v0
+; GCN-NEXT: s_endpgm
%c1 = fcmp olt float %x, 1.0
%s1 = select i1 %c1, i32 56789, i32 1
%c2 = icmp ne i32 %s1, 56789
@@ -34,15 +35,15 @@ define amdgpu_kernel void @ne_t(float %x
ret void
}
-; GCN-LABEL: {{^}}eq_f:
-; GCN-DAG: s_load_dword [[X:s[0-9]+]]
-; GCN: v_cmp_lt_f32_e{{32|64}} [[CC:s\[[0-9]+:[0-9]+\]|vcc]], [[X]], 1.0{{$}}
-; GCN-NOT: 0xddd5
-; GCN-NOT: v_cndmask_b32
-; GCN-NOT: v_cmp_eq_u32
-; GCN: v_cndmask_b32_e{{32|64}} [[RES:v[0-9]+]], 4.0, 2.0, [[CC]]
-; GCN: store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
define amdgpu_kernel void @eq_f(float %x) {
+; GCN-LABEL: eq_f:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dword s0, s[0:1], 0x24
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: v_cmp_lt_f32_e64 s[0:1], s0, 1.0
+; GCN-NEXT: v_cndmask_b32_e64 v0, 4.0, 2.0, s[0:1]
+; GCN-NEXT: flat_store_dword v[0:1], v0
+; GCN-NEXT: s_endpgm
%c1 = fcmp olt float %x, 1.0
%s1 = select i1 %c1, i32 1, i32 56789
%c2 = icmp eq i32 %s1, 56789
@@ -51,15 +52,15 @@ define amdgpu_kernel void @eq_f(float %x
ret void
}
-; GCN-LABEL: {{^}}ne_f:
-; GCN-DAG: s_load_dword [[X:s[0-9]+]]
-; GCN: v_cmp_lt_f32_e{{32|64}} [[CC:s\[[0-9]+:[0-9]+\]|vcc]], [[X]], 1.0{{$}}
-; GCN-NOT: 0xddd5
-; GCN-NOT: v_cndmask_b32
-; GCN-NOT: v_cmp_eq_u32
-; GCN: v_cndmask_b32_e{{32|64}} [[RES:v[0-9]+]], 2.0, 4.0, [[CC]]
-; GCN: store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
define amdgpu_kernel void @ne_f(float %x) {
+; GCN-LABEL: ne_f:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_load_dword s0, s[0:1], 0x24
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: v_cmp_lt_f32_e64 s[0:1], s0, 1.0
+; GCN-NEXT: v_cndmask_b32_e64 v0, 2.0, 4.0, s[0:1]
+; GCN-NEXT: flat_store_dword v[0:1], v0
+; GCN-NEXT: s_endpgm
%c1 = fcmp olt float %x, 1.0
%s1 = select i1 %c1, i32 1, i32 56789
%c2 = icmp ne i32 %s1, 56789
@@ -68,10 +69,12 @@ define amdgpu_kernel void @ne_f(float %x
ret void
}
-; GCN-LABEL: {{^}}different_constants:
-; GCN: v_mov_b32_e32 [[RES:v[0-9]+]], 2.0
-; GCN: store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
define amdgpu_kernel void @different_constants(float %x) {
+; GCN-LABEL: different_constants:
+; GCN: ; %bb.0:
+; GCN-NEXT: v_mov_b32_e32 v0, 2.0
+; GCN-NEXT: flat_store_dword v[0:1], v0
+; GCN-NEXT: s_endpgm
%c1 = fcmp olt float %x, 1.0
%s1 = select i1 %c1, i32 56789, i32 1
%c2 = icmp eq i32 %s1, 5678
Modified: llvm/trunk/test/CodeGen/AMDGPU/load-lo16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/load-lo16.ll?rev=369787&r1=369786&r2=369787&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/load-lo16.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/load-lo16.ll Fri Aug 23 10:58:49 2019
@@ -1,28 +1,64 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-sroa=0 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX900 %s
; RUN: llc -march=amdgcn -mcpu=gfx906 -amdgpu-sroa=0 -mattr=-promote-alloca,+sram-ecc -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX906,NO-D16-HI %s
; RUN: llc -march=amdgcn -mcpu=fiji -amdgpu-sroa=0 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX803,NO-D16-HI %s
-; GCN-LABEL: {{^}}load_local_lo_v2i16_undeflo:
-; GCN: s_waitcnt
-; GFX900-NEXT: ds_read_u16_d16 v0, v0
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; NO-D16-HI: ds_read_u16
define <2 x i16> @load_local_lo_v2i16_undeflo(i16 addrspace(3)* %in) #0 {
+; GFX900-LABEL: load_local_lo_v2i16_undeflo:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: ds_read_u16_d16 v0, v0
+; GFX900-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_local_lo_v2i16_undeflo:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: ds_read_u16 v0, v0
+; GFX906-NEXT: s_waitcnt lgkmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_local_lo_v2i16_undeflo:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_mov_b32 m0, -1
+; GFX803-NEXT: ds_read_u16 v0, v0
+; GFX803-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load i16, i16 addrspace(3)* %in
%build = insertelement <2 x i16> undef, i16 %load, i32 0
ret <2 x i16> %build
}
-; GCN-LABEL: {{^}}load_local_lo_v2i16_reglo:
-; GCN: s_waitcnt
-; GCN: ds_read_u16 v0, v0
-; GFX9: v_and_b32_e32 v0, 0xffff, v0
-; GFX9: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9: s_setpc_b64
define <2 x i16> @load_local_lo_v2i16_reglo(i16 addrspace(3)* %in, i16 %reg) #0 {
+; GFX900-LABEL: load_local_lo_v2i16_reglo:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: ds_read_u16 v0, v0
+; GFX900-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX900-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_local_lo_v2i16_reglo:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: ds_read_u16 v0, v0
+; GFX906-NEXT: s_waitcnt lgkmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX906-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_local_lo_v2i16_reglo:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_mov_b32 m0, -1
+; GFX803-NEXT: ds_read_u16 v0, v0
+; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX803-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load i16, i16 addrspace(3)* %in
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 1
@@ -31,14 +67,40 @@ entry:
}
; Show that we get reasonable regalloc without physreg constraints.
-; GCN-LABEL: {{^}}load_local_lo_v2i16_reglo_vreg:
-; GCN: s_waitcnt
-; GCN: ds_read_u16 v0, v0
-; GCN: s_waitcnt
-; GFX9: v_and_b32_e32 v0, 0xffff, v0
-; GFX9: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9: global_store_dword v
define void @load_local_lo_v2i16_reglo_vreg(i16 addrspace(3)* %in, i16 %reg) #0 {
+; GFX900-LABEL: load_local_lo_v2i16_reglo_vreg:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: ds_read_u16 v0, v0
+; GFX900-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX900-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX900-NEXT: global_store_dword v[0:1], v0, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_local_lo_v2i16_reglo_vreg:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: ds_read_u16 v0, v0
+; GFX906-NEXT: s_waitcnt lgkmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX906-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_local_lo_v2i16_reglo_vreg:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_mov_b32 m0, -1
+; GFX803-NEXT: ds_read_u16 v0, v0
+; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX803-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load i16, i16 addrspace(3)* %in
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 1
@@ -47,48 +109,104 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_local_lo_v2i16_zerolo:
-; GCN: s_waitcnt
-; GFX900-NEXT: v_mov_b32_e32 v1, 0
-; GFX900-NEXT: ds_read_u16_d16 v1, v0
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: v_mov_b32_e32 v0, v1
-; GFX900-NEXT: s_setpc_b64
-
-; NO-D16-HI: ds_read_u16 v
define <2 x i16> @load_local_lo_v2i16_zerolo(i16 addrspace(3)* %in) #0 {
+; GFX900-LABEL: load_local_lo_v2i16_zerolo:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-NEXT: ds_read_u16_d16 v1, v0
+; GFX900-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-NEXT: v_mov_b32_e32 v0, v1
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_local_lo_v2i16_zerolo:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: ds_read_u16 v0, v0
+; GFX906-NEXT: s_waitcnt lgkmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_local_lo_v2i16_zerolo:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_mov_b32 m0, -1
+; GFX803-NEXT: ds_read_u16 v0, v0
+; GFX803-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load i16, i16 addrspace(3)* %in
%build = insertelement <2 x i16> zeroinitializer, i16 %load, i32 0
ret <2 x i16> %build
}
-; GCN-LABEL: {{^}}load_local_lo_v2f16_fpimm:
-; GCN: s_waitcnt
-; GFX900-NEXT: v_mov_b32_e32 v1, 2.0
-; GFX900-NEXT: ds_read_u16_d16 v1, v0
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: v_mov_b32_e32 v0, v1
-; GFX900-NEXT: s_setpc_b64
-
-; NO-D16-HI: ds_read_u16 v
define <2 x half> @load_local_lo_v2f16_fpimm(half addrspace(3)* %in) #0 {
+; GFX900-LABEL: load_local_lo_v2f16_fpimm:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_mov_b32_e32 v1, 2.0
+; GFX900-NEXT: ds_read_u16_d16 v1, v0
+; GFX900-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-NEXT: v_mov_b32_e32 v0, v1
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_local_lo_v2f16_fpimm:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: ds_read_u16 v0, v0
+; GFX906-NEXT: s_movk_i32 s4, 0x4000
+; GFX906-NEXT: s_waitcnt lgkmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX906-NEXT: v_lshl_or_b32 v0, s4, 16, v0
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_local_lo_v2f16_fpimm:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_mov_b32 m0, -1
+; GFX803-NEXT: ds_read_u16 v0, v0
+; GFX803-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-NEXT: v_or_b32_e32 v0, 2.0, v0
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load half, half addrspace(3)* %in
%build = insertelement <2 x half> <half 0.0, half 2.0>, half %load, i32 0
ret <2 x half> %build
}
-; GCN-LABEL: {{^}}load_local_lo_v2f16_reghi_vreg:
-; GCN: s_waitcnt
-; GFX900-NEXT: ds_read_u16_d16 v1, v0
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword v[0:1], v1, off{{$}}
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; NO-D16-HI: ds_read_u16 v
define void @load_local_lo_v2f16_reghi_vreg(half addrspace(3)* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_local_lo_v2f16_reghi_vreg:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: ds_read_u16_d16 v1, v0
+; GFX900-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v1, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_local_lo_v2f16_reghi_vreg:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: ds_read_u16 v0, v0
+; GFX906-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX906-NEXT: s_waitcnt lgkmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX906-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_local_lo_v2f16_reghi_vreg:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_mov_b32 m0, -1
+; GFX803-NEXT: ds_read_u16 v0, v0
+; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX803-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x half>
%load = load half, half addrspace(3)* %in
@@ -96,15 +214,41 @@ entry:
store <2 x half> %build1, <2 x half> addrspace(1)* undef
ret void
}
-; GCN-LABEL: {{^}}load_local_lo_v2f16_reglo_vreg:
-; GFX900: ds_read_u16 v
-; GFX900: v_and_b32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}}
-; GFX900: v_lshl_or_b32 v{{[0-9]+}}, v{{[0-9]+}}, 16, v{{[0-9]+}}
-; GFX900: global_store_dword
-
-; NO-D16-HI: ds_read_u16 v
define void @load_local_lo_v2f16_reglo_vreg(half addrspace(3)* %in, half %reg) #0 {
+; GFX900-LABEL: load_local_lo_v2f16_reglo_vreg:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: ds_read_u16 v0, v0
+; GFX900-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX900-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX900-NEXT: global_store_dword v[0:1], v0, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_local_lo_v2f16_reglo_vreg:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: ds_read_u16 v0, v0
+; GFX906-NEXT: s_waitcnt lgkmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX906-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_local_lo_v2f16_reglo_vreg:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_mov_b32 m0, -1
+; GFX803-NEXT: ds_read_u16 v0, v0
+; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX803-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load half, half addrspace(3)* %in
%build0 = insertelement <2 x half> undef, half %reg, i32 1
@@ -113,16 +257,39 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_local_lo_v2i16_reghi_vreg_zexti8:
-; GCN: s_waitcnt
-; GFX900-NEXT: ds_read_u8_d16 v1, v0
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword v[0:1], v1, off{{$}}
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; NO-D16-HI: ds_read_u8 v
define void @load_local_lo_v2i16_reghi_vreg_zexti8(i8 addrspace(3)* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_local_lo_v2i16_reghi_vreg_zexti8:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: ds_read_u8_d16 v1, v0
+; GFX900-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v1, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_local_lo_v2i16_reghi_vreg_zexti8:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: ds_read_u8 v0, v0
+; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
+; GFX906-NEXT: s_waitcnt lgkmcnt(0)
+; GFX906-NEXT: v_bfi_b32 v0, v2, v0, v1
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_local_lo_v2i16_reghi_vreg_zexti8:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_mov_b32 m0, -1
+; GFX803-NEXT: ds_read_u8 v0, v0
+; GFX803-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX803-NEXT: s_mov_b32 s4, 0x5040c00
+; GFX803-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-NEXT: v_perm_b32 v0, v1, v0, s4
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x i16>
%load = load i8, i8 addrspace(3)* %in
@@ -132,15 +299,40 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_local_lo_v2i16_reglo_vreg_zexti8:
-; GCN: s_waitcnt
-; GFX900: ds_read_u8 v
-; GFX900: global_store_dword
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; NO-D16-HI: ds_read_u8 v
define void @load_local_lo_v2i16_reglo_vreg_zexti8(i8 addrspace(3)* %in, i16 %reg) #0 {
+; GFX900-LABEL: load_local_lo_v2i16_reglo_vreg_zexti8:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: ds_read_u8 v0, v0
+; GFX900-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX900-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX900-NEXT: global_store_dword v[0:1], v0, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_local_lo_v2i16_reglo_vreg_zexti8:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: ds_read_u8 v0, v0
+; GFX906-NEXT: s_waitcnt lgkmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX906-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_local_lo_v2i16_reglo_vreg_zexti8:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_mov_b32 m0, -1
+; GFX803-NEXT: ds_read_u8 v0, v0
+; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX803-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load i8, i8 addrspace(3)* %in
%ext = zext i8 %load to i16
@@ -150,16 +342,38 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_local_lo_v2i16_reghi_vreg_sexti8:
-; GCN: s_waitcnt
-; GFX900-NEXT: ds_read_i8_d16 v1, v0
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword v[0:1], v1, off{{$}}
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; NO-D16-HI: ds_read_i8 v
define void @load_local_lo_v2i16_reghi_vreg_sexti8(i8 addrspace(3)* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_local_lo_v2i16_reghi_vreg_sexti8:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: ds_read_i8_d16 v1, v0
+; GFX900-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v1, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_local_lo_v2i16_reghi_vreg_sexti8:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: ds_read_i8 v0, v0
+; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
+; GFX906-NEXT: s_waitcnt lgkmcnt(0)
+; GFX906-NEXT: v_bfi_b32 v0, v2, v0, v1
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_local_lo_v2i16_reghi_vreg_sexti8:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_mov_b32 m0, -1
+; GFX803-NEXT: ds_read_i8 v0, v0
+; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX803-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x i16>
%load = load i8, i8 addrspace(3)* %in
@@ -169,14 +383,40 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_local_lo_v2i16_reglo_vreg_sexti8:
-; GCN: s_waitcnt
-; GFX900: ds_read_i8 v
-; GFX900: v_and_b32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}}
-; GFX900: v_lshl_or_b32 v{{[0-9]+}}, v{{[0-9]+}}, 16, v{{[0-9]+}}
-
-; NO-D16-HI: ds_read_i8 v
define void @load_local_lo_v2i16_reglo_vreg_sexti8(i8 addrspace(3)* %in, i16 %reg) #0 {
+; GFX900-LABEL: load_local_lo_v2i16_reglo_vreg_sexti8:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: ds_read_i8 v0, v0
+; GFX900-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX900-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX900-NEXT: global_store_dword v[0:1], v0, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_local_lo_v2i16_reglo_vreg_sexti8:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: ds_read_i8 v0, v0
+; GFX906-NEXT: s_waitcnt lgkmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX906-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_local_lo_v2i16_reglo_vreg_sexti8:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_mov_b32 m0, -1
+; GFX803-NEXT: ds_read_i8 v0, v0
+; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX803-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load i8, i8 addrspace(3)* %in
%ext = sext i8 %load to i16
@@ -186,15 +426,40 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_local_lo_v2f16_reglo_vreg_zexti8:
-; GCN: s_waitcnt
-; GFX900: ds_read_u8 v
-; GFX900: global_store_dword
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; NO-D16-HI: ds_read_u8 v
define void @load_local_lo_v2f16_reglo_vreg_zexti8(i8 addrspace(3)* %in, half %reg) #0 {
+; GFX900-LABEL: load_local_lo_v2f16_reglo_vreg_zexti8:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: ds_read_u8 v0, v0
+; GFX900-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX900-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX900-NEXT: global_store_dword v[0:1], v0, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_local_lo_v2f16_reglo_vreg_zexti8:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: ds_read_u8 v0, v0
+; GFX906-NEXT: s_waitcnt lgkmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX906-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_local_lo_v2f16_reglo_vreg_zexti8:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_mov_b32 m0, -1
+; GFX803-NEXT: ds_read_u8 v0, v0
+; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX803-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load i8, i8 addrspace(3)* %in
%ext = zext i8 %load to i16
@@ -205,14 +470,40 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_local_lo_v2f16_reglo_vreg_sexti8:
-; GCN: s_waitcnt
-; GFX900: ds_read_i8 v
-; GFX900: v_and_b32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}}
-; GFX900: v_lshl_or_b32 v{{[0-9]+}}, v{{[0-9]+}}, 16, v{{[0-9]+}}
-
-; NO-D16-HI: ds_read_i8 v
define void @load_local_lo_v2f16_reglo_vreg_sexti8(i8 addrspace(3)* %in, half %reg) #0 {
+; GFX900-LABEL: load_local_lo_v2f16_reglo_vreg_sexti8:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: ds_read_i8 v0, v0
+; GFX900-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX900-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX900-NEXT: global_store_dword v[0:1], v0, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_local_lo_v2f16_reglo_vreg_sexti8:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: ds_read_i8 v0, v0
+; GFX906-NEXT: s_waitcnt lgkmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX906-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_local_lo_v2f16_reglo_vreg_sexti8:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_mov_b32 m0, -1
+; GFX803-NEXT: ds_read_i8 v0, v0
+; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX803-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load i8, i8 addrspace(3)* %in
%ext = sext i8 %load to i16
@@ -223,20 +514,46 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_local_lo_v2i16_reghi_vreg_multi_use_lo:
-; GFX900: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900: ds_read_u16 v0, v0
-; GFX900: v_mov_b32_e32 v3, 0
-; GFX900: v_mov_b32_e32 v2, 0xffff
-; GFX900: s_waitcnt lgkmcnt(0)
-; GFX900: ds_write_b16 v3, v0
-; GFX900: v_bfi_b32 v0, v2, v0, v1
-; GFX900: global_store_dword v[0:1], v0, off
-; GFX900: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX900: s_setpc_b64 s[30:31]
-
-; NO-D16-HI: ds_read_u16 v
define void @load_local_lo_v2i16_reghi_vreg_multi_use_lo(i16 addrspace(3)* %in, <2 x i16> %reg) #0 {
+; GFX900-LABEL: load_local_lo_v2i16_reghi_vreg_multi_use_lo:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: ds_read_u16 v0, v0
+; GFX900-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-NEXT: v_mov_b32_e32 v2, 0xffff
+; GFX900-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-NEXT: ds_write_b16 v3, v0
+; GFX900-NEXT: v_bfi_b32 v0, v2, v0, v1
+; GFX900-NEXT: global_store_dword v[0:1], v0, off
+; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_local_lo_v2i16_reghi_vreg_multi_use_lo:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: ds_read_u16 v0, v0
+; GFX906-NEXT: v_mov_b32_e32 v3, 0
+; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
+; GFX906-NEXT: s_waitcnt lgkmcnt(0)
+; GFX906-NEXT: ds_write_b16 v3, v0
+; GFX906-NEXT: v_bfi_b32 v0, v2, v0, v1
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_local_lo_v2i16_reghi_vreg_multi_use_lo:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_mov_b32 m0, -1
+; GFX803-NEXT: v_mov_b32_e32 v2, 0
+; GFX803-NEXT: ds_read_u16 v0, v0
+; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX803-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-NEXT: ds_write_b16 v2, v0
+; GFX803-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load i16, i16 addrspace(3)* %in
%elt1 = extractelement <2 x i16> %reg, i32 1
@@ -246,19 +563,47 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_local_lo_v2i16_reghi_vreg_multi_use_hi:
-; GFX900: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900: v_lshrrev_b32_e32 v2, 16, v1
-; GFX900: ds_read_u16_d16 v1, v0
-; GFX900: v_mov_b32_e32 v0, 0
-; GFX900: ds_write_b16 v0, v2
-; GFX900: s_waitcnt lgkmcnt(1)
-; GFX900: global_store_dword v[0:1], v1, off
-; GFX900: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX900: s_setpc_b64 s[30:31]
-
-; NO-D16-HI: ds_read_u16 v
define void @load_local_lo_v2i16_reghi_vreg_multi_use_hi(i16 addrspace(3)* %in, <2 x i16> %reg) #0 {
+; GFX900-LABEL: load_local_lo_v2i16_reghi_vreg_multi_use_hi:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_lshrrev_b32_e32 v2, 16, v1
+; GFX900-NEXT: ds_read_u16_d16 v1, v0
+; GFX900-NEXT: v_mov_b32_e32 v0, 0
+; GFX900-NEXT: ds_write_b16 v0, v2
+; GFX900-NEXT: s_waitcnt lgkmcnt(1)
+; GFX900-NEXT: global_store_dword v[0:1], v1, off
+; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_local_lo_v2i16_reghi_vreg_multi_use_hi:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: ds_read_u16 v0, v0
+; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
+; GFX906-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX906-NEXT: v_mov_b32_e32 v4, 0
+; GFX906-NEXT: ds_write_b16 v4, v3
+; GFX906-NEXT: s_waitcnt lgkmcnt(1)
+; GFX906-NEXT: v_bfi_b32 v0, v2, v0, v1
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_local_lo_v2i16_reghi_vreg_multi_use_hi:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_mov_b32 m0, -1
+; GFX803-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX803-NEXT: v_mov_b32_e32 v3, 0
+; GFX803-NEXT: ds_read_u16 v0, v0
+; GFX803-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX803-NEXT: ds_write_b16 v3, v1
+; GFX803-NEXT: s_waitcnt lgkmcnt(1)
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load i16, i16 addrspace(3)* %in
%elt1 = extractelement <2 x i16> %reg, i32 1
@@ -268,21 +613,49 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_local_lo_v2i16_reghi_vreg_multi_use_lohi:
-; GFX900: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900: ds_read_u16 v0, v0
-; GFX900: v_lshrrev_b32_e32 v[[A_F16:[0-9]+]], 16, v1
-; GFX900: v_mov_b32_e32 v[[A_F32:[0-9]+]], 0xffff
-; GFX900: s_waitcnt lgkmcnt(0)
-; GFX900: ds_write_b16 v2, v0
-; GFX900: ds_write_b16 v3, v[[A_F16]]
-; GFX900: v_bfi_b32 v0, v[[A_F32]], v0, v1
-; GFX900: global_store_dword v[0:1], v0, off
-; GFX900: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX900: s_setpc_b64 s[30:31]
-
-; NO-D16-HI: ds_read_u16 v
define void @load_local_lo_v2i16_reghi_vreg_multi_use_lohi(i16 addrspace(3)* noalias %in, <2 x i16> %reg, i16 addrspace(3)* noalias %out0, i16 addrspace(3)* noalias %out1) #0 {
+; GFX900-LABEL: load_local_lo_v2i16_reghi_vreg_multi_use_lohi:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: ds_read_u16 v0, v0
+; GFX900-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX900-NEXT: v_mov_b32_e32 v4, 0xffff
+; GFX900-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-NEXT: ds_write_b16 v2, v0
+; GFX900-NEXT: ds_write_b16 v3, v5
+; GFX900-NEXT: v_bfi_b32 v0, v4, v0, v1
+; GFX900-NEXT: global_store_dword v[0:1], v0, off
+; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_local_lo_v2i16_reghi_vreg_multi_use_lohi:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: ds_read_u16 v0, v0
+; GFX906-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX906-NEXT: v_mov_b32_e32 v4, 0xffff
+; GFX906-NEXT: s_waitcnt lgkmcnt(0)
+; GFX906-NEXT: ds_write_b16 v2, v0
+; GFX906-NEXT: ds_write_b16 v3, v5
+; GFX906-NEXT: v_bfi_b32 v0, v4, v0, v1
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_local_lo_v2i16_reghi_vreg_multi_use_lohi:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_mov_b32 m0, -1
+; GFX803-NEXT: ds_read_u16 v0, v0
+; GFX803-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX803-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX803-NEXT: s_waitcnt lgkmcnt(0)
+; GFX803-NEXT: ds_write_b16 v2, v0
+; GFX803-NEXT: ds_write_b16 v3, v1
+; GFX803-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%load = load i16, i16 addrspace(3)* %in
%elt1 = extractelement <2 x i16> %reg, i32 1
@@ -293,17 +666,39 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_global_lo_v2i16_reglo_vreg:
-; GCN: s_waitcnt
-; GFX900-NEXT: global_load_short_d16 v2, v[0:1], off offset:-4094
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; GFX906: global_load_ushort v0, v[0:1], off offset:-4094
-; GFX906: v_bfi_b32
define void @load_global_lo_v2i16_reglo_vreg(i16 addrspace(1)* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_global_lo_v2i16_reglo_vreg:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: global_load_short_d16 v2, v[0:1], off offset:-4094
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v2, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_global_lo_v2i16_reglo_vreg:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: global_load_ushort v0, v[0:1], off offset:-4094
+; GFX906-NEXT: v_mov_b32_e32 v1, 0xffff
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_bfi_b32 v0, v1, v0, v2
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_global_lo_v2i16_reglo_vreg:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_add_u32_e32 v0, vcc, 0xfffff002, v0
+; GFX803-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
+; GFX803-NEXT: flat_load_ushort v0, v[0:1]
+; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x i16>
%gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i64 -2047
@@ -313,21 +708,40 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_global_lo_v2f16_reglo_vreg:
-; GCN: s_waitcnt
-; GFX900-NEXT: global_load_short_d16 v2, v[0:1], off offset:-4094
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; GFX906: global_load_ushort v0, v[0:1], off offset:-4094
-; GFX906: v_lshrrev_b32
-; GFX906: v_and_b32_e32
-; GFX906: v_lshl_or_b32
-
-; GFX803: flat_load_ushort
define void @load_global_lo_v2f16_reglo_vreg(half addrspace(1)* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_global_lo_v2f16_reglo_vreg:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: global_load_short_d16 v2, v[0:1], off offset:-4094
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v2, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_global_lo_v2f16_reglo_vreg:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: global_load_ushort v0, v[0:1], off offset:-4094
+; GFX906-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX906-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_global_lo_v2f16_reglo_vreg:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_add_u32_e32 v0, vcc, 0xfffff002, v0
+; GFX803-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
+; GFX803-NEXT: flat_load_ushort v0, v[0:1]
+; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x half>
%gep = getelementptr inbounds half, half addrspace(1)* %in, i64 -2047
@@ -337,19 +751,40 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_global_lo_v2i16_reglo_vreg_zexti8:
-; GCN: s_waitcnt
-; GFX900-NEXT: global_load_ubyte_d16 v2, v[0:1], off offset:-4095
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; GFX906: global_load_ubyte v0, v[0:1], off offset:-4095
-; GFX906: v_bfi_b32
-
-; GFX803: flat_load_ubyte
define void @load_global_lo_v2i16_reglo_vreg_zexti8(i8 addrspace(1)* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_global_lo_v2i16_reglo_vreg_zexti8:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: global_load_ubyte_d16 v2, v[0:1], off offset:-4095
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v2, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_global_lo_v2i16_reglo_vreg_zexti8:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: global_load_ubyte v0, v[0:1], off offset:-4095
+; GFX906-NEXT: v_mov_b32_e32 v1, 0xffff
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_bfi_b32 v0, v1, v0, v2
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_global_lo_v2i16_reglo_vreg_zexti8:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_add_u32_e32 v0, vcc, 0xfffff001, v0
+; GFX803-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
+; GFX803-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX803-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX803-NEXT: s_mov_b32 s4, 0x5040c00
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_perm_b32 v0, v1, v0, s4
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x i16>
%gep = getelementptr inbounds i8, i8 addrspace(1)* %in, i64 -4095
@@ -360,19 +795,39 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_global_lo_v2i16_reglo_vreg_sexti8:
-; GCN: s_waitcnt
-; GFX900-NEXT: global_load_sbyte_d16 v2, v[0:1], off offset:-4095
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; GFX906: global_load_sbyte v0, v[0:1], off offset:-4095
-; GFX906: v_bfi_b32
-
-; GFX803: flat_load_sbyte
define void @load_global_lo_v2i16_reglo_vreg_sexti8(i8 addrspace(1)* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_global_lo_v2i16_reglo_vreg_sexti8:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: global_load_sbyte_d16 v2, v[0:1], off offset:-4095
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v2, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_global_lo_v2i16_reglo_vreg_sexti8:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: global_load_sbyte v0, v[0:1], off offset:-4095
+; GFX906-NEXT: v_mov_b32_e32 v1, 0xffff
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_bfi_b32 v0, v1, v0, v2
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_global_lo_v2i16_reglo_vreg_sexti8:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_add_u32_e32 v0, vcc, 0xfffff001, v0
+; GFX803-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
+; GFX803-NEXT: flat_load_sbyte v0, v[0:1]
+; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x i16>
%gep = getelementptr inbounds i8, i8 addrspace(1)* %in, i64 -4095
@@ -383,20 +838,41 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_global_lo_v2f16_reglo_vreg_zexti8:
-; GCN: s_waitcnt
-; GFX900-NEXT: global_load_ubyte_d16 v2, v[0:1], off offset:-4095
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; GFX906: global_load_ubyte v0, v[0:1], off offset:-4095
-; GFX906: v_and_b32_e32
-; GFX906: v_lshl_or_b32
-
-; GFX803: flat_load_ubyte
define void @load_global_lo_v2f16_reglo_vreg_zexti8(i8 addrspace(1)* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_global_lo_v2f16_reglo_vreg_zexti8:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: global_load_ubyte_d16 v2, v[0:1], off offset:-4095
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v2, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_global_lo_v2f16_reglo_vreg_zexti8:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: global_load_ubyte v0, v[0:1], off offset:-4095
+; GFX906-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX906-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_global_lo_v2f16_reglo_vreg_zexti8:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_add_u32_e32 v0, vcc, 0xfffff001, v0
+; GFX803-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
+; GFX803-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX803-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX803-NEXT: s_mov_b32 s4, 0x5040c00
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_perm_b32 v0, v1, v0, s4
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x half>
%gep = getelementptr inbounds i8, i8 addrspace(1)* %in, i64 -4095
@@ -408,21 +884,40 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_global_lo_v2f16_reglo_vreg_sexti8:
-; GCN: s_waitcnt
-; GFX900-NEXT: global_load_sbyte_d16 v2, v[0:1], off offset:-4095
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; GFX906: global_load_sbyte v0, v[0:1], off offset:-4095
-; GFX906: v_lshrrev_b32
-; GFX906: v_and_b32
-; GFX906: v_lshl_or_b32
-
-; GFX803: flat_load_sbyte
define void @load_global_lo_v2f16_reglo_vreg_sexti8(i8 addrspace(1)* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_global_lo_v2f16_reglo_vreg_sexti8:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: global_load_sbyte_d16 v2, v[0:1], off offset:-4095
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v2, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_global_lo_v2f16_reglo_vreg_sexti8:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: global_load_sbyte v0, v[0:1], off offset:-4095
+; GFX906-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX906-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_global_lo_v2f16_reglo_vreg_sexti8:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_add_u32_e32 v0, vcc, 0xfffff001, v0
+; GFX803-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
+; GFX803-NEXT: flat_load_sbyte v0, v[0:1]
+; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x half>
%gep = getelementptr inbounds i8, i8 addrspace(1)* %in, i64 -4095
@@ -434,22 +929,37 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_flat_lo_v2i16_reghi_vreg:
-; GCN: s_waitcnt
-; GFX900-NEXT: flat_load_short_d16 v2, v[0:1]
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword v[0:1], v2
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; GFX803: flat_load_ushort v{{[0-9]+}}
-; GFX803: v_or_b32_e32
-
-; GFX906: flat_load_ushort [[LOAD:v[0-9]+]]
-; GFX906: v_mov_b32_e32 [[MASK:v[0-9]+]], 0xffff{{$}}
-; GFX906: v_bfi_b32 v{{[0-9]+}}, [[MASK]], [[LOAD]], v2
-; GFX906: global_store_dword
define void @load_flat_lo_v2i16_reghi_vreg(i16* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_flat_lo_v2i16_reghi_vreg:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: flat_load_short_d16 v2, v[0:1]
+; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v2, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_flat_lo_v2i16_reghi_vreg:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: flat_load_ushort v0, v[0:1]
+; GFX906-NEXT: v_mov_b32_e32 v1, 0xffff
+; GFX906-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_bfi_b32 v0, v1, v0, v2
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_flat_lo_v2i16_reghi_vreg:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: flat_load_ushort v0, v[0:1]
+; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x i16>
%load = load i16, i16* %in
@@ -458,24 +968,39 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_flat_lo_v2f16_reghi_vreg:
-; GCN: s_waitcnt
-; GFX900-NEXT: flat_load_short_d16 v2, v[0:1]
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword v[0:1], v2
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; GFX803: flat_load_ushort v{{[0-9]+}}
-; GFX803: v_or_b32_e32
-
-; FIXME: and should be removable
-; GFX906: flat_load_ushort [[LOAD:v[0-9]+]]
-; GFX906: v_lshrrev_b32_e32 [[SHR:v[0-9]+]], 16, v2
-; GFX906: v_and_b32_e32 [[AND:v[0-9]+]], 0xffff, [[LOAD]]
-; GFX906: v_lshl_or_b32 [[LSHL_OR:v[0-9]+]], [[SHR]], 16, [[AND]]
-; GFX906: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[LSHL_OR]]
define void @load_flat_lo_v2f16_reghi_vreg(half* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_flat_lo_v2f16_reghi_vreg:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: flat_load_short_d16 v2, v[0:1]
+; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v2, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_flat_lo_v2f16_reghi_vreg:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: flat_load_ushort v0, v[0:1]
+; GFX906-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX906-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX906-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_flat_lo_v2f16_reghi_vreg:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: flat_load_ushort v0, v[0:1]
+; FIXME: and should be removable
+; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x half>
%load = load half, half* %in
@@ -484,23 +1009,38 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_flat_lo_v2i16_reglo_vreg_zexti8:
-; GCN: s_waitcnt
-; GFX900-NEXT: flat_load_ubyte_d16 v2, v[0:1]
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword v[0:1], v2
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; GFX803: flat_load_ubyte [[LO:v[0-9]+]]
-; GFX803: v_lshrrev_b32_e32 [[HI:v[0-9]+]], 16, v2
-; GFX803: s_mov_b32 [[MASK:s[0-9]+]], 0x5040c00
-; GFX803: v_perm_b32 [[RES:v[0-9]+]], [[HI]], [[LO]], [[MASK]]
-; GFX803: flat_store_dword v[0:1], [[RES]]
-
-; GFX906: flat_load_ubyte
-; GFX906: v_bfi_b32
define void @load_flat_lo_v2i16_reglo_vreg_zexti8(i8* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_flat_lo_v2i16_reglo_vreg_zexti8:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: flat_load_ubyte_d16 v2, v[0:1]
+; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v2, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_flat_lo_v2i16_reglo_vreg_zexti8:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX906-NEXT: v_mov_b32_e32 v1, 0xffff
+; GFX906-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_bfi_b32 v0, v1, v0, v2
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_flat_lo_v2i16_reglo_vreg_zexti8:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX803-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX803-NEXT: s_mov_b32 s4, 0x5040c00
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_perm_b32 v0, v1, v0, s4
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x i16>
%load = load i8, i8* %in
@@ -510,20 +1050,37 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_flat_lo_v2i16_reglo_vreg_sexti8:
-; GCN: s_waitcnt
-; GFX900-NEXT: flat_load_sbyte_d16 v2, v[0:1]
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword v[0:1], v2
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; GFX803: flat_load_sbyte v{{[0-9]+}}
-; GFX803: v_or_b32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-
-; GFX906: flat_load_sbyte
-; GFX906: v_bfi_b32
define void @load_flat_lo_v2i16_reglo_vreg_sexti8(i8* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_flat_lo_v2i16_reglo_vreg_sexti8:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: flat_load_sbyte_d16 v2, v[0:1]
+; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v2, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_flat_lo_v2i16_reglo_vreg_sexti8:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: flat_load_sbyte v0, v[0:1]
+; GFX906-NEXT: v_mov_b32_e32 v1, 0xffff
+; GFX906-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_bfi_b32 v0, v1, v0, v2
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_flat_lo_v2i16_reglo_vreg_sexti8:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: flat_load_sbyte v0, v[0:1]
+; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x i16>
%load = load i8, i8* %in
@@ -533,25 +1090,39 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_flat_lo_v2f16_reglo_vreg_zexti8:
-; GCN: s_waitcnt
-; GFX900-NEXT: flat_load_ubyte_d16 v2, v[0:1]
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword v[0:1], v2
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; GFX803: flat_load_ubyte [[LO:v[0-9]+]]
-; GFX803: v_lshrrev_b32_e32 [[HI:v[0-9]+]], 16, v2
-; GFX803: s_mov_b32 [[MASK:s[0-9]+]], 0x5040c00
-; GFX803: v_perm_b32 [[RES:v[0-9]+]], [[HI]], [[LO]], [[MASK]]
-; GFX803: flat_store_dword v[0:1], [[RES]]
-
-; GFX906: flat_load_ubyte
-; GFX906: v_lshrrev_b32
-; GFX906: v_and_b32
-; GFX906: v_lshl_or_b32
define void @load_flat_lo_v2f16_reglo_vreg_zexti8(i8* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_flat_lo_v2f16_reglo_vreg_zexti8:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: flat_load_ubyte_d16 v2, v[0:1]
+; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v2, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_flat_lo_v2f16_reglo_vreg_zexti8:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX906-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX906-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX906-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_flat_lo_v2f16_reglo_vreg_zexti8:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX803-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX803-NEXT: s_mov_b32 s4, 0x5040c00
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_perm_b32 v0, v1, v0, s4
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x half>
%load = load i8, i8* %in
@@ -562,22 +1133,38 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_flat_lo_v2f16_reglo_vreg_sexti8:
-; GCN: s_waitcnt
-; GFX900-NEXT: flat_load_sbyte_d16 v2, v[0:1]
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword v[0:1], v2
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; GFX803: flat_load_sbyte v{{[0-9]+}}
-; GFX803: v_or_b32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-
-; GFX906: flat_load_sbyte
-; GFX906: v_lshrrev_b32
-; GFX906: v_and_b32
-; GFX906: v_lshl_or_b32
define void @load_flat_lo_v2f16_reglo_vreg_sexti8(i8* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_flat_lo_v2f16_reglo_vreg_sexti8:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: flat_load_sbyte_d16 v2, v[0:1]
+; GFX900-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v2, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_flat_lo_v2f16_reglo_vreg_sexti8:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: flat_load_sbyte v0, v[0:1]
+; GFX906-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX906-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX906-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_flat_lo_v2f16_reglo_vreg_sexti8:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: flat_load_sbyte v0, v[0:1]
+; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x half>
%load = load i8, i8* %in
@@ -588,16 +1175,37 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg:
-; GCN: s_waitcnt
-; GFX900: buffer_load_short_d16 v0, off, s[0:3], s32 offset:4094{{$}}
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; NO-D16-HI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s32 offset:4094{{$}}
define void @load_private_lo_v2i16_reglo_vreg(i16 addrspace(5)* byval %in, i32 %reg) #0 {
+; GFX900-LABEL: load_private_lo_v2i16_reglo_vreg:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: buffer_load_short_d16 v0, off, s[0:3], s32 offset:4094
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v0, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_private_lo_v2i16_reglo_vreg:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:4094
+; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_bfi_b32 v0, v2, v1, v0
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:4094
+; GFX803-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX803-NEXT: s_waitcnt vmcnt(0)
+; GFX803-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x i16>
%gep = getelementptr inbounds i16, i16 addrspace(5)* %in, i64 2047
@@ -607,19 +1215,39 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_private_lo_v2i16_reghi_vreg:
-; GCN: s_waitcnt
-; GFX900: buffer_load_ushort v1, off, s[0:3], s32 offset:4094{{$}}
-; GFX900-NEXT: s_waitcnt
-; GFX900: v_and_b32
-; GFX900: v_lshl_or_b32
-
-; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; NO-D16-HI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s32 offset:4094{{$}}
define void @load_private_lo_v2i16_reghi_vreg(i16 addrspace(5)* byval %in, i16 %reg) #0 {
+; GFX900-LABEL: load_private_lo_v2i16_reghi_vreg:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:4094
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX900-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX900-NEXT: global_store_dword v[0:1], v0, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_private_lo_v2i16_reghi_vreg:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:4094
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX906-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_private_lo_v2i16_reghi_vreg:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:4094
+; GFX803-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX803-NEXT: s_waitcnt vmcnt(0)
+; GFX803-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%gep = getelementptr inbounds i16, i16 addrspace(5)* %in, i64 2047
%load = load i16, i16 addrspace(5)* %gep
@@ -629,16 +1257,38 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_private_lo_v2f16_reglo_vreg:
-; GCN: s_waitcnt
-; GFX900: buffer_load_short_d16 v0, off, s[0:3], s32 offset:4094{{$}}
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; NO-D16-HI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s32 offset:4094{{$}}
define void @load_private_lo_v2f16_reglo_vreg(half addrspace(5)* byval %in, i32 %reg) #0 {
+; GFX900-LABEL: load_private_lo_v2f16_reglo_vreg:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: buffer_load_short_d16 v0, off, s[0:3], s32 offset:4094
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v0, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_private_lo_v2f16_reglo_vreg:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:4094
+; GFX906-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX906-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_private_lo_v2f16_reglo_vreg:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:4094
+; GFX803-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX803-NEXT: s_waitcnt vmcnt(0)
+; GFX803-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x half>
%gep = getelementptr inbounds half, half addrspace(5)* %in, i64 2047
@@ -648,16 +1298,37 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_nooff:
-; GCN: s_waitcnt
-; GFX900-NEXT: buffer_load_short_d16 v1, off, s[0:3], s33 offset:4094{{$}}
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; NO-D16-HI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s33 offset:4094{{$}}
define void @load_private_lo_v2i16_reglo_vreg_nooff(i16 addrspace(5)* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_private_lo_v2i16_reglo_vreg_nooff:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: buffer_load_short_d16 v1, off, s[0:3], s33 offset:4094
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v1, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_private_lo_v2i16_reglo_vreg_nooff:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: buffer_load_ushort v0, off, s[0:3], s33 offset:4094
+; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_bfi_b32 v0, v2, v0, v1
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg_nooff:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: buffer_load_ushort v0, off, s[0:3], s33 offset:4094
+; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX803-NEXT: s_waitcnt vmcnt(0)
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x i16>
%load = load volatile i16, i16 addrspace(5)* inttoptr (i32 4094 to i16 addrspace(5)*)
@@ -666,16 +1337,37 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_private_lo_v2i16_reghi_vreg_nooff:
-; GCN: s_waitcnt
-; GFX900-NEXT: buffer_load_short_d16 v1, off, s[0:3], s33 offset:4094{{$}}
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; NO-D16-HI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s33 offset:4094{{$}}
define void @load_private_lo_v2i16_reghi_vreg_nooff(i16 addrspace(5)* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_private_lo_v2i16_reghi_vreg_nooff:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: buffer_load_short_d16 v1, off, s[0:3], s33 offset:4094
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v1, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_private_lo_v2i16_reghi_vreg_nooff:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: buffer_load_ushort v0, off, s[0:3], s33 offset:4094
+; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_bfi_b32 v0, v2, v0, v1
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_private_lo_v2i16_reghi_vreg_nooff:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: buffer_load_ushort v0, off, s[0:3], s33 offset:4094
+; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX803-NEXT: s_waitcnt vmcnt(0)
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x i16>
%load = load volatile i16, i16 addrspace(5)* inttoptr (i32 4094 to i16 addrspace(5)*)
@@ -684,16 +1376,38 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_private_lo_v2f16_reglo_vreg_nooff:
-; GCN: s_waitcnt
-; GFX900-NEXT: buffer_load_short_d16 v1, off, s[0:3], s33 offset:4094{{$}}
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; NO-D16-HI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s33 offset:4094{{$}}
define void @load_private_lo_v2f16_reglo_vreg_nooff(half addrspace(5)* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_private_lo_v2f16_reglo_vreg_nooff:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: buffer_load_short_d16 v1, off, s[0:3], s33 offset:4094
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v1, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_private_lo_v2f16_reglo_vreg_nooff:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: buffer_load_ushort v0, off, s[0:3], s33 offset:4094
+; GFX906-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX906-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_private_lo_v2f16_reglo_vreg_nooff:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: buffer_load_ushort v0, off, s[0:3], s33 offset:4094
+; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX803-NEXT: s_waitcnt vmcnt(0)
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x half>
%load = load volatile half, half addrspace(5)* inttoptr (i32 4094 to half addrspace(5)*)
@@ -702,16 +1416,38 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_zexti8:
-; GCN: s_waitcnt
-; GFX900: buffer_load_ubyte_d16 v0, off, s[0:3], s32 offset:4095{{$}}
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; NO-D16-HI: buffer_load_ubyte v{{[0-9]+}}, off, s[0:3], s32 offset:4095{{$}}
define void @load_private_lo_v2i16_reglo_vreg_zexti8(i8 addrspace(5)* byval %in, i32 %reg) #0 {
+; GFX900-LABEL: load_private_lo_v2i16_reglo_vreg_zexti8:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: buffer_load_ubyte_d16 v0, off, s[0:3], s32 offset:4095
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v0, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_private_lo_v2i16_reglo_vreg_zexti8:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: buffer_load_ubyte v1, off, s[0:3], s32 offset:4095
+; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_bfi_b32 v0, v2, v1, v0
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg_zexti8:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: buffer_load_ubyte v1, off, s[0:3], s32 offset:4095
+; GFX803-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX803-NEXT: s_mov_b32 s4, 0x5040c00
+; GFX803-NEXT: s_waitcnt vmcnt(0)
+; GFX803-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x i16>
%gep = getelementptr inbounds i8, i8 addrspace(5)* %in, i64 4095
@@ -722,16 +1458,37 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_sexti8:
-; GCN: s_waitcnt
-; GFX900: buffer_load_sbyte_d16 v0, off, s[0:3], s32 offset:4095{{$}}
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; NO-D16-HI: buffer_load_sbyte v{{[0-9]+}}, off, s[0:3], s32 offset:4095{{$}}
define void @load_private_lo_v2i16_reglo_vreg_sexti8(i8 addrspace(5)* byval %in, i32 %reg) #0 {
+; GFX900-LABEL: load_private_lo_v2i16_reglo_vreg_sexti8:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: buffer_load_sbyte_d16 v0, off, s[0:3], s32 offset:4095
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v0, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_private_lo_v2i16_reglo_vreg_sexti8:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: buffer_load_sbyte v1, off, s[0:3], s32 offset:4095
+; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_bfi_b32 v0, v2, v1, v0
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg_sexti8:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: buffer_load_sbyte v1, off, s[0:3], s32 offset:4095
+; GFX803-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX803-NEXT: s_waitcnt vmcnt(0)
+; GFX803-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x i16>
%gep = getelementptr inbounds i8, i8 addrspace(5)* %in, i64 4095
@@ -742,16 +1499,38 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_nooff_zexti8:
-; GCN: s_waitcnt
-; GFX900-NEXT: buffer_load_ubyte_d16 v1, off, s[0:3], s33 offset:4094{{$}}
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; NO-D16-HI: buffer_load_ubyte v0, off, s[0:3], s33 offset:4094{{$}}
define void @load_private_lo_v2i16_reglo_vreg_nooff_zexti8(i8 addrspace(5)* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_zexti8:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: buffer_load_ubyte_d16 v1, off, s[0:3], s33 offset:4094
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v1, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_zexti8:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: buffer_load_ubyte v0, off, s[0:3], s33 offset:4094
+; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_bfi_b32 v0, v2, v0, v1
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_zexti8:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: buffer_load_ubyte v0, off, s[0:3], s33 offset:4094
+; GFX803-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX803-NEXT: s_mov_b32 s4, 0x5040c00
+; GFX803-NEXT: s_waitcnt vmcnt(0)
+; GFX803-NEXT: v_perm_b32 v0, v1, v0, s4
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x i16>
%load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*)
@@ -761,16 +1540,37 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_nooff_sexti8:
-; GCN: s_waitcnt
-; GFX900-NEXT: buffer_load_sbyte_d16 v1, off, s[0:3], s33 offset:4094{{$}}
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; NO-D16-HI: buffer_load_sbyte v0, off, s[0:3], s33 offset:4094{{$}}
define void @load_private_lo_v2i16_reglo_vreg_nooff_sexti8(i8 addrspace(5)* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_sexti8:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: buffer_load_sbyte_d16 v1, off, s[0:3], s33 offset:4094
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v1, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_sexti8:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: buffer_load_sbyte v0, off, s[0:3], s33 offset:4094
+; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_bfi_b32 v0, v2, v0, v1
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_sexti8:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: buffer_load_sbyte v0, off, s[0:3], s33 offset:4094
+; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX803-NEXT: s_waitcnt vmcnt(0)
+; GFX803-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x i16>
%load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*)
@@ -780,16 +1580,39 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_private_lo_v2f16_reglo_vreg_nooff_zexti8:
-; GCN: s_waitcnt
-; GFX900-NEXT: buffer_load_ubyte_d16 v1, off, s[0:3], s33 offset:4094{{$}}
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; NO-D16-HI: buffer_load_ubyte v0, off, s[0:3], s33 offset:4094{{$}}
define void @load_private_lo_v2f16_reglo_vreg_nooff_zexti8(i8 addrspace(5)* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_private_lo_v2f16_reglo_vreg_nooff_zexti8:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: buffer_load_ubyte_d16 v1, off, s[0:3], s33 offset:4094
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v1, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_private_lo_v2f16_reglo_vreg_nooff_zexti8:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: buffer_load_ubyte v0, off, s[0:3], s33 offset:4094
+; GFX906-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX906-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_private_lo_v2f16_reglo_vreg_nooff_zexti8:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: buffer_load_ubyte v0, off, s[0:3], s33 offset:4094
+; GFX803-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX803-NEXT: s_mov_b32 s4, 0x5040c00
+; GFX803-NEXT: s_waitcnt vmcnt(0)
+; GFX803-NEXT: v_perm_b32 v0, v1, v0, s4
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x half>
%load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*)
@@ -800,18 +1623,39 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_constant_lo_v2i16_reglo_vreg:
-; GCN: s_waitcnt
-; GFX900-NEXT: global_load_short_d16 v2, v[0:1], off offset:-4094
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; GFX803: flat_load_ushort
-
-; GFX906: global_load_ushort
define void @load_constant_lo_v2i16_reglo_vreg(i16 addrspace(4)* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_constant_lo_v2i16_reglo_vreg:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: global_load_short_d16 v2, v[0:1], off offset:-4094
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v2, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_constant_lo_v2i16_reglo_vreg:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: global_load_ushort v0, v[0:1], off offset:-4094
+; GFX906-NEXT: v_mov_b32_e32 v1, 0xffff
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_bfi_b32 v0, v1, v0, v2
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_constant_lo_v2i16_reglo_vreg:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_add_u32_e32 v0, vcc, 0xfffff002, v0
+; GFX803-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
+; GFX803-NEXT: flat_load_ushort v0, v[0:1]
+; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x i16>
%gep = getelementptr inbounds i16, i16 addrspace(4)* %in, i64 -2047
@@ -821,18 +1665,40 @@ entry:
ret void
}
-; GCN-LABEL: load_constant_lo_v2f16_reglo_vreg
-; GCN: s_waitcnt
-; GFX900-NEXT: global_load_short_d16 v2, v[0:1], off offset:-4094
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; GFX803: flat_load_ushort
-
-; GFX906: global_load_ushort
define void @load_constant_lo_v2f16_reglo_vreg(half addrspace(4)* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_constant_lo_v2f16_reglo_vreg:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: global_load_short_d16 v2, v[0:1], off offset:-4094
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v2, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_constant_lo_v2f16_reglo_vreg:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: global_load_ushort v0, v[0:1], off offset:-4094
+; GFX906-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX906-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_constant_lo_v2f16_reglo_vreg:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_add_u32_e32 v0, vcc, 0xfffff002, v0
+; GFX803-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
+; GFX803-NEXT: flat_load_ushort v0, v[0:1]
+; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x half>
%gep = getelementptr inbounds half, half addrspace(4)* %in, i64 -2047
@@ -842,20 +1708,41 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_constant_lo_v2f16_reglo_vreg_zexti8:
-; GCN: s_waitcnt
-; GFX900-NEXT: global_load_ubyte_d16 v2, v[0:1], off offset:-4095
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; GFX906: global_load_ubyte v0, v[0:1], off offset:-4095
-; GFX906: v_and_b32_e32
-; GFX906: v_lshl_or_b32
-
-; GFX803: flat_load_ubyte
define void @load_constant_lo_v2f16_reglo_vreg_zexti8(i8 addrspace(4)* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_constant_lo_v2f16_reglo_vreg_zexti8:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: global_load_ubyte_d16 v2, v[0:1], off offset:-4095
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v2, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_constant_lo_v2f16_reglo_vreg_zexti8:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: global_load_ubyte v0, v[0:1], off offset:-4095
+; GFX906-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX906-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_constant_lo_v2f16_reglo_vreg_zexti8:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_add_u32_e32 v0, vcc, 0xfffff001, v0
+; GFX803-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
+; GFX803-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX803-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX803-NEXT: s_mov_b32 s4, 0x5040c00
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_perm_b32 v0, v1, v0, s4
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x half>
%gep = getelementptr inbounds i8, i8 addrspace(4)* %in, i64 -4095
@@ -867,21 +1754,40 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_constant_lo_v2f16_reglo_vreg_sexti8:
-; GCN: s_waitcnt
-; GFX900-NEXT: global_load_sbyte_d16 v2, v[0:1], off offset:-4095
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: global_store_dword
-; GFX900-NEXT: s_waitcnt
-; GFX900-NEXT: s_setpc_b64
-
-; GFX906: global_load_sbyte v0, v[0:1], off offset:-4095
-; GFX906: v_lshrrev_b32
-; GFX906: v_and_b32
-; GFX906: v_lshl_or_b32
-
-; GFX803: flat_load_sbyte
define void @load_constant_lo_v2f16_reglo_vreg_sexti8(i8 addrspace(4)* %in, i32 %reg) #0 {
+; GFX900-LABEL: load_constant_lo_v2f16_reglo_vreg_sexti8:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: global_load_sbyte_d16 v2, v[0:1], off offset:-4095
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v2, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_constant_lo_v2f16_reglo_vreg_sexti8:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: global_load_sbyte v0, v[0:1], off offset:-4095
+; GFX906-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX906-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_constant_lo_v2f16_reglo_vreg_sexti8:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_add_u32_e32 v0, vcc, 0xfffff001, v0
+; GFX803-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc
+; GFX803-NEXT: flat_load_sbyte v0, v[0:1]
+; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%reg.bc = bitcast i32 %reg to <2 x half>
%gep = getelementptr inbounds i8, i8 addrspace(4)* %in, i64 -4095
@@ -893,12 +1799,43 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_to_offset:
-; GFX900: buffer_store_dword
-; GFX900-NEXT: buffer_load_short_d16 v0, off, s[0:3], s32 offset:4094
-
-; NO-D16-HI: buffer_load_ushort v
define void @load_private_lo_v2i16_reglo_vreg_to_offset(i32 %reg) #0 {
+; GFX900-LABEL: load_private_lo_v2i16_reglo_vreg_to_offset:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_mov_b32_e32 v1, 0x7b
+; GFX900-NEXT: buffer_store_dword v1, off, s[0:3], s32
+; GFX900-NEXT: buffer_load_short_d16 v0, off, s[0:3], s32 offset:4094
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v0, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_private_lo_v2i16_reglo_vreg_to_offset:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_mov_b32_e32 v1, 0x7b
+; GFX906-NEXT: buffer_store_dword v1, off, s[0:3], s32
+; GFX906-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:4094
+; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_bfi_b32 v0, v2, v1, v0
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg_to_offset:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_mov_b32_e32 v1, 0x7b
+; GFX803-NEXT: buffer_store_dword v1, off, s[0:3], s32
+; GFX803-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:4094
+; GFX803-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX803-NEXT: s_waitcnt vmcnt(0)
+; GFX803-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%obj0 = alloca [10 x i32], align 4, addrspace(5)
%obj1 = alloca [4096 x i16], align 2, addrspace(5)
@@ -912,12 +1849,43 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_sexti8_to_offset:
-; GFX900: buffer_store_dword
-; GFX900-NEXT: buffer_load_sbyte_d16 v0, off, s[0:3], s32 offset:4095
-
-; NO-D16-HI: buffer_load_sbyte v
define void @load_private_lo_v2i16_reglo_vreg_sexti8_to_offset(i32 %reg) #0 {
+; GFX900-LABEL: load_private_lo_v2i16_reglo_vreg_sexti8_to_offset:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_mov_b32_e32 v1, 0x7b
+; GFX900-NEXT: buffer_store_dword v1, off, s[0:3], s32
+; GFX900-NEXT: buffer_load_sbyte_d16 v0, off, s[0:3], s32 offset:4095
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v0, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_private_lo_v2i16_reglo_vreg_sexti8_to_offset:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_mov_b32_e32 v1, 0x7b
+; GFX906-NEXT: buffer_store_dword v1, off, s[0:3], s32
+; GFX906-NEXT: buffer_load_sbyte v1, off, s[0:3], s32 offset:4095
+; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_bfi_b32 v0, v2, v1, v0
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg_sexti8_to_offset:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_mov_b32_e32 v1, 0x7b
+; GFX803-NEXT: buffer_store_dword v1, off, s[0:3], s32
+; GFX803-NEXT: buffer_load_sbyte v1, off, s[0:3], s32 offset:4095
+; GFX803-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX803-NEXT: s_waitcnt vmcnt(0)
+; GFX803-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%obj0 = alloca [10 x i32], align 4, addrspace(5)
%obj1 = alloca [4096 x i8], align 2, addrspace(5)
@@ -932,12 +1900,44 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_zexti8_to_offset:
-; GFX900: buffer_store_dword
-; GFX900-NEXT: buffer_load_ubyte_d16 v0, off, s[0:3], s32 offset:4095
-
-; NO-D16-HI: buffer_load_ubyte v
define void @load_private_lo_v2i16_reglo_vreg_zexti8_to_offset(i32 %reg) #0 {
+; GFX900-LABEL: load_private_lo_v2i16_reglo_vreg_zexti8_to_offset:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_mov_b32_e32 v1, 0x7b
+; GFX900-NEXT: buffer_store_dword v1, off, s[0:3], s32
+; GFX900-NEXT: buffer_load_ubyte_d16 v0, off, s[0:3], s32 offset:4095
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v0, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_private_lo_v2i16_reglo_vreg_zexti8_to_offset:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_mov_b32_e32 v1, 0x7b
+; GFX906-NEXT: buffer_store_dword v1, off, s[0:3], s32
+; GFX906-NEXT: buffer_load_ubyte v1, off, s[0:3], s32 offset:4095
+; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_bfi_b32 v0, v2, v1, v0
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg_zexti8_to_offset:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_mov_b32_e32 v1, 0x7b
+; GFX803-NEXT: buffer_store_dword v1, off, s[0:3], s32
+; GFX803-NEXT: buffer_load_ubyte v1, off, s[0:3], s32 offset:4095
+; GFX803-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX803-NEXT: s_mov_b32 s4, 0x5040c00
+; GFX803-NEXT: s_waitcnt vmcnt(0)
+; GFX803-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%obj0 = alloca [10 x i32], align 4, addrspace(5)
%obj1 = alloca [4096 x i8], align 2, addrspace(5)
@@ -952,12 +1952,44 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_private_lo_v2f16_reglo_vreg_sexti8_to_offset:
-; GFX900: buffer_store_dword
-; GFX900-NEXT: buffer_load_sbyte_d16 v0, off, s[0:3], s32 offset:4095
-
-; NO-D16-HI: buffer_load_sbyte v
define void @load_private_lo_v2f16_reglo_vreg_sexti8_to_offset(i32 %reg) #0 {
+; GFX900-LABEL: load_private_lo_v2f16_reglo_vreg_sexti8_to_offset:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_mov_b32_e32 v1, 0x7b
+; GFX900-NEXT: buffer_store_dword v1, off, s[0:3], s32
+; GFX900-NEXT: buffer_load_sbyte_d16 v0, off, s[0:3], s32 offset:4095
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v0, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_private_lo_v2f16_reglo_vreg_sexti8_to_offset:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_mov_b32_e32 v1, 0x7b
+; GFX906-NEXT: buffer_store_dword v1, off, s[0:3], s32
+; GFX906-NEXT: buffer_load_sbyte v1, off, s[0:3], s32 offset:4095
+; GFX906-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX906-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_private_lo_v2f16_reglo_vreg_sexti8_to_offset:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_mov_b32_e32 v1, 0x7b
+; GFX803-NEXT: buffer_store_dword v1, off, s[0:3], s32
+; GFX803-NEXT: buffer_load_sbyte v1, off, s[0:3], s32 offset:4095
+; GFX803-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX803-NEXT: s_waitcnt vmcnt(0)
+; GFX803-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%obj0 = alloca [10 x i32], align 4, addrspace(5)
%obj1 = alloca [4096 x i8], align 2, addrspace(5)
@@ -973,12 +2005,45 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_private_lo_v2f16_reglo_vreg_zexti8_to_offset:
-; GFX900: buffer_store_dword
-; GFX900-NEXT: buffer_load_ubyte_d16 v0, off, s[0:3], s32 offset:4095
-
-; NO-D16-HI: buffer_load_ubyte v
define void @load_private_lo_v2f16_reglo_vreg_zexti8_to_offset(i32 %reg) #0 {
+; GFX900-LABEL: load_private_lo_v2f16_reglo_vreg_zexti8_to_offset:
+; GFX900: ; %bb.0: ; %entry
+; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-NEXT: v_mov_b32_e32 v1, 0x7b
+; GFX900-NEXT: buffer_store_dword v1, off, s[0:3], s32
+; GFX900-NEXT: buffer_load_ubyte_d16 v0, off, s[0:3], s32 offset:4095
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: global_store_dword v[0:1], v0, off
+; GFX900-NEXT: s_waitcnt vmcnt(0)
+; GFX900-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX906-LABEL: load_private_lo_v2f16_reglo_vreg_zexti8_to_offset:
+; GFX906: ; %bb.0: ; %entry
+; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX906-NEXT: v_mov_b32_e32 v1, 0x7b
+; GFX906-NEXT: buffer_store_dword v1, off, s[0:3], s32
+; GFX906-NEXT: buffer_load_ubyte v1, off, s[0:3], s32 offset:4095
+; GFX906-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX906-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX906-NEXT: global_store_dword v[0:1], v0, off
+; GFX906-NEXT: s_waitcnt vmcnt(0)
+; GFX906-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX803-LABEL: load_private_lo_v2f16_reglo_vreg_zexti8_to_offset:
+; GFX803: ; %bb.0: ; %entry
+; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX803-NEXT: v_mov_b32_e32 v1, 0x7b
+; GFX803-NEXT: buffer_store_dword v1, off, s[0:3], s32
+; GFX803-NEXT: buffer_load_ubyte v1, off, s[0:3], s32 offset:4095
+; GFX803-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX803-NEXT: s_mov_b32 s4, 0x5040c00
+; GFX803-NEXT: s_waitcnt vmcnt(0)
+; GFX803-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX803-NEXT: flat_store_dword v[0:1], v0
+; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX803-NEXT: s_setpc_b64 s[30:31]
entry:
%obj0 = alloca [10 x i32], align 4, addrspace(5)
%obj1 = alloca [4096 x i8], align 2, addrspace(5)
Modified: llvm/trunk/test/CodeGen/AMDGPU/memory_clause.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/memory_clause.ll?rev=369787&r1=369786&r2=369787&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/memory_clause.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/memory_clause.ll Fri Aug 23 10:58:49 2019
@@ -1,12 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=gfx902 -verify-machineinstrs -amdgpu-enable-global-sgpr-addr < %s | FileCheck -check-prefix=GCN %s
-; GCN-LABEL: {{^}}vector_clause:
-; GCN: global_load_dwordx4
-; GCN-NEXT: global_load_dwordx4
-; GCN-NEXT: global_load_dwordx4
-; GCN-NEXT: global_load_dwordx4
-; GCN-NEXT: s_nop
define amdgpu_kernel void @vector_clause(<4 x i32> addrspace(1)* noalias nocapture readonly %arg, <4 x i32> addrspace(1)* noalias nocapture %arg1) {
+; GCN-LABEL: vector_clause:
+; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GCN-NEXT: v_mov_b32_e32 v17, 0
+; GCN-NEXT: v_lshlrev_b32_e32 v16, 4, v0
+; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2c
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: global_load_dwordx4 v[0:3], v[16:17], s[2:3]
+; GCN-NEXT: global_load_dwordx4 v[4:7], v[16:17], s[2:3] offset:16
+; GCN-NEXT: global_load_dwordx4 v[8:11], v[16:17], s[2:3] offset:32
+; GCN-NEXT: global_load_dwordx4 v[12:15], v[16:17], s[2:3] offset:48
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: s_waitcnt vmcnt(3)
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: global_store_dwordx4 v[16:17], v[0:3], s[4:5]
+; GCN-NEXT: s_waitcnt vmcnt(3)
+; GCN-NEXT: global_store_dwordx4 v[16:17], v[4:7], s[4:5] offset:16
+; GCN-NEXT: s_waitcnt vmcnt(3)
+; GCN-NEXT: global_store_dwordx4 v[16:17], v[8:11], s[4:5] offset:32
+; GCN-NEXT: s_waitcnt vmcnt(3)
+; GCN-NEXT: global_store_dwordx4 v[16:17], v[12:15], s[4:5] offset:48
+; GCN-NEXT: s_endpgm
bb:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
%tmp2 = zext i32 %tmp to i64
@@ -32,16 +49,45 @@ bb:
ret void
}
-; GCN-LABEL: {{^}}scalar_clause:
-; GCN: s_load_dwordx2
-; GCN-NEXT: s_load_dwordx2
-; GCN-NEXT: s_nop
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_load_dwordx4
-; GCN-NEXT: s_load_dwordx4
-; GCN-NEXT: s_load_dwordx4
-; GCN-NEXT: s_load_dwordx4
define amdgpu_kernel void @scalar_clause(<4 x i32> addrspace(1)* noalias nocapture readonly %arg, <4 x i32> addrspace(1)* noalias nocapture %arg1) {
+; GCN-LABEL: scalar_clause:
+; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: s_load_dwordx2 s[16:17], s[0:1], 0x24
+; GCN-NEXT: s_load_dwordx2 s[18:19], s[0:1], 0x2c
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_load_dwordx4 s[0:3], s[16:17], 0x0
+; GCN-NEXT: s_load_dwordx4 s[4:7], s[16:17], 0x10
+; GCN-NEXT: s_load_dwordx4 s[8:11], s[16:17], 0x20
+; GCN-NEXT: s_load_dwordx4 s[12:15], s[16:17], 0x30
+; GCN-NEXT: v_mov_b32_e32 v12, s18
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NEXT: v_mov_b32_e32 v4, s4
+; GCN-NEXT: v_mov_b32_e32 v13, s19
+; GCN-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NEXT: v_mov_b32_e32 v2, s2
+; GCN-NEXT: v_mov_b32_e32 v3, s3
+; GCN-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NEXT: v_mov_b32_e32 v6, s6
+; GCN-NEXT: v_mov_b32_e32 v7, s7
+; GCN-NEXT: v_mov_b32_e32 v8, s8
+; GCN-NEXT: v_mov_b32_e32 v9, s9
+; GCN-NEXT: v_mov_b32_e32 v10, s10
+; GCN-NEXT: v_mov_b32_e32 v11, s11
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: global_store_dwordx4 v[12:13], v[0:3], off
+; GCN-NEXT: global_store_dwordx4 v[12:13], v[4:7], off offset:16
+; GCN-NEXT: v_mov_b32_e32 v0, s12
+; GCN-NEXT: v_mov_b32_e32 v1, s13
+; GCN-NEXT: v_mov_b32_e32 v2, s14
+; GCN-NEXT: v_mov_b32_e32 v3, s15
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: global_store_dwordx4 v[12:13], v[8:11], off offset:32
+; GCN-NEXT: global_store_dwordx4 v[12:13], v[0:3], off offset:48
+; GCN-NEXT: s_endpgm
bb:
%tmp = load <4 x i32>, <4 x i32> addrspace(1)* %arg, align 16
%tmp2 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 1
@@ -60,26 +106,70 @@ bb:
ret void
}
-; GCN-LABEL: {{^}}mubuf_clause:
-; GCN: buffer_load_dword
-; GCN-NEXT: buffer_load_dword
-; GCN-NEXT: buffer_load_dword
-; GCN-NEXT: buffer_load_dword
-; GCN-NEXT: buffer_load_dword
-; GCN-NEXT: buffer_load_dword
-; GCN-NEXT: buffer_load_dword
-; GCN-NEXT: buffer_load_dword
-; GCN-NEXT: buffer_load_dword
-; GCN-NEXT: buffer_load_dword
-; GCN-NEXT: buffer_load_dword
-; GCN-NEXT: buffer_load_dword
-; GCN-NEXT: buffer_load_dword
-; GCN-NEXT: buffer_load_dword
-; GCN-NEXT: buffer_load_dword
-; GCN-NEXT: s_nop
-; GCN-NEXT: s_nop
-; GCN-NEXT: buffer_load_dword
define void @mubuf_clause(<4 x i32> addrspace(5)* noalias nocapture readonly %arg, <4 x i32> addrspace(5)* noalias nocapture %arg1) {
+; GCN-LABEL: mubuf_clause:
+; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_and_b32_e32 v2, 0x3ff, v2
+; GCN-NEXT: v_lshlrev_b32_e32 v2, 4, v2
+; GCN-NEXT: v_add_u32_e32 v0, v0, v2
+; GCN-NEXT: v_add_u32_e32 v1, v1, v2
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: buffer_load_dword v3, v0, s[0:3], s33 offen
+; GCN-NEXT: buffer_load_dword v4, v0, s[0:3], s33 offen offset:4
+; GCN-NEXT: buffer_load_dword v5, v0, s[0:3], s33 offen offset:8
+; GCN-NEXT: buffer_load_dword v6, v0, s[0:3], s33 offen offset:12
+; GCN-NEXT: buffer_load_dword v7, v0, s[0:3], s33 offen offset:16
+; GCN-NEXT: buffer_load_dword v8, v0, s[0:3], s33 offen offset:20
+; GCN-NEXT: buffer_load_dword v9, v0, s[0:3], s33 offen offset:24
+; GCN-NEXT: buffer_load_dword v10, v0, s[0:3], s33 offen offset:28
+; GCN-NEXT: buffer_load_dword v11, v0, s[0:3], s33 offen offset:32
+; GCN-NEXT: buffer_load_dword v12, v0, s[0:3], s33 offen offset:36
+; GCN-NEXT: buffer_load_dword v13, v0, s[0:3], s33 offen offset:40
+; GCN-NEXT: buffer_load_dword v14, v0, s[0:3], s33 offen offset:44
+; GCN-NEXT: buffer_load_dword v15, v0, s[0:3], s33 offen offset:48
+; GCN-NEXT: buffer_load_dword v16, v0, s[0:3], s33 offen offset:52
+; GCN-NEXT: buffer_load_dword v17, v0, s[0:3], s33 offen offset:56
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: buffer_load_dword v0, v0, s[0:3], s33 offen offset:60
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: s_waitcnt vmcnt(15)
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: buffer_store_dword v3, v1, s[0:3], s33 offen
+; GCN-NEXT: s_waitcnt vmcnt(15)
+; GCN-NEXT: buffer_store_dword v4, v1, s[0:3], s33 offen offset:4
+; GCN-NEXT: s_waitcnt vmcnt(15)
+; GCN-NEXT: buffer_store_dword v5, v1, s[0:3], s33 offen offset:8
+; GCN-NEXT: s_waitcnt vmcnt(15)
+; GCN-NEXT: buffer_store_dword v6, v1, s[0:3], s33 offen offset:12
+; GCN-NEXT: s_waitcnt vmcnt(15)
+; GCN-NEXT: buffer_store_dword v7, v1, s[0:3], s33 offen offset:16
+; GCN-NEXT: s_waitcnt vmcnt(15)
+; GCN-NEXT: buffer_store_dword v8, v1, s[0:3], s33 offen offset:20
+; GCN-NEXT: s_waitcnt vmcnt(15)
+; GCN-NEXT: buffer_store_dword v9, v1, s[0:3], s33 offen offset:24
+; GCN-NEXT: s_waitcnt vmcnt(15)
+; GCN-NEXT: buffer_store_dword v10, v1, s[0:3], s33 offen offset:28
+; GCN-NEXT: s_waitcnt vmcnt(15)
+; GCN-NEXT: buffer_store_dword v11, v1, s[0:3], s33 offen offset:32
+; GCN-NEXT: s_waitcnt vmcnt(15)
+; GCN-NEXT: buffer_store_dword v12, v1, s[0:3], s33 offen offset:36
+; GCN-NEXT: s_waitcnt vmcnt(15)
+; GCN-NEXT: buffer_store_dword v13, v1, s[0:3], s33 offen offset:40
+; GCN-NEXT: s_waitcnt vmcnt(15)
+; GCN-NEXT: buffer_store_dword v14, v1, s[0:3], s33 offen offset:44
+; GCN-NEXT: s_waitcnt vmcnt(15)
+; GCN-NEXT: buffer_store_dword v15, v1, s[0:3], s33 offen offset:48
+; GCN-NEXT: s_waitcnt vmcnt(15)
+; GCN-NEXT: buffer_store_dword v16, v1, s[0:3], s33 offen offset:52
+; GCN-NEXT: s_waitcnt vmcnt(15)
+; GCN-NEXT: buffer_store_dword v17, v1, s[0:3], s33 offen offset:56
+; GCN-NEXT: s_waitcnt vmcnt(15)
+; GCN-NEXT: buffer_store_dword v0, v1, s[0:3], s33 offen offset:60
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
bb:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
%tmp2 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %arg, i32 %tmp
@@ -104,14 +194,29 @@ bb:
ret void
}
-; GCN-LABEL: {{^}}vector_clause_indirect:
-; GCN: global_load_dwordx2 [[ADDR:v\[[0-9:]+\]]], v[{{[0-9:]+}}], s[{{[0-9:]+}}]
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: s_nop 0
-; GCN-NEXT: global_load_dwordx4 v[{{[0-9:]+}}], [[ADDR]], off
-; GCN-NEXT: global_load_dwordx4 v[{{[0-9:]+}}], [[ADDR]], off offset:16
define amdgpu_kernel void @vector_clause_indirect(i64 addrspace(1)* noalias nocapture readonly %arg, <4 x i32> addrspace(1)* noalias nocapture readnone %arg1, <4 x i32> addrspace(1)* noalias nocapture %arg2) {
+; GCN-LABEL: vector_clause_indirect:
+; GCN: ; %bb.0: ; %bb
+; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GCN-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 3, v0
+; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: global_load_dwordx2 v[8:9], v[0:1], s[2:3]
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: global_load_dwordx4 v[0:3], v[8:9], off
+; GCN-NEXT: global_load_dwordx4 v[4:7], v[8:9], off offset:16
+; GCN-NEXT: v_mov_b32_e32 v9, s5
+; GCN-NEXT: v_mov_b32_e32 v8, s4
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: global_store_dwordx4 v[8:9], v[0:3], off
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: global_store_dwordx4 v[8:9], v[4:7], off offset:16
+; GCN-NEXT: s_endpgm
bb:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
%tmp3 = zext i32 %tmp to i64
@@ -127,12 +232,25 @@ bb:
ret void
}
-; GCN-LABEL: {{^}}load_global_d16_hi:
-; GCN: global_load_short_d16_hi v
-; GCN-NEXT: s_nop
-; GCN-NEXT: s_nop
-; GCN-NEXT: global_load_short_d16_hi v
define void @load_global_d16_hi(i16 addrspace(1)* %in, i16 %reg, <2 x i16> addrspace(1)* %out) {
+; GCN-LABEL: load_global_d16_hi:
+; GCN: ; %bb.0: ; %entry
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v5, v2
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: global_load_short_d16_hi v5, v[0:1], off
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: global_load_short_d16_hi v2, v[0:1], off offset:64
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: global_store_dword v[3:4], v5, off
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: global_store_dword v[3:4], v2, off offset:128
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
entry:
%gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i64 32
%load1 = load i16, i16 addrspace(1)* %in
@@ -147,12 +265,25 @@ entry:
ret void
}
-; GCN-LABEL: {{^}}load_global_d16_lo:
-; GCN: global_load_short_d16 v
-; GCN-NEXT: s_nop
-; GCN-NEXT: s_nop
-; GCN-NEXT: global_load_short_d16 v
define void @load_global_d16_lo(i16 addrspace(1)* %in, i32 %reg, <2 x i16> addrspace(1)* %out) {
+; GCN-LABEL: load_global_d16_lo:
+; GCN: ; %bb.0: ; %entry
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v5, v2
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: global_load_short_d16 v5, v[0:1], off
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: global_load_short_d16 v2, v[0:1], off offset:64
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: s_nop 0
+; GCN-NEXT: global_store_dword v[3:4], v5, off
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: global_store_dword v[3:4], v2, off offset:128
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
entry:
%gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i64 32
%reg.bc1 = bitcast i32 %reg to <2 x i16>
Modified: llvm/trunk/test/CodeGen/AMDGPU/r600-export-fix.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/r600-export-fix.ll?rev=369787&r1=369786&r2=369787&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/r600-export-fix.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/r600-export-fix.ll Fri Aug 23 10:58:49 2019
@@ -1,16 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=r600 -mcpu=cedar | FileCheck %s
-;CHECK: EXPORT T{{[0-9]}}.XYZW
-;CHECK: EXPORT T{{[0-9]}}.0000
-;CHECK: EXPORT T{{[0-9]}}.0000
-;CHECK: EXPORT T{{[0-9]}}.0YZW
-;CHECK: EXPORT T{{[0-9]}}.XYZW
-;CHECK: EXPORT T{{[0-9]}}.XY00
-;CHECK: EXPORT T{{[0-9]}}.0000
-;CHECK: EXPORT T{{[0-9]}}.0000
-
-
define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {
+; CHECK-LABEL: main:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: CALL_FS
+; CHECK-NEXT: ALU 24, @12, KC0[CB0:0-32], KC1[]
+; CHECK-NEXT: EXPORT T0.XYZW
+; CHECK-NEXT: EXPORT T0.0000
+; CHECK-NEXT: EXPORT T0.0000
+; CHECK-NEXT: EXPORT T4.0YZW
+; CHECK-NEXT: EXPORT T3.XYZW
+; CHECK-NEXT: EXPORT T2.XY00
+; CHECK-NEXT: EXPORT T0.0000
+; CHECK-NEXT: EXPORT T0.0000
+; CHECK-NEXT: CF_END
+; CHECK-NEXT: PAD
+; CHECK-NEXT: ALU clause starting at 12:
+; CHECK-NEXT: MUL_IEEE * T0.W, KC0[4].X, T1.X,
+; CHECK-NEXT: MULADD_IEEE T0.W, KC0[5].X, T1.Y, PV.W,
+; CHECK-NEXT: MUL_IEEE * T2.W, KC0[4].Y, T1.X,
+; CHECK-NEXT: MULADD_IEEE * T0.W, KC0[6].X, T1.Z, PV.W,
+; CHECK-NEXT: MULADD_IEEE T0.X, KC0[7].X, T1.W, PV.W,
+; CHECK-NEXT: MULADD_IEEE * T0.W, KC0[5].Y, T1.Y, T2.W,
+; CHECK-NEXT: MUL_IEEE * T2.W, KC0[4].Z, T1.X,
+; CHECK-NEXT: MOV T2.Y, KC0[2].Z,
+; CHECK-NEXT: MULADD_IEEE * T2.W, KC0[5].Z, T1.Y, PV.W,
+; CHECK-NEXT: MULADD_IEEE * T0.W, KC0[6].Y, T1.Z, T0.W,
+; CHECK-NEXT: MOV T2.X, KC0[2].Y,
+; CHECK-NEXT: MULADD_IEEE * T0.Y, KC0[7].Y, T1.W, PV.W,
+; CHECK-NEXT: MULADD_IEEE * T0.W, KC0[6].Z, T1.Z, T2.W,
+; CHECK-NEXT: MULADD_IEEE T0.Z, KC0[7].Z, T1.W, PV.W,
+; CHECK-NEXT: MUL_IEEE * T0.W, KC0[4].W, T1.X,
+; CHECK-NEXT: MOV * T3.W, KC0[2].X,
+; CHECK-NEXT: MOV T3.Z, KC0[3].Z,
+; CHECK-NEXT: MULADD_IEEE * T0.W, KC0[5].W, T1.Y, T0.W,
+; CHECK-NEXT: MOV * T4.W, KC0[0].Z,
+; CHECK-NEXT: MOV T3.Y, KC0[3].Y,
+; CHECK-NEXT: MOV * T4.Z, KC0[0].Y,
+; CHECK-NEXT: MULADD_IEEE * T0.W, KC0[6].W, T1.Z, T0.W,
+; CHECK-NEXT: MOV T3.X, KC0[3].X,
+; CHECK-NEXT: MOV * T4.Y, KC0[0].X,
+; CHECK-NEXT: MULADD_IEEE * T0.W, KC0[7].W, T1.W, T0.W,
main_body:
%0 = extractelement <4 x float> %reg1, i32 0
%1 = extractelement <4 x float> %reg1, i32 1
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