[PATCH] D66636: [X86][BtVer2] Fix latency of ALU RMW instructions.

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb created this revision.
andreadb added reviewers: RKSimon, craig.topper.
Herald added a subscriber: gbedwell.

Excluding ADC/SBB and the bit-test instructions (BTR/BTS/BTC), the observed latency of all other RMW integer arithmetic/logic instructions is 6cy and not 5cy.

Example (ADD):

  addb $0, (%rsp)            # Latency: 6cy
  addb $7, (%rsp)            # Latency: 6cy
  addb %sil, (%rsp)          # Latency: 6cy
  
  addw $0, (%rsp)            # Latency: 6cy
  addw $511, (%rsp)          # Latency: 6cy
  addw %si, (%rsp)           # Latency: 6cy
  
  addl $0, (%rsp)            # Latency: 6cy
  addl $511, (%rsp)          # Latency: 6cy
  addl %esi, (%rsp)          # Latency: 6cy
  
  addq $0, (%rsp)            # Latency: 6cy
  addq $511, (%rsp)          # Latency: 6cy
  addq %rsi, (%rsp)          # Latency: 6cy

The same latency profile applies to SUB/AND/OR/XOR/INC/DEC.

The observed latency of ADC/SBB is 7-8cy. So we need a different write to model those.
Latency of BTS/BTR/BTC is not fixed by this patch (they are much slower than what the model for btver2 currently reports).


https://reviews.llvm.org/D66636

Files:
  lib/Target/X86/X86ScheduleBtVer2.td
  test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s

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