[llvm] r369700 - [PowerPC] Automatically generate various tests. NFC
Amaury Sechet via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 22 13:26:56 PDT 2019
Author: deadalnix
Date: Thu Aug 22 13:26:56 2019
New Revision: 369700
URL: http://llvm.org/viewvc/llvm-project?rev=369700&view=rev
Log:
[PowerPC] Automatically generate various tests. NFC
Modified:
llvm/trunk/test/CodeGen/PowerPC/testComparesi32gtu.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesi32ltu.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigeuc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigeui.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigeull.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigeus.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigtsc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigtsi.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigtsll.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigtss.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigtuc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigtui.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesigtus.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesileuc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesileui.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesileull.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesileus.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesiltsc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesiltsi.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesiltsll.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesiltss.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesiltuc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesiltui.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesiltus.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllgeuc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllgeui.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllgeull.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllgeus.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllgtsll.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllgtuc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllgtui.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllgtus.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllleuc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllleui.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllleull.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllleus.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllltsll.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllltuc.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllltui.ll
llvm/trunk/test/CodeGen/PowerPC/testComparesllltus.ll
llvm/trunk/test/CodeGen/PowerPC/vec_shuffle.ll
llvm/trunk/test/CodeGen/PowerPC/vec_shuffle_le.ll
llvm/trunk/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll
llvm/trunk/test/CodeGen/PowerPC/vec_shuffle_p8vector_le.ll
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesi32gtu.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesi32gtu.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesi32gtu.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesi32gtu.ll Thu Aug 22 13:26:56 2019
@@ -1,25 +1,65 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
%struct.tree_common = type { i8, [3 x i8] }
declare signext i32 @fn2(...) local_unnamed_addr #1
; Function Attrs: nounwind
define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) {
-; CHECK-LABEL: testCompare1:
-; CHECK: # %bb.0: # %entry
-; CHECK: lbz r3, 0(r3)
-; CHECK-DAG: clrlwi r3, r3, 31
-; CHECK-DAG: clrldi r3, r3, 32
-; CHECK: lbz r4, 0(r4)
-; CHECK-DAG: clrlwi r4, r4, 31
-; CHECK-DAG: clrldi r4, r4, 32
-; CHECK: sub r3, r3, r4
-; CHECK-NEXT: rldicl r3, r3, 1, 63
+; BE-LABEL: testCompare1:
+; BE: # %bb.0: # %entry
+; BE-NEXT: mflr r0
+; BE-NEXT: std r0, 16(r1)
+; BE-NEXT: stdu r1, -112(r1)
+; BE-NEXT: .cfi_def_cfa_offset 112
+; BE-NEXT: .cfi_offset lr, 16
+; BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; BE-NEXT: lbz r3, 0(r3)
+; BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; BE-NEXT: clrlwi r3, r3, 31
+; BE-NEXT: clrldi r3, r3, 32
+; BE-NEXT: lbz r4, 0(r4)
+; BE-NEXT: clrlwi r4, r4, 31
+; BE-NEXT: clrldi r4, r4, 32
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: bl fn2
+; BE-NEXT: nop
+; BE-NEXT: addi r1, r1, 112
+; BE-NEXT: ld r0, 16(r1)
+; BE-NEXT: mtlr r0
+; BE-NEXT: blr
+;
+; LE-LABEL: testCompare1:
+; LE: # %bb.0: # %entry
+; LE-NEXT: mflr r0
+; LE-NEXT: std r0, 16(r1)
+; LE-NEXT: stdu r1, -32(r1)
+; LE-NEXT: .cfi_def_cfa_offset 32
+; LE-NEXT: .cfi_offset lr, 16
+; LE-NEXT: addis r4, r2, .LC0 at toc@ha
+; LE-NEXT: lbz r3, 0(r3)
+; LE-NEXT: ld r4, .LC0 at toc@l(r4)
+; LE-NEXT: clrlwi r3, r3, 31
+; LE-NEXT: clrldi r3, r3, 32
+; LE-NEXT: lbz r4, 0(r4)
+; LE-NEXT: clrlwi r4, r4, 31
+; LE-NEXT: clrldi r4, r4, 32
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: bl fn2
+; LE-NEXT: nop
+; LE-NEXT: addi r1, r1, 32
+; LE-NEXT: ld r0, 16(r1)
+; LE-NEXT: mtlr r0
+; LE-NEXT: blr
entry:
%bf.load = load i8, i8* bitcast (i32 (%struct.tree_common*)* @testCompare1 to i8*), align 4
%bf.clear = and i8 %bf.load, 1
@@ -36,11 +76,11 @@ entry:
define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: testCompare2:
; CHECK: # %bb.0: # %entry
-; CHECK-DAG: rlwinm r3, r3, 0, 31, 31
-; CHECK-DAG: rlwinm r4, r4, 0, 31, 31
-; CHECK-DAG: clrldi r3, r3, 32
-; CHECK-DAG: clrldi r4, r4, 32
-; CHECK: sub r3, r4, r3
+; CHECK-NEXT: rlwinm r3, r3, 0, 31, 31
+; CHECK-NEXT: rlwinm r4, r4, 0, 31, 31
+; CHECK-NEXT: clrldi r3, r3, 32
+; CHECK-NEXT: clrldi r4, r4, 32
+; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesi32ltu.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesi32ltu.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesi32ltu.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesi32ltu.ll Thu Aug 22 13:26:56 2019
@@ -1,25 +1,65 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
%struct.tree_common = type { i8, [3 x i8] }
declare signext i32 @fn2(...) local_unnamed_addr #1
; Function Attrs: nounwind
define i32 @testCompare1(%struct.tree_common* nocapture readonly %arg1) {
-; CHECK-LABEL: testCompare1:
-; CHECK: # %bb.0: # %entry
-; CHECK: lbz r3, 0(r3)
-; CHECK-DAG: clrlwi r3, r3, 31
-; CHECK-DAG: clrldi r3, r3, 32
-; CHECK: lbz r4, 0(r4)
-; CHECK-DAG: clrlwi r4, r4, 31
-; CHECK-DAG: clrldi r4, r4, 32
-; CHECK: sub r3, r4, r3
-; CHECK-NEXT: rldicl r3, r3, 1, 63
+; BE-LABEL: testCompare1:
+; BE: # %bb.0: # %entry
+; BE-NEXT: mflr r0
+; BE-NEXT: std r0, 16(r1)
+; BE-NEXT: stdu r1, -112(r1)
+; BE-NEXT: .cfi_def_cfa_offset 112
+; BE-NEXT: .cfi_offset lr, 16
+; BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; BE-NEXT: lbz r3, 0(r3)
+; BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; BE-NEXT: clrlwi r3, r3, 31
+; BE-NEXT: clrldi r3, r3, 32
+; BE-NEXT: lbz r4, 0(r4)
+; BE-NEXT: clrlwi r4, r4, 31
+; BE-NEXT: clrldi r4, r4, 32
+; BE-NEXT: sub r3, r4, r3
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: bl fn2
+; BE-NEXT: nop
+; BE-NEXT: addi r1, r1, 112
+; BE-NEXT: ld r0, 16(r1)
+; BE-NEXT: mtlr r0
+; BE-NEXT: blr
+;
+; LE-LABEL: testCompare1:
+; LE: # %bb.0: # %entry
+; LE-NEXT: mflr r0
+; LE-NEXT: std r0, 16(r1)
+; LE-NEXT: stdu r1, -32(r1)
+; LE-NEXT: .cfi_def_cfa_offset 32
+; LE-NEXT: .cfi_offset lr, 16
+; LE-NEXT: addis r4, r2, .LC0 at toc@ha
+; LE-NEXT: lbz r3, 0(r3)
+; LE-NEXT: ld r4, .LC0 at toc@l(r4)
+; LE-NEXT: clrlwi r3, r3, 31
+; LE-NEXT: clrldi r3, r3, 32
+; LE-NEXT: lbz r4, 0(r4)
+; LE-NEXT: clrlwi r4, r4, 31
+; LE-NEXT: clrldi r4, r4, 32
+; LE-NEXT: sub r3, r4, r3
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: bl fn2
+; LE-NEXT: nop
+; LE-NEXT: addi r1, r1, 32
+; LE-NEXT: ld r0, 16(r1)
+; LE-NEXT: mtlr r0
+; LE-NEXT: blr
entry:
%bf.load = load i8, i8* bitcast (i32 (%struct.tree_common*)* @testCompare1 to i8*), align 4
%bf.clear = and i8 %bf.load, 1
@@ -36,11 +76,11 @@ entry:
define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: testCompare2:
; CHECK: # %bb.0: # %entry
-; CHECK-DAG: rlwinm r3, r3, 0, 31, 31
-; CHECK-DAG: rlwinm r4, r4, 0, 31, 31
-; CHECK-DAG: clrldi r3, r3, 32
-; CHECK-DAG: clrldi r4, r4, 32
-; CHECK: sub r3, r3, r4
+; CHECK-NEXT: rlwinm r3, r3, 0, 31, 31
+; CHECK-NEXT: rlwinm r4, r4, 0, 31, 31
+; CHECK-NEXT: clrldi r3, r3, 32
+; CHECK-NEXT: clrldi r4, r4, 32
+; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigeuc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigeuc.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigeuc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigeuc.ll Thu Aug 22 13:26:56 2019
@@ -1,77 +1,116 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeuc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_igeuc:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
-; CHECK-LABEL: test_igeuc:
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeuc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_igeuc_sext:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: addi r3, r3, -1
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i8 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
-; CHECK-LABEL: @test_igeuc_sext
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK-NEXT: blr
-
+
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeuc_z(i8 zeroext %a) {
+; CHECK-LABEL: test_igeuc_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li r3, 1
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i8 %a, 0
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
-; CHECK-LABEL: @test_igeuc_z
-; CHECK: li r3, 1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeuc_sext_z(i8 zeroext %a) {
+; CHECK-LABEL: test_igeuc_sext_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li r3, -1
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i8 %a, 0
%conv2 = sext i1 %cmp to i32
ret i32 %conv2
-; CHECK-LABEL: @test_igeuc_sext_z
-; CHECK: li r3, -1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeuc_store(i8 zeroext %a, i8 zeroext %b) {
+; BE-LABEL: test_igeuc_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: not r3, r3
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: stb r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_igeuc_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: not r3, r3
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: stb r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob
ret void
; CHECK_LABEL: test_igeuc_store:
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; BE-LABEL: test_igeuc_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: addi r3, r3, -1
+; BE-NEXT: stb r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_igeuc_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: addi r3, r3, -1
+; LE-NEXT: stb r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i8 %a, %b
%conv3 = sext i1 %cmp to i8
@@ -82,31 +121,51 @@ entry:
; CHECK-TBD: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK-TBD: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK-TBD: stb [[REG3]]
-; CHECK-TBD: blr
+; CHECK-TBD: blr
}
; Function Attrs : norecurse nounwind
define void @test_igeuc_z_store(i8 zeroext %a) {
+; BE-LABEL: test_igeuc_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r3, r2, .LC0 at toc@ha
+; BE-NEXT: li r4, 1
+; BE-NEXT: ld r3, .LC0 at toc@l(r3)
+; BE-NEXT: stb r4, 0(r3)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_igeuc_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: addis r3, r2, glob at toc@ha
+; LE-NEXT: li r4, 1
+; LE-NEXT: stb r4, glob at toc@l(r3)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i8 %a, 0
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob
ret void
-; CHECK-LABEL: @test_igeuc_z_store
-; CHECK: li [[REG1:r[0-9]+]], 1
-; CHECK: stb [[REG1]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeuc_sext_z_store(i8 zeroext %a) {
+; BE-LABEL: test_igeuc_sext_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r3, r2, .LC0 at toc@ha
+; BE-NEXT: li r4, -1
+; BE-NEXT: ld r3, .LC0 at toc@l(r3)
+; BE-NEXT: stb r4, 0(r3)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_igeuc_sext_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: addis r3, r2, glob at toc@ha
+; LE-NEXT: li r4, -1
+; LE-NEXT: stb r4, glob at toc@l(r3)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i8 %a, 0
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob
ret void
-; CHECK-LABEL: @test_igeuc_sext_z_store
-; CHECK: li [[REG1:r[0-9]+]], -1
-; CHECK: stb [[REG1]]
-; CHECK: blr
}
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigeui.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigeui.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigeui.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigeui.ll Thu Aug 22 13:26:56 2019
@@ -1,112 +1,165 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_igeui:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
-; CHECK-LABEL: test_igeui:
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_igeui_sext:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: addi r3, r3, -1
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i32 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
-; CHECK-LABEL: @test_igeui_sext
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeui_z(i32 zeroext %a) {
+; CHECK-LABEL: test_igeui_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li r3, 1
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i32 %a, 0
%sub = zext i1 %cmp to i32
ret i32 %sub
-; CHECK-LABEL: @test_igeui_z
-; CHECK: li r3, 1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeui_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_igeui_sext_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li r3, -1
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i32 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
-; CHECK-LABEL: @test_igeui_sext_z
-; CHECK: li r3, -1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeui_store(i32 zeroext %a, i32 zeroext %b) {
+; BE-LABEL: test_igeui_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: not r3, r3
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: stw r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_igeui_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: not r3, r3
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: stw r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob
ret void
; CHECK_LABEL: test_igeuc_store:
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; BE-LABEL: test_igeui_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: addi r3, r3, -1
+; BE-NEXT: stw r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_igeui_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: addi r3, r3, -1
+; LE-NEXT: stw r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob
ret void
-; CHECK-LABEL: @test_igeui_sext_store
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK: stw [[REG3]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeui_z_store(i32 zeroext %a) {
+; BE-LABEL: test_igeui_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r3, r2, .LC0 at toc@ha
+; BE-NEXT: li r4, 1
+; BE-NEXT: ld r3, .LC0 at toc@l(r3)
+; BE-NEXT: stw r4, 0(r3)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_igeui_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: addis r3, r2, glob at toc@ha
+; LE-NEXT: li r4, 1
+; LE-NEXT: stw r4, glob at toc@l(r3)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i32 %a, 0
%conv1 = zext i1 %cmp to i32
store i32 %conv1, i32* @glob
ret void
-; CHECK-LABEL: @test_igeui_z_store
-; CHECK: li [[REG1:r[0-9]+]], 1
-; CHECK: stw [[REG1]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeui_sext_z_store(i32 zeroext %a) {
+; BE-LABEL: test_igeui_sext_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r3, r2, .LC0 at toc@ha
+; BE-NEXT: li r4, -1
+; BE-NEXT: ld r3, .LC0 at toc@l(r3)
+; BE-NEXT: stw r4, 0(r3)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_igeui_sext_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: addis r3, r2, glob at toc@ha
+; LE-NEXT: li r4, -1
+; LE-NEXT: stw r4, glob at toc@l(r3)
+; LE-NEXT: blr
entry:
- %cmp = icmp uge i32 %a, 0
+ %cmp = icmp uge i32 %a, 0
%conv1 = sext i1 %cmp to i32
store i32 %conv1, i32* @glob
ret void
-; CHECK-LABEL: @test_igeui_sext_z_store
-; CHECK: li [[REG1:r[0-9]+]], -1
-; CHECK: stw [[REG1]]
-; CHECK: blr
}
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigeull.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigeull.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigeull.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigeull.ll Thu Aug 22 13:26:56 2019
@@ -1,111 +1,163 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeull(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igeull:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subfc r3, r4, r3
+; CHECK-NEXT: subfe r3, r4, r4
+; CHECK-NEXT: addi r3, r3, 1
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i64 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
-; CHECK-LABEL: test_igeull:
-; CHECK: subfc {{r[0-9]+}}, r4, r3
-; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r4, r4
-; CHECK-NEXT: addi r3, [[REG1]], 1
-; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeull_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_igeull_sext:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subfc r3, r4, r3
+; CHECK-NEXT: subfe r3, r4, r4
+; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i64 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
-; CHECK-LABEL: @test_igeull_sext
-; CHECK: subfc [[REG1:r[0-9]+]], r4, r3
-; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
-; CHECK: not r3, [[REG2]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeull_z(i64 %a) {
+; CHECK-LABEL: test_igeull_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li r3, 1
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i64 %a, 0
%sub = zext i1 %cmp to i32
ret i32 %sub
-; CHECK-LABEL: @test_igeull_z
-; CHECK: li r3, 1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeull_sext_z(i64 %a) {
+; CHECK-LABEL: test_igeull_sext_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li r3, -1
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i64 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
-; CHECK-LABEL: @test_igeull_sext_z
-; CHECK: li r3, -1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeull_store(i64 %a, i64 %b) {
+; BE-LABEL: test_igeull_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: subfc r3, r4, r3
+; BE-NEXT: ld r3, .LC0 at toc@l(r5)
+; BE-NEXT: subfe r4, r4, r4
+; BE-NEXT: addi r4, r4, 1
+; BE-NEXT: std r4, 0(r3)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_igeull_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: subfc r3, r4, r3
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: subfe r3, r4, r4
+; LE-NEXT: addi r3, r3, 1
+; LE-NEXT: std r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
-; CHECK-LABEL: test_igeull_store:
-; CHECK: subfc {{r[0-9]+}}, r4, r3
-; CHECK: subfe [[REG1:r[0-9]+]], r4, r4
-; CHECK: addi {{r[0-9]+}}, [[REG1]], 1
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeull_sext_store(i64 %a, i64 %b) {
+; BE-LABEL: test_igeull_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: subfc r3, r4, r3
+; BE-NEXT: ld r3, .LC0 at toc@l(r5)
+; BE-NEXT: subfe r4, r4, r4
+; BE-NEXT: not r4, r4
+; BE-NEXT: std r4, 0(r3)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_igeull_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: subfc r3, r4, r3
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: subfe r3, r4, r4
+; LE-NEXT: not r3, r3
+; LE-NEXT: std r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
-; CHECK-LABEL: @test_igeull_sext_store
-; CHECK: subfc [[REG1:r[0-9]+]], r4, r3
-; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
-; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: std [[REG3]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeull_z_store(i64 %a) {
+; BE-LABEL: test_igeull_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r3, r2, .LC0 at toc@ha
+; BE-NEXT: li r4, 1
+; BE-NEXT: ld r3, .LC0 at toc@l(r3)
+; BE-NEXT: std r4, 0(r3)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_igeull_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: addis r3, r2, glob at toc@ha
+; LE-NEXT: li r4, 1
+; LE-NEXT: std r4, glob at toc@l(r3)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
-; CHECK-LABEL: @test_igeull_z_store
-; CHECK: li [[REG1:r[0-9]+]], 1
-; CHECK: std [[REG1]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeull_sext_z_store(i64 %a) {
+; BE-LABEL: test_igeull_sext_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r3, r2, .LC0 at toc@ha
+; BE-NEXT: li r4, -1
+; BE-NEXT: ld r3, .LC0 at toc@l(r3)
+; BE-NEXT: std r4, 0(r3)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_igeull_sext_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: addis r3, r2, glob at toc@ha
+; LE-NEXT: li r4, -1
+; LE-NEXT: std r4, glob at toc@l(r3)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i64 %a, 0
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
-; CHECK-LABEL: @test_igeull_sext_z_store
-; CHECK: li [[REG1:r[0-9]+]], -1
-; CHECK: std [[REG1]]
-; CHECK: blr
}
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigeus.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigeus.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigeus.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigeus.ll Thu Aug 22 13:26:56 2019
@@ -1,112 +1,165 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeus(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_igeus:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i16 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
-; CHECK-LABEL: test_igeus:
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeus_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_igeus_sext:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: addi r3, r3, -1
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i16 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
-; CHECK-LABEL: @test_igeus_sext
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeus_z(i16 zeroext %a) {
+; CHECK-LABEL: test_igeus_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li r3, 1
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i16 %a, 0
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
-; CHECK-LABEL: @test_igeus_z
-; CHECK: li r3, 1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeus_sext_z(i16 zeroext %a) {
+; CHECK-LABEL: test_igeus_sext_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li r3, 1
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i16 %a, 0
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
-; CHECK-LABEL: @test_igeus_sext_z
-; CHECK: li r3, 1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeus_store(i16 zeroext %a, i16 zeroext %b) {
+; BE-LABEL: test_igeus_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: not r3, r3
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: sth r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_igeus_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: not r3, r3
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: sth r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob
ret void
; CHECK_LABEL: test_igeus_store:
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; BE-LABEL: test_igeus_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: addi r3, r3, -1
+; BE-NEXT: sth r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_igeus_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: addi r3, r3, -1
+; LE-NEXT: sth r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob
ret void
-; CHECK-LABEL: @test_igeus_sext_store
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK: sth [[REG3]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeus_z_store(i16 zeroext %a) {
+; BE-LABEL: test_igeus_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r3, r2, .LC0 at toc@ha
+; BE-NEXT: li r4, 1
+; BE-NEXT: ld r3, .LC0 at toc@l(r3)
+; BE-NEXT: sth r4, 0(r3)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_igeus_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: addis r3, r2, glob at toc@ha
+; LE-NEXT: li r4, 1
+; LE-NEXT: sth r4, glob at toc@l(r3)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i16 %a, 0
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob
ret void
-; CHECK-LABEL: @test_igeus_z_store
-; CHECK: li [[REG1:r[0-9]+]], 1
-; CHECK: sth [[REG1]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_igeus_sext_z_store(i16 zeroext %a) {
+; BE-LABEL: test_igeus_sext_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r3, r2, .LC0 at toc@ha
+; BE-NEXT: li r4, -1
+; BE-NEXT: ld r3, .LC0 at toc@l(r3)
+; BE-NEXT: sth r4, 0(r3)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_igeus_sext_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: addis r3, r2, glob at toc@ha
+; LE-NEXT: li r4, -1
+; LE-NEXT: sth r4, glob at toc@l(r3)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i16 %a, 0
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob
ret void
-; CHECK-LABEL: @test_igeus_sext_z_store
-; CHECK: li [[REG1:r[0-9]+]], -1
-; CHECK: sth [[REG1]]
-; CHECK: blr
}
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigtsc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigtsc.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigtsc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigtsc.ll Thu Aug 22 13:26:56 2019
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@@ -11,8 +12,8 @@
define signext i32 @test_igtsc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igtsc:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i8 %a, %b
@@ -24,8 +25,8 @@ entry:
define signext i32 @test_igtsc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igtsc_sext:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i8 %a, %b
@@ -50,9 +51,10 @@ entry:
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsc_sext_z(i8 signext %a) {
; CHECK-LABEL: test_igtsc_sext_z:
-; CHECK: neg [[REG2:r[0-9]+]], r3
-; CHECK-NEXT: sradi r3, [[REG2]], 63
-; CHECK-NEXT: blr
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i8 %a, 0
%sub = sext i1 %cmp to i32
@@ -63,8 +65,12 @@ entry:
define void @test_igtsc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igtsc_store:
; CHECK: # %bb.0: # %entry
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: stb r3, 0(r5)
+; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i8 %a, %b
%conv3 = zext i1 %cmp to i8
@@ -76,8 +82,12 @@ entry:
define void @test_igtsc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igtsc_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: stb r3, 0(r5)
+; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i8 %a, %b
%conv3 = sext i1 %cmp to i8
@@ -106,8 +116,13 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_igtsc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_igtsc_sext_z_store:
-; CHECK: neg [[REG2:r[0-9]+]], r3
-; CHECK: sradi {{r[0-9]+}}, [[REG2]], 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: stb r3, 0(r4)
+; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i8 %a, 0
%conv2 = sext i1 %cmp to i8
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigtsi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigtsi.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigtsi.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigtsi.ll Thu Aug 22 13:26:56 2019
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@@ -11,8 +12,8 @@
define signext i32 @test_igtsi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igtsi:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, %b
@@ -24,8 +25,8 @@ entry:
define signext i32 @test_igtsi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igtsi_sext:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, %b
@@ -50,9 +51,10 @@ entry:
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsi_sext_z(i32 signext %a) {
; CHECK-LABEL: test_igtsi_sext_z:
-; CHECK: neg [[REG2:r[0-9]+]], r3
-; CHECK-NEXT: sradi r3, [[REG2]], 63
-; CHECK-NEXT: blr
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, 0
%sub = sext i1 %cmp to i32
@@ -63,8 +65,12 @@ entry:
define void @test_igtsi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igtsi_store:
; CHECK: # %bb.0: # %entry
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: stw r3, 0(r5)
+; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, %b
%conv = zext i1 %cmp to i32
@@ -76,8 +82,12 @@ entry:
define void @test_igtsi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igtsi_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: stw r3, 0(r5)
+; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, %b
%sub = sext i1 %cmp to i32
@@ -106,8 +116,13 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_igtsi_sext_z_store(i32 signext %a) {
; CHECK-LABEL: test_igtsi_sext_z_store:
-; CHECK: neg [[REG:r[0-9]+]], r3
-; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: stw r3, 0(r4)
+; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i32 %a, 0
%sub = sext i1 %cmp to i32
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigtsll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigtsll.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigtsll.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigtsll.ll Thu Aug 22 13:26:56 2019
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@@ -11,11 +12,11 @@
define signext i32 @test_igtsll(i64 %a, i64 %b) {
; CHECK-LABEL: test_igtsll:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63
-; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4
-; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK-NEXT: xori r3, [[REG4]], 1
+; CHECK-NEXT: sradi r5, r4, 63
+; CHECK-NEXT: rldicl r6, r3, 1, 63
+; CHECK-NEXT: subfc r3, r3, r4
+; CHECK-NEXT: adde r3, r6, r5
+; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, %b
@@ -27,12 +28,12 @@ entry:
define signext i32 @test_igtsll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_igtsll_sext:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63
-; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4
-; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1
-; CHECK-NEXT: neg r3, [[REG5]]
+; CHECK-NEXT: sradi r5, r4, 63
+; CHECK-NEXT: rldicl r6, r3, 1, 63
+; CHECK-NEXT: subfc r3, r3, r4
+; CHECK-NEXT: adde r3, r6, r5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, %b
@@ -58,9 +59,11 @@ entry:
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsll_sext_z(i64 %a) {
; CHECK-LABEL: test_igtsll_sext_z:
-; CHECK: addi [[REG1:r[0-9]+]], r3, -1
-; CHECK-NEXT: nor [[REG2:r[0-9]+]], [[REG1]], r3
-; CHECK-NEXT: sradi r3, [[REG2]], 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addi r4, r3, -1
+; CHECK-NEXT: nor r3, r4, r3
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, 0
%sub = sext i1 %cmp to i32
@@ -71,12 +74,16 @@ entry:
define void @test_igtsll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_igtsll_store:
; CHECK: # %bb.0: # %entry
-; CHECK: sradi [[REG1:r[0-9]+]], r4, 63
-; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63
+; CHECK-NEXT: sradi r6, r4, 63
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: subfc r4, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: adde r3, r3, r6
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4
-; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
-; CHECK-NOT: neg
entry:
%cmp = icmp sgt i64 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -88,12 +95,17 @@ entry:
define void @test_igtsll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_igtsll_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK: sradi [[REG1:r[0-9]+]], r4, 63
-; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63
+; CHECK-NEXT: sradi r6, r4, 63
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: subfc r4, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: adde r3, r3, r6
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4
-; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
-; CHECK: neg {{r[0-9]+}}, [[REG5]]
entry:
%cmp = icmp sgt i64 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -123,9 +135,14 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_igtsll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_igtsll_sext_z_store:
-; CHECK: addi [[REG1:r[0-9]+]], r3, -1
-; CHECK: nor [[REG2:r[0-9]+]], [[REG1]], r3
-; CHECK: sradi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: addi r5, r3, -1
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: nor r3, r5, r3
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, 0
%conv1 = sext i1 %cmp to i64
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigtss.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigtss.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigtss.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigtss.ll Thu Aug 22 13:26:56 2019
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@@ -11,8 +12,8 @@
define signext i32 @test_igtss(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igtss:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: rldicl r3, [[REG1]], 1, 63
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i16 %a, %b
@@ -24,8 +25,8 @@ entry:
define signext i32 @test_igtss_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igtss_sext:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i16 %a, %b
@@ -51,8 +52,8 @@ entry:
define signext i32 @test_igtss_sext_z(i16 signext %a) {
; CHECK-LABEL: test_igtss_sext_z:
; CHECK: # %bb.0: # %entry
-; CHECK: neg [[REG2:r[0-9]+]], r3
-; CHECK-NEXT: sradi r3, [[REG2]], 63
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i16 %a, 0
@@ -64,8 +65,12 @@ entry:
define void @test_igtss_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igtss_store:
; CHECK: # %bb.0: # %entry
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 1, 63
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: sth r3, 0(r5)
+; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i16 %a, %b
%conv3 = zext i1 %cmp to i16
@@ -77,8 +82,12 @@ entry:
define void @test_igtss_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igtss_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: sth r3, 0(r5)
+; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i16 %a, %b
%conv3 = sext i1 %cmp to i16
@@ -107,8 +116,13 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_igtss_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_igtss_sext_z_store:
-; CHECK: neg [[REG2:r[0-9]+]], r3
-; CHECK: sradi {{r[0-9]+}}, [[REG2]], 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: sth r3, 0(r4)
+; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i16 %a, 0
%conv2 = sext i1 %cmp to i16
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigtuc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigtuc.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigtuc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigtuc.ll Thu Aug 22 13:26:56 2019
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@@ -10,8 +11,9 @@
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_igtuc:
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i8 %a, %b
@@ -22,8 +24,9 @@ entry:
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtuc_sext(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_igtuc_sext:
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i8 %a, %b
@@ -34,7 +37,8 @@ entry:
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtuc_z(i8 zeroext %a) {
; CHECK-LABEL: test_igtuc_z:
-; CHECK: cntlzw r3, r3
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
@@ -47,7 +51,8 @@ entry:
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtuc_sext_z(i8 zeroext %a) {
; CHECK-LABEL: test_igtuc_sext_z:
-; CHECK: cntlzw r3, r3
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
@@ -61,8 +66,13 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_igtuc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_igtuc_store:
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: stb r3, 0(r5)
+; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i8 %a, %b
%conv3 = zext i1 %cmp to i8
@@ -73,8 +83,13 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_igtuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_igtuc_sext_store:
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: stb r3, 0(r5)
+; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i8 %a, %b
%conv3 = sext i1 %cmp to i8
@@ -85,10 +100,13 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_igtuc_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_igtuc_z_store:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: stb r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
@@ -100,11 +118,14 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_igtuc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_igtuc_sext_z_store:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: neg r3, r3
-; CHECK: stb r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigtui.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigtui.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigtui.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigtui.ll Thu Aug 22 13:26:56 2019
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@@ -10,8 +11,9 @@
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_igtui:
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i32 %a, %b
@@ -22,8 +24,9 @@ entry:
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtui_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_igtui_sext:
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i32 %a, %b
@@ -34,7 +37,8 @@ entry:
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtui_z(i32 zeroext %a) {
; CHECK-LABEL: test_igtui_z:
-; CHECK: cntlzw r3, r3
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
@@ -47,7 +51,8 @@ entry:
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtui_sext_z(i32 zeroext %a) {
; CHECK-LABEL: test_igtui_sext_z:
-; CHECK: cntlzw r3, r3
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
@@ -61,8 +66,13 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_igtui_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_igtui_store:
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: stw r3, 0(r5)
+; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i32 %a, %b
%conv = zext i1 %cmp to i32
@@ -73,8 +83,13 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_igtui_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_igtui_sext_store:
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: stw r3, 0(r5)
+; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i32 %a, %b
%sub = sext i1 %cmp to i32
@@ -85,10 +100,13 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_igtui_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_igtui_z_store:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: stw r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
@@ -100,11 +118,14 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_igtui_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_igtui_sext_z_store:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: neg r3, r3
-; CHECK: stw r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesigtus.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesigtus.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesigtus.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesigtus.ll Thu Aug 22 13:26:56 2019
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@@ -10,8 +11,9 @@
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_igtus:
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i16 %a, %b
@@ -22,8 +24,9 @@ entry:
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtus_sext(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_igtus_sext:
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i16 %a, %b
@@ -34,7 +37,8 @@ entry:
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtus_z(i16 zeroext %a) {
; CHECK-LABEL: test_igtus_z:
-; CHECK: cntlzw r3, r3
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
@@ -47,7 +51,8 @@ entry:
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtus_sext_z(i16 zeroext %a) {
; CHECK-LABEL: test_igtus_sext_z:
-; CHECK: cntlzw r3, r3
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
@@ -61,9 +66,13 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_igtus_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_igtus_store:
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
-; CHECK: blr
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: sth r3, 0(r5)
+; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i16 %a, %b
%conv3 = zext i1 %cmp to i16
@@ -74,9 +83,13 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_igtus_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_igtus_sext_store:
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
-; CHECK: blr
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: sth r3, 0(r5)
+; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i16 %a, %b
%conv3 = sext i1 %cmp to i16
@@ -87,10 +100,13 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_igtus_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_igtus_z_store:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: sth r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
@@ -102,11 +118,14 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_igtus_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_igtus_sext_z_store:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: neg r3, r3
-; CHECK: sth r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i16 %a, 0
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesileuc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesileuc.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesileuc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesileuc.ll Thu Aug 22 13:26:56 2019
@@ -1,117 +1,173 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileuc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_ileuc:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
-; CHECK-LABEL: test_ileuc:
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileuc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_ileuc_sext:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: addi r3, r3, -1
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i8 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
-; CHECK-LABEL: @test_ileuc_sext
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileuc_z(i8 zeroext %a) {
+; CHECK-LABEL: test_ileuc_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
-; CHECK-LABEL: test_ileuc_z:
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK: srwi r3, [[REG1]], 5
-; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileuc_sext_z(i8 zeroext %a) {
+; CHECK-LABEL: test_ileuc_sext_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i8 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
-; CHECK-LABEL: @test_ileuc_sext_z
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
-; CHECK-NEXT: neg r3, [[REG2]]
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileuc_store(i8 zeroext %a, i8 zeroext %b) {
+; BE-LABEL: test_ileuc_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r4, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: not r3, r3
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: stb r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_ileuc_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r4, r3
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: not r3, r3
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: stb r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob
ret void
-; CHECK-LABEL: test_ileuc_store:
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; BE-LABEL: test_ileuc_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r4, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: addi r3, r3, -1
+; BE-NEXT: stb r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_ileuc_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r4, r3
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: addi r3, r3, -1
+; LE-NEXT: stb r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob
ret void
-; CHECK-LABEL: @test_ileuc_sext_store
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK: stb [[REG3]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileuc_z_store(i8 zeroext %a) {
+; BE-LABEL: test_ileuc_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; BE-NEXT: cntlzw r3, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; BE-NEXT: srwi r3, r3, 5
+; BE-NEXT: stb r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_ileuc_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: cntlzw r3, r3
+; LE-NEXT: addis r4, r2, glob at toc@ha
+; LE-NEXT: srwi r3, r3, 5
+; LE-NEXT: stb r3, glob at toc@l(r4)
+; LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob
ret void
-; CHECK-LABEL: test_ileuc_z_store:
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK: srwi {{r[0-9]+}}, [[REG1]], 5
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileuc_sext_z_store(i8 zeroext %a) {
+; BE-LABEL: test_ileuc_sext_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; BE-NEXT: cntlzw r3, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; BE-NEXT: srwi r3, r3, 5
+; BE-NEXT: neg r3, r3
+; BE-NEXT: stb r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_ileuc_sext_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: cntlzw r3, r3
+; LE-NEXT: addis r4, r2, glob at toc@ha
+; LE-NEXT: srwi r3, r3, 5
+; LE-NEXT: neg r3, r3
+; LE-NEXT: stb r3, glob at toc@l(r4)
+; LE-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob
ret void
-; CHECK-LABEL: @test_ileuc_sext_z_store
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
-; CHECK: neg [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: stb [[REG3]]
-; CHECK: blr
}
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesileui.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesileui.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesileui.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesileui.ll Thu Aug 22 13:26:56 2019
@@ -1,117 +1,173 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_ileui:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i32 %a, %b
%sub = zext i1 %cmp to i32
ret i32 %sub
-; CHECK-LABEL: test_ileui:
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_ileui_sext:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: addi r3, r3, -1
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i32 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
-; CHECK-LABEL: @test_ileui_sext
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileui_z(i32 zeroext %a) {
+; CHECK-LABEL: test_ileui_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%sub = zext i1 %cmp to i32
ret i32 %sub
-; CHECK-LABEL: test_ileui_z:
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK: srwi r3, [[REG1]], 5
-; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileui_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_ileui_sext_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
-; CHECK-LABEL: @test_ileui_sext_z
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
-; CHECK-NEXT: neg r3, [[REG2]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileui_store(i32 zeroext %a, i32 zeroext %b) {
+; BE-LABEL: test_ileui_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r4, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: not r3, r3
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: stw r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_ileui_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r4, r3
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: not r3, r3
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: stw r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i32 %a, %b
%sub = zext i1 %cmp to i32
store i32 %sub, i32* @glob
ret void
-; CHECK-LABEL: test_ileui_store:
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; BE-LABEL: test_ileui_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r4, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: addi r3, r3, -1
+; BE-NEXT: stw r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_ileui_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r4, r3
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: addi r3, r3, -1
+; LE-NEXT: stw r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob
ret void
-; CHECK-LABEL: @test_ileui_sext_store
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK: stw [[REG3]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileui_z_store(i32 zeroext %a) {
+; BE-LABEL: test_ileui_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; BE-NEXT: cntlzw r3, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; BE-NEXT: srwi r3, r3, 5
+; BE-NEXT: stw r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_ileui_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: cntlzw r3, r3
+; LE-NEXT: addis r4, r2, glob at toc@ha
+; LE-NEXT: srwi r3, r3, 5
+; LE-NEXT: stw r3, glob at toc@l(r4)
+; LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%sub = zext i1 %cmp to i32
store i32 %sub, i32* @glob
ret void
-; CHECK-LABEL: test_ileui_z_store:
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK: srwi {{r[0-9]+}}, [[REG1]], 5
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileui_sext_z_store(i32 zeroext %a) {
+; BE-LABEL: test_ileui_sext_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; BE-NEXT: cntlzw r3, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; BE-NEXT: srwi r3, r3, 5
+; BE-NEXT: neg r3, r3
+; BE-NEXT: stw r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_ileui_sext_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: cntlzw r3, r3
+; LE-NEXT: addis r4, r2, glob at toc@ha
+; LE-NEXT: srwi r3, r3, 5
+; LE-NEXT: neg r3, r3
+; LE-NEXT: stw r3, glob at toc@l(r4)
+; LE-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob
ret void
-; CHECK-LABEL: @test_ileui_sext_z_store
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
-; CHECK: neg [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: stw [[REG3]]
-; CHECK: blr
}
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesileull.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesileull.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesileull.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesileull.ll Thu Aug 22 13:26:56 2019
@@ -1,115 +1,170 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileull(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ileull:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subfc r4, r3, r4
+; CHECK-NEXT: subfe r3, r3, r3
+; CHECK-NEXT: addi r3, r3, 1
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i64 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
-; CHECK-LABEL: test_ileull:
-; CHECK: subfc {{r[0-9]+}}, r3, r4
-; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r3, r3
-; CHECK-NEXT: addi r3, [[REG1]], 1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileull_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_ileull_sext:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subfc r4, r3, r4
+; CHECK-NEXT: subfe r3, r3, r3
+; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i64 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
-; CHECK-LABEL: @test_ileull_sext
-; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
-; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
-; CHECK: not r3, [[REG2]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileull_z(i64 %a) {
+; CHECK-LABEL: test_ileull_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzd r3, r3
+; CHECK-NEXT: rldicl r3, r3, 58, 63
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i64 %a, 0
%conv = zext i1 %cmp to i32
ret i32 %conv
-; CHECK-LABEL: test_ileull_z
-; CHECK: cntlzd [[REG1:r[0-9]+]], r3
-; CHECK-NEXT: rldicl r3, [[REG1]], 58, 63
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileull_sext_z(i64 %a) {
+; CHECK-LABEL: test_ileull_sext_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: subfe r3, r3, r3
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i64 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
-; CHECK-LABEL: @test_ileull_sext_z
-; CHECK: addic [[REG1:r[0-9]+]], r3, -1
-; CHECK: subfe r3, [[REG1]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileull_store(i64 %a, i64 %b) {
+; BE-LABEL: test_ileull_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: subfc r4, r3, r4
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: subfe r3, r3, r3
+; BE-NEXT: addi r3, r3, 1
+; BE-NEXT: std r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_ileull_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: subfc r4, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: subfe r3, r3, r3
+; LE-NEXT: addi r3, r3, 1
+; LE-NEXT: std r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
-; CHECK-LABEL: test_ileull_store:
-; CHECK: subfc {{r[0-9]+}}, r3, r4
-; CHECK: subfe [[REG1:r[0-9]+]], r3, r3
-; CHECK: addi {{r[0-9]+}}, [[REG1]], 1
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileull_sext_store(i64 %a, i64 %b) {
+; BE-LABEL: test_ileull_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: subfc r4, r3, r4
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: subfe r3, r3, r3
+; BE-NEXT: not r3, r3
+; BE-NEXT: std r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_ileull_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: subfc r4, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: subfe r3, r3, r3
+; LE-NEXT: not r3, r3
+; LE-NEXT: std r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
-; CHECK-LABEL: @test_ileull_sext_store
-; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
-; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
-; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: std [[REG3]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileull_z_store(i64 %a) {
+; BE-LABEL: test_ileull_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; BE-NEXT: cntlzd r3, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; BE-NEXT: rldicl r3, r3, 58, 63
+; BE-NEXT: std r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_ileull_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: cntlzd r3, r3
+; LE-NEXT: addis r4, r2, glob at toc@ha
+; LE-NEXT: rldicl r3, r3, 58, 63
+; LE-NEXT: std r3, glob at toc@l(r4)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
-; CHECK-LABEL: test_ileull_z_store:
-; CHECK: cntlzd [[REG1:r[0-9]+]], r3
-; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 58, 63
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileull_sext_z_store(i64 %a) {
+; BE-LABEL: test_ileull_sext_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; BE-NEXT: addic r3, r3, -1
+; BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; BE-NEXT: subfe r3, r3, r3
+; BE-NEXT: std r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_ileull_sext_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: addic r3, r3, -1
+; LE-NEXT: addis r4, r2, glob at toc@ha
+; LE-NEXT: subfe r3, r3, r3
+; LE-NEXT: std r3, glob at toc@l(r4)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i64 %a, 0
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
-; CHECK-LABEL: @test_ileull_sext_z_store
-; CHECK: addic [[REG1:r[0-9]+]], r3, -1
-; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
-; CHECK: std [[REG2]]
-; CHECK: blr
}
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesileus.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesileus.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesileus.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesileus.ll Thu Aug 22 13:26:56 2019
@@ -1,117 +1,173 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileus(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_ileus:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i16 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
-; CHECK-LABEL: test_ileus:
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileus_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_ileus_sext:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: addi r3, r3, -1
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i16 %a, %b
%sub = sext i1 %cmp to i32
ret i32 %sub
-; CHECK-LABEL: @test_ileus_sext
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileus_z(i16 zeroext %a) {
+; CHECK-LABEL: test_ileus_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i16 %a, 0
%conv1 = zext i1 %cmp to i32
ret i32 %conv1
-; CHECK-LABEL: test_ileus_z:
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK: srwi r3, [[REG1]], 5
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileus_sext_z(i16 zeroext %a) {
+; CHECK-LABEL: test_ileus_sext_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i16 %a, 0
%sub = sext i1 %cmp to i32
ret i32 %sub
-; CHECK-LABEL: @test_ileus_sext_z
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
-; CHECK-NEXT: neg r3, [[REG2]]
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileus_store(i16 zeroext %a, i16 zeroext %b) {
+; BE-LABEL: test_ileus_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r4, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: not r3, r3
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: sth r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_ileus_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r4, r3
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: not r3, r3
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: sth r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob
ret void
-; CHECK-LABEL: test_ileus_store:
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; BE-LABEL: test_ileus_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r4, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: addi r3, r3, -1
+; BE-NEXT: sth r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_ileus_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r4, r3
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: addi r3, r3, -1
+; LE-NEXT: sth r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob
ret void
-; CHECK-LABEL: @test_ileus_sext_store
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK: sth [[REG3]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileus_z_store(i16 zeroext %a) {
+; BE-LABEL: test_ileus_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; BE-NEXT: cntlzw r3, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; BE-NEXT: srwi r3, r3, 5
+; BE-NEXT: sth r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_ileus_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: cntlzw r3, r3
+; LE-NEXT: addis r4, r2, glob at toc@ha
+; LE-NEXT: srwi r3, r3, 5
+; LE-NEXT: sth r3, glob at toc@l(r4)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i16 %a, 0
%conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob
ret void
-; CHECK-LABEL: test_ileus_z_store:
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK: srwi {{r[0-9]+}}, [[REG1]], 5
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_ileus_sext_z_store(i16 zeroext %a) {
+; BE-LABEL: test_ileus_sext_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; BE-NEXT: cntlzw r3, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; BE-NEXT: srwi r3, r3, 5
+; BE-NEXT: neg r3, r3
+; BE-NEXT: sth r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_ileus_sext_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: cntlzw r3, r3
+; LE-NEXT: addis r4, r2, glob at toc@ha
+; LE-NEXT: srwi r3, r3, 5
+; LE-NEXT: neg r3, r3
+; LE-NEXT: sth r3, glob at toc@l(r4)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i16 %a, 0
%conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob
ret void
-; CHECK-LABEL: @test_ileus_sext_z_store
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
-; CHECK: neg [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: sth [[REG3]]
-; CHECK: blr
}
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesiltsc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesiltsc.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesiltsc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesiltsc.ll Thu Aug 22 13:26:56 2019
@@ -1,10 +1,12 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i8 0, align 1
@@ -12,8 +14,8 @@
define signext i32 @test_iltsc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_iltsc:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i8 %a, %b
@@ -25,8 +27,8 @@ entry:
define signext i32 @test_iltsc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_iltsc_sext:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i8 %a, %b
@@ -37,8 +39,9 @@ entry:
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltsc_sext_z(i8 signext %a) {
; CHECK-LABEL: test_iltsc_sext_z:
-; CHECK: srawi r3, r3, 31
-; CHECK-NEXT: blr
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: srawi r3, r3, 31
+; CHECK-NEXT: blr
entry:
%cmp = icmp slt i8 %a, 0
%sub = sext i1 %cmp to i32
@@ -47,10 +50,22 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_iltsc_store(i8 signext %a, i8 signext %b) {
-; CHECK-LABEL: test_iltsc_store:
-; CHECK: # %bb.0: # %entry
-; CHECK: sub [[REG:r[0-9]+]], r3, r4
-; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; BE-LABEL: test_iltsc_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r5, .LC0 at toc@l(r5)
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: stb r3, 0(r5)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_iltsc_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: stb r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp slt i8 %a, %b
%conv3 = zext i1 %cmp to i8
@@ -60,10 +75,22 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_iltsc_sext_store(i8 signext %a, i8 signext %b) {
-; CHECK-LABEL: test_iltsc_sext_store:
-; CHECK: # %bb.0: # %entry
-; CHECK: sub [[REG:r[0-9]+]], r3, r4
-; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+; BE-LABEL: test_iltsc_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r5, .LC0 at toc@l(r5)
+; BE-NEXT: sradi r3, r3, 63
+; BE-NEXT: stb r3, 0(r5)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_iltsc_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: sradi r3, r3, 63
+; LE-NEXT: stb r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp slt i8 %a, %b
%conv3 = sext i1 %cmp to i8
@@ -73,8 +100,20 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_iltsc_sext_z_store(i8 signext %a) {
-; CHECK-LABEL: test_iltsc_sext_z_store:
-; CHECK: srwi {{r[0-9]+}}, r3, 7
+; BE-LABEL: test_iltsc_sext_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; BE-NEXT: srwi r3, r3, 7
+; BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; BE-NEXT: stb r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_iltsc_sext_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: addis r4, r2, glob at toc@ha
+; LE-NEXT: srwi r3, r3, 7
+; LE-NEXT: stb r3, glob at toc@l(r4)
+; LE-NEXT: blr
entry:
%cmp = icmp slt i8 %a, 0
%conv2 = sext i1 %cmp to i8
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesiltsi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesiltsi.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesiltsi.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesiltsi.ll Thu Aug 22 13:26:56 2019
@@ -1,10 +1,12 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i32 0, align 4
@@ -12,8 +14,8 @@
define signext i32 @test_iltsi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_iltsi:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i32 %a, %b
@@ -25,8 +27,8 @@ entry:
define signext i32 @test_iltsi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_iltsi_sext:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i32 %a, %b
@@ -48,10 +50,22 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_iltsi_store(i32 signext %a, i32 signext %b) {
-; CHECK-LABEL: test_iltsi_store:
-; CHECK: # %bb.0: # %entry
-; CHECK: sub [[REG:r[0-9]+]], r3, r4
-; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; BE-LABEL: test_iltsi_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r5, .LC0 at toc@l(r5)
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: stw r3, 0(r5)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_iltsi_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: stw r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp slt i32 %a, %b
%conv = zext i1 %cmp to i32
@@ -61,10 +75,22 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_iltsi_sext_store(i32 signext %a, i32 signext %b) {
-; CHECK-LABEL: test_iltsi_sext_store:
-; CHECK: # %bb.0: # %entry
-; CHECK: sub [[REG:r[0-9]+]], r3, r4
-; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+; BE-LABEL: test_iltsi_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r5, .LC0 at toc@l(r5)
+; BE-NEXT: sradi r3, r3, 63
+; BE-NEXT: stw r3, 0(r5)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_iltsi_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: sradi r3, r3, 63
+; LE-NEXT: stw r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp slt i32 %a, %b
%sub = sext i1 %cmp to i32
@@ -74,9 +100,20 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_iltsi_sext_z_store(i32 signext %a) {
-; CHECK-LABEL: test_iltsi_sext_z_store:
-; CHECK: srawi {{r[0-9]+}}, r3, 31
-; CHECK: blr
+; BE-LABEL: test_iltsi_sext_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; BE-NEXT: srawi r3, r3, 31
+; BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; BE-NEXT: stw r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_iltsi_sext_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: addis r4, r2, glob at toc@ha
+; LE-NEXT: srawi r3, r3, 31
+; LE-NEXT: stw r3, glob at toc@l(r4)
+; LE-NEXT: blr
entry:
%cmp = icmp slt i32 %a, 0
%sub = sext i1 %cmp to i32
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesiltsll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesiltsll.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesiltsll.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesiltsll.ll Thu Aug 22 13:26:56 2019
@@ -1,10 +1,12 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i64 0, align 8
@@ -12,11 +14,11 @@
define signext i32 @test_iltsll(i64 %a, i64 %b) {
; CHECK-LABEL: test_iltsll:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63
-; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3
-; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK-NEXT: xori r3, [[REG4]], 1
+; CHECK-NEXT: sradi r5, r3, 63
+; CHECK-NEXT: rldicl r6, r4, 1, 63
+; CHECK-NEXT: subfc r3, r4, r3
+; CHECK-NEXT: adde r3, r6, r5
+; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, %b
@@ -28,12 +30,12 @@ entry:
define signext i32 @test_iltsll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_iltsll_sext:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63
-; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3
-; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1
-; CHECK-NEXT: neg r3, [[REG5]]
+; CHECK-NEXT: sradi r5, r3, 63
+; CHECK-NEXT: rldicl r6, r4, 1, 63
+; CHECK-NEXT: subfc r3, r4, r3
+; CHECK-NEXT: adde r3, r6, r5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, %b
@@ -55,14 +57,29 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_iltsll_store(i64 %a, i64 %b) {
-; CHECK-LABEL: test_iltsll_store:
-; CHECK: # %bb.0: # %entry
-; CHECK: sradi [[REG1:r[0-9]+]], r3, 63
-; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63
+; BE-LABEL: test_iltsll_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: sradi r6, r3, 63
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: subfc r3, r4, r3
+; BE-NEXT: rldicl r3, r4, 1, 63
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: adde r3, r3, r6
+; BE-NEXT: xori r3, r3, 1
+; BE-NEXT: std r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_iltsll_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sradi r6, r3, 63
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: subfc r3, r4, r3
+; LE-NEXT: rldicl r3, r4, 1, 63
+; LE-NEXT: adde r3, r3, r6
+; LE-NEXT: xori r3, r3, 1
+; LE-NEXT: std r3, glob at toc@l(r5)
+; LE-NEXT: blr
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3
-; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
-; CHECK-NOT: neg {{r[0-9]+}}, [[REG5]]
entry:
%cmp = icmp slt i64 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -72,14 +89,31 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_iltsll_sext_store(i64 %a, i64 %b) {
-; CHECK-LABEL: test_iltsll_sext_store:
-; CHECK: # %bb.0: # %entry
-; CHECK: sradi [[REG1:r[0-9]+]], r3, 63
-; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63
+; BE-LABEL: test_iltsll_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: sradi r6, r3, 63
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: subfc r3, r4, r3
+; BE-NEXT: rldicl r3, r4, 1, 63
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: adde r3, r3, r6
+; BE-NEXT: xori r3, r3, 1
+; BE-NEXT: neg r3, r3
+; BE-NEXT: std r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_iltsll_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sradi r6, r3, 63
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: subfc r3, r4, r3
+; LE-NEXT: rldicl r3, r4, 1, 63
+; LE-NEXT: adde r3, r3, r6
+; LE-NEXT: xori r3, r3, 1
+; LE-NEXT: neg r3, r3
+; LE-NEXT: std r3, glob at toc@l(r5)
+; LE-NEXT: blr
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3
-; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
-; CHECK: neg {{r[0-9]+}}, [[REG5]]
entry:
%cmp = icmp slt i64 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -89,8 +123,20 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_iltsll_sext_z_store(i64 %a) {
-; CHECK-LABEL: test_iltsll_sext_z_store:
-; CHECK: sradi r3, r3, 63
+; BE-LABEL: test_iltsll_sext_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; BE-NEXT: sradi r3, r3, 63
+; BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; BE-NEXT: std r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_iltsll_sext_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: addis r4, r2, glob at toc@ha
+; LE-NEXT: sradi r3, r3, 63
+; LE-NEXT: std r3, glob at toc@l(r4)
+; LE-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 0
%conv2 = sext i1 %cmp to i64
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesiltss.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesiltss.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesiltss.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesiltss.ll Thu Aug 22 13:26:56 2019
@@ -1,10 +1,12 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i16 0, align 2
@@ -12,8 +14,8 @@
define signext i32 @test_iltss(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iltss:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i16 %a, %b
@@ -25,8 +27,8 @@ entry:
define signext i32 @test_iltss_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iltss_sext:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i16 %a, %b
@@ -37,8 +39,9 @@ entry:
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltss_sext_z(i16 signext %a) {
; CHECK-LABEL: test_iltss_sext_z:
-; CHECK: srawi r3, r3, 31
-; CHECK-NEXT: blr
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: srawi r3, r3, 31
+; CHECK-NEXT: blr
entry:
%cmp = icmp slt i16 %a, 0
%sub = sext i1 %cmp to i32
@@ -47,10 +50,22 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_iltss_store(i16 signext %a, i16 signext %b) {
-; CHECK-LABEL: test_iltss_store:
-; CHECK: # %bb.0: # %entry
-; CHECK: sub [[REG:r[0-9]+]], r3, r4
-; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; BE-LABEL: test_iltss_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r5, .LC0 at toc@l(r5)
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: sth r3, 0(r5)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_iltss_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: sth r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp slt i16 %a, %b
%conv3 = zext i1 %cmp to i16
@@ -60,10 +75,22 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_iltss_sext_store(i16 signext %a, i16 signext %b) {
-; CHECK-LABEL: test_iltss_sext_store:
-; CHECK: # %bb.0: # %entry
-; CHECK: sub [[REG:r[0-9]+]], r3, r4
-; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+; BE-LABEL: test_iltss_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r5, .LC0 at toc@l(r5)
+; BE-NEXT: sradi r3, r3, 63
+; BE-NEXT: sth r3, 0(r5)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_iltss_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: sradi r3, r3, 63
+; LE-NEXT: sth r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp slt i16 %a, %b
%conv3 = sext i1 %cmp to i16
@@ -73,8 +100,20 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_iltss_sext_z_store(i16 signext %a) {
-; CHECK-LABEL: test_iltss_sext_z_store:
-; CHECK: srwi {{r[0-9]+}}, r3, 15
+; BE-LABEL: test_iltss_sext_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; BE-NEXT: srwi r3, r3, 15
+; BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; BE-NEXT: sth r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_iltss_sext_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: addis r4, r2, glob at toc@ha
+; LE-NEXT: srwi r3, r3, 15
+; LE-NEXT: sth r3, glob at toc@l(r4)
+; LE-NEXT: blr
entry:
%cmp = icmp slt i16 %a, 0
%sub = sext i1 %cmp to i16
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesiltuc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesiltuc.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesiltuc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesiltuc.ll Thu Aug 22 13:26:56 2019
@@ -1,17 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_iltuc:
-; CHECK: sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i8 %a, %b
@@ -22,8 +26,9 @@ entry:
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltuc_sext(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_iltuc_sext:
-; CHECK: sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i8 %a, %b
@@ -33,9 +38,22 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_iltuc_store(i8 zeroext %a, i8 zeroext %b) {
-; CHECK-LABEL: test_iltuc_store:
-; CHECK: sub [[REG:r[2-9]+]], r3, r4
-; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; BE-LABEL: test_iltuc_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r5, .LC0 at toc@l(r5)
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: stb r3, 0(r5)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_iltuc_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: stb r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ult i8 %a, %b
%conv3 = zext i1 %cmp to i8
@@ -45,9 +63,22 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_iltuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
-; CHECK-LABEL: test_iltuc_sext_store:
-; CHECK: sub [[REG:r[0-9]+]], r3, r4
-; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+; BE-LABEL: test_iltuc_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r5, .LC0 at toc@l(r5)
+; BE-NEXT: sradi r3, r3, 63
+; BE-NEXT: stb r3, 0(r5)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_iltuc_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: sradi r3, r3, 63
+; LE-NEXT: stb r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ult i8 %a, %b
%conv3 = sext i1 %cmp to i8
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesiltui.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesiltui.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesiltui.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesiltui.ll Thu Aug 22 13:26:56 2019
@@ -1,17 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_iltui:
-; CHECK: sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i32 %a, %b
@@ -22,8 +26,9 @@ entry:
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltui_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_iltui_sext:
-; CHECK: sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i32 %a, %b
@@ -33,9 +38,22 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_iltui_store(i32 zeroext %a, i32 zeroext %b) {
-; CHECK-LABEL: test_iltui_store:
-; CHECK: sub [[REG:r[2-9]+]], r3, r4
-; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; BE-LABEL: test_iltui_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r5, .LC0 at toc@l(r5)
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: stw r3, 0(r5)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_iltui_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: stw r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ult i32 %a, %b
%conv = zext i1 %cmp to i32
@@ -45,9 +63,22 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_iltui_sext_store(i32 zeroext %a, i32 zeroext %b) {
-; CHECK-LABEL: test_iltui_sext_store:
-; CHECK: sub [[REG:r[0-9]+]], r3, r4
-; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+; BE-LABEL: test_iltui_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r5, .LC0 at toc@l(r5)
+; BE-NEXT: sradi r3, r3, 63
+; BE-NEXT: stw r3, 0(r5)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_iltui_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: sradi r3, r3, 63
+; LE-NEXT: stw r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ult i32 %a, %b
%sub = sext i1 %cmp to i32
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesiltus.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesiltus.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesiltus.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesiltus.ll Thu Aug 22 13:26:56 2019
@@ -1,17 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iltus:
-; CHECK: sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i16 %a, %b
@@ -22,8 +26,9 @@ entry:
; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltus_sext(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iltus_sext:
-; CHECK: sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i16 %a, %b
@@ -33,9 +38,22 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_iltus_store(i16 zeroext %a, i16 zeroext %b) {
-; CHECK-LABEL: test_iltus_store:
-; CHECK: sub [[REG:r[2-9]+]], r3, r4
-; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; BE-LABEL: test_iltus_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r5, .LC0 at toc@l(r5)
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: sth r3, 0(r5)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_iltus_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: sth r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ult i16 %a, %b
%conv3 = zext i1 %cmp to i16
@@ -45,9 +63,22 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_iltus_sext_store(i16 zeroext %a, i16 zeroext %b) {
-; CHECK-LABEL: test_iltus_sext_store:
-; CHECK: sub [[REG:r[0-9]+]], r3, r4
-; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+; BE-LABEL: test_iltus_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r5, .LC0 at toc@l(r5)
+; BE-NEXT: sradi r3, r3, 63
+; BE-NEXT: sth r3, 0(r5)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_iltus_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: sradi r3, r3, 63
+; LE-NEXT: sth r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ult i16 %a, %b
%conv3 = sext i1 %cmp to i16
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgeuc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgeuc.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgeuc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgeuc.ll Thu Aug 22 13:26:56 2019
@@ -1,112 +1,165 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeuc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llgeuc:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i8 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
-; CHECK-LABEL: test_llgeuc:
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeuc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llgeuc_sext:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: addi r3, r3, -1
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i8 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
-; CHECK-LABEL: @test_llgeuc_sext
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeuc_z(i8 zeroext %a) {
+; CHECK-LABEL: test_llgeuc_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li r3, 1
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i8 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
-; CHECK-LABEL: @test_llgeuc_z
-; CHECK: li r3, 1
-; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeuc_sext_z(i8 zeroext %a) {
+; CHECK-LABEL: test_llgeuc_sext_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li r3, -1
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i8 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
-; CHECK-LABEL: @test_llgeuc_sext_z
-; CHECK: li r3, -1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeuc_store(i8 zeroext %a, i8 zeroext %b) {
+; BE-LABEL: test_llgeuc_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: not r3, r3
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: stb r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llgeuc_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: not r3, r3
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: stb r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob
ret void
; CHECK_LABEL: test_llgeuc_store:
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; BE-LABEL: test_llgeuc_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: addi r3, r3, -1
+; BE-NEXT: stb r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llgeuc_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: addi r3, r3, -1
+; LE-NEXT: stb r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob
ret void
-; CHECK-LABEL: @test_llgeuc_sext_store
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK: stb [[REG3]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeuc_z_store(i8 zeroext %a) {
+; BE-LABEL: test_llgeuc_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r3, r2, .LC0 at toc@ha
+; BE-NEXT: li r4, 1
+; BE-NEXT: ld r3, .LC0 at toc@l(r3)
+; BE-NEXT: stb r4, 0(r3)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llgeuc_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: addis r3, r2, glob at toc@ha
+; LE-NEXT: li r4, 1
+; LE-NEXT: stb r4, glob at toc@l(r3)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i8 %a, 0
%conv1 = zext i1 %cmp to i8
store i8 %conv1, i8* @glob
ret void
-; CHECK-LABEL: @test_llgeuc_z_store
-; CHECK: li [[REG1:r[0-9]+]], 1
-; CHECK: stb [[REG1]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeuc_sext_z_store(i8 zeroext %a) {
+; BE-LABEL: test_llgeuc_sext_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r3, r2, .LC0 at toc@ha
+; BE-NEXT: li r4, -1
+; BE-NEXT: ld r3, .LC0 at toc@l(r3)
+; BE-NEXT: stb r4, 0(r3)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llgeuc_sext_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: addis r3, r2, glob at toc@ha
+; LE-NEXT: li r4, -1
+; LE-NEXT: stb r4, glob at toc@l(r3)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i8 %a, 0
%conv1 = sext i1 %cmp to i8
store i8 %conv1, i8* @glob
ret void
-; CHECK-LABEL: @test_llgeuc_sext_z_store
-; CHECK: li [[REG1:r[0-9]+]], -1
-; CHECK: stb [[REG1]]
-; CHECK: blr
}
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgeui.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgeui.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgeui.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgeui.ll Thu Aug 22 13:26:56 2019
@@ -1,112 +1,165 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llgeui:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i32 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
-; CHECK-LABEL: test_llgeui:
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llgeui_sext:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: addi r3, r3, -1
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i32 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
-; CHECK-LABEL: @test_llgeui_sext
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeui_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llgeui_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li r3, 1
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i32 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
-; CHECK-LABEL: @test_llgeui_z
-; CHECK: li r3, 1
-; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeui_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llgeui_sext_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li r3, -1
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i32 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
-; CHECK-LABEL: @test_llgeui_sext_z
-; CHECK: li r3, -1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeui_store(i32 zeroext %a, i32 zeroext %b) {
+; BE-LABEL: test_llgeui_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: not r3, r3
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: stw r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llgeui_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: not r3, r3
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: stw r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob
ret void
; CHECK_LABEL: test_igeuc_store:
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; BE-LABEL: test_llgeui_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: addi r3, r3, -1
+; BE-NEXT: stw r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llgeui_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: addi r3, r3, -1
+; LE-NEXT: stw r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob
ret void
-; CHECK-LABEL: @test_llgeui_sext_store
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK: stw [[REG3]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeui_z_store(i32 zeroext %a) {
+; BE-LABEL: test_llgeui_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r3, r2, .LC0 at toc@ha
+; BE-NEXT: li r4, 1
+; BE-NEXT: ld r3, .LC0 at toc@l(r3)
+; BE-NEXT: stw r4, 0(r3)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llgeui_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: addis r3, r2, glob at toc@ha
+; LE-NEXT: li r4, 1
+; LE-NEXT: stw r4, glob at toc@l(r3)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i32 %a, 0
%sub = zext i1 %cmp to i32
store i32 %sub, i32* @glob
ret void
-; CHECK-LABEL: @test_llgeui_z_store
-; CHECK: li [[REG1:r[0-9]+]], 1
-; CHECK: stw [[REG1]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeui_sext_z_store(i32 zeroext %a) {
+; BE-LABEL: test_llgeui_sext_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r3, r2, .LC0 at toc@ha
+; BE-NEXT: li r4, -1
+; BE-NEXT: ld r3, .LC0 at toc@l(r3)
+; BE-NEXT: stw r4, 0(r3)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llgeui_sext_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: addis r3, r2, glob at toc@ha
+; LE-NEXT: li r4, -1
+; LE-NEXT: stw r4, glob at toc@l(r3)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i32 %a, 0
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob
ret void
-; CHECK-LABEL: @test_llgeui_sext_z_store
-; CHECK: li [[REG1:r[0-9]+]], -1
-; CHECK: stw [[REG1]]
-; CHECK: blr
}
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgeull.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgeull.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgeull.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgeull.ll Thu Aug 22 13:26:56 2019
@@ -1,110 +1,162 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeull(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgeull:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subfc r3, r4, r3
+; CHECK-NEXT: subfe r3, r4, r4
+; CHECK-NEXT: addi r3, r3, 1
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i64 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
-; CHECK-LABEL: test_llgeull:
-; CHECK: subfc {{r[0-9]+}}, r4, r3
-; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r4, r4
-; CHECK-NEXT: addi r3, [[REG1]], 1
-; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeull_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llgeull_sext:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subfc r3, r4, r3
+; CHECK-NEXT: subfe r3, r4, r4
+; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i64 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
-; CHECK-LABEL: @test_llgeull_sext
-; CHECK: subfc [[REG1:r[0-9]+]], r4, r3
-; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
-; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeull_z(i64 %a) {
+; CHECK-LABEL: test_llgeull_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li r3, 1
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i64 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
-; CHECK-LABEL: @test_llgeull_z
-; CHECK: li r3, 1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeull_sext_z(i64 %a) {
+; CHECK-LABEL: test_llgeull_sext_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li r3, -1
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i64 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
-; CHECK-LABEL: @test_llgeull_sext_z
-; CHECK: li r3, -1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeull_store(i64 %a, i64 %b) {
+; BE-LABEL: test_llgeull_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: subfc r3, r4, r3
+; BE-NEXT: ld r3, .LC0 at toc@l(r5)
+; BE-NEXT: subfe r4, r4, r4
+; BE-NEXT: addi r4, r4, 1
+; BE-NEXT: std r4, 0(r3)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llgeull_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: subfc r3, r4, r3
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: subfe r3, r4, r4
+; LE-NEXT: addi r3, r3, 1
+; LE-NEXT: std r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
-; CHECK-LABEL: test_llgeull_store:
-; CHECK: subfc {{r[0-9]+}}, r4, r3
-; CHECK: subfe [[REG1:r[0-9]+]], r4, r4
-; CHECK: addi {{r[0-9]+}}, [[REG1]], 1
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeull_sext_store(i64 %a, i64 %b) {
+; BE-LABEL: test_llgeull_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: subfc r3, r4, r3
+; BE-NEXT: ld r3, .LC0 at toc@l(r5)
+; BE-NEXT: subfe r4, r4, r4
+; BE-NEXT: not r4, r4
+; BE-NEXT: std r4, 0(r3)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llgeull_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: subfc r3, r4, r3
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: subfe r3, r4, r4
+; LE-NEXT: not r3, r3
+; LE-NEXT: std r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
-; CHECK-LABEL: @test_llgeull_sext_store
-; CHECK: subfc [[REG1:r[0-9]+]], r4, r3
-; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
-; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: std [[REG3]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeull_z_store(i64 %a) {
+; BE-LABEL: test_llgeull_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r3, r2, .LC0 at toc@ha
+; BE-NEXT: li r4, 1
+; BE-NEXT: ld r3, .LC0 at toc@l(r3)
+; BE-NEXT: std r4, 0(r3)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llgeull_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: addis r3, r2, glob at toc@ha
+; LE-NEXT: li r4, 1
+; LE-NEXT: std r4, glob at toc@l(r3)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
-; CHECK-LABEL: @test_llgeull_z_store
-; CHECK: li [[REG1:r[0-9]+]], 1
-; CHECK: std [[REG1]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeull_sext_z_store(i64 %a) {
+; BE-LABEL: test_llgeull_sext_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r3, r2, .LC0 at toc@ha
+; BE-NEXT: li r4, -1
+; BE-NEXT: ld r3, .LC0 at toc@l(r3)
+; BE-NEXT: std r4, 0(r3)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llgeull_sext_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: addis r3, r2, glob at toc@ha
+; LE-NEXT: li r4, -1
+; LE-NEXT: std r4, glob at toc@l(r3)
+; LE-NEXT: blr
entry:
store i64 -1, i64* @glob
ret void
-; CHECK-LABEL: @test_llgeull_sext_z_store
-; CHECK: li [[REG1:r[0-9]+]], -1
-; CHECK: std [[REG1]]
-; CHECK: blr
}
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgeus.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgeus.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgeus.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgeus.ll Thu Aug 22 13:26:56 2019
@@ -1,112 +1,165 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeus(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llgeus:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i16 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
-; CHECK-LABEL: test_llgeus:
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeus_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llgeus_sext:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: addi r3, r3, -1
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i16 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
-; CHECK-LABEL: @test_llgeus_sext
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeus_z(i16 zeroext %a) {
+; CHECK-LABEL: test_llgeus_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li r3, 1
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i16 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
-; CHECK-LABEL: @test_llgeus_z
-; CHECK: li r3, 1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeus_sext_z(i16 zeroext %a) {
+; CHECK-LABEL: test_llgeus_sext_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: li r3, -1
+; CHECK-NEXT: blr
entry:
%cmp = icmp uge i16 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
-; CHECK-LABEL: @test_llgeus_sext_z
-; CHECK: li r3, -1
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeus_store(i16 zeroext %a, i16 zeroext %b) {
+; BE-LABEL: test_llgeus_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: not r3, r3
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: sth r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llgeus_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: not r3, r3
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: sth r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob
ret void
; CHECK_LABEL: test_llgeus_store:
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; BE-LABEL: test_llgeus_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: addi r3, r3, -1
+; BE-NEXT: sth r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llgeus_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: addi r3, r3, -1
+; LE-NEXT: sth r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob
ret void
-; CHECK-LABEL: @test_llgeus_sext_store
-; CHECK: sub [[REG1:r[0-9]+]], r3, r4
-; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK: sth [[REG3]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeus_z_store(i16 zeroext %a) {
+; BE-LABEL: test_llgeus_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r3, r2, .LC0 at toc@ha
+; BE-NEXT: li r4, 1
+; BE-NEXT: ld r3, .LC0 at toc@l(r3)
+; BE-NEXT: sth r4, 0(r3)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llgeus_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: addis r3, r2, glob at toc@ha
+; LE-NEXT: li r4, 1
+; LE-NEXT: sth r4, glob at toc@l(r3)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i16 %a, 0
%conv1 = zext i1 %cmp to i16
store i16 %conv1, i16* @glob
ret void
-; CHECK-LABEL: @test_llgeus_z_store
-; CHECK: li [[REG1:r[0-9]+]], 1
-; CHECK: sth [[REG1]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeus_sext_z_store(i16 zeroext %a) {
+; BE-LABEL: test_llgeus_sext_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r3, r2, .LC0 at toc@ha
+; BE-NEXT: li r4, -1
+; BE-NEXT: ld r3, .LC0 at toc@l(r3)
+; BE-NEXT: sth r4, 0(r3)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llgeus_sext_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: addis r3, r2, glob at toc@ha
+; LE-NEXT: li r4, -1
+; LE-NEXT: sth r4, glob at toc@l(r3)
+; LE-NEXT: blr
entry:
%cmp = icmp uge i16 %a, 0
%conv1 = sext i1 %cmp to i16
store i16 %conv1, i16* @glob
ret void
-; CHECK-LABEL: @test_llgeus_sext_z_store
-; CHECK: li [[REG1:r[0-9]+]], -1
-; CHECK: sth [[REG1]]
-; CHECK: blr
}
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgtsll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgtsll.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgtsll.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgtsll.ll Thu Aug 22 13:26:56 2019
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@@ -11,11 +12,11 @@
define i64 @test_llgtsll(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgtsll:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63
-; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4
-; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK-NEXT: xori r3, [[REG4]], 1
+; CHECK-NEXT: sradi r5, r4, 63
+; CHECK-NEXT: rldicl r6, r3, 1, 63
+; CHECK-NEXT: subfc r3, r3, r4
+; CHECK-NEXT: adde r3, r6, r5
+; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, %b
@@ -27,12 +28,12 @@ entry:
define i64 @test_llgtsll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgtsll_sext:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r4, 63
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r3, 1, 63
-; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r3, r4
-; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1
-; CHECK-NEXT: neg r3, [[REG5]]
+; CHECK-NEXT: sradi r5, r4, 63
+; CHECK-NEXT: rldicl r6, r3, 1, 63
+; CHECK-NEXT: subfc r3, r3, r4
+; CHECK-NEXT: adde r3, r6, r5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, %b
@@ -58,9 +59,11 @@ entry:
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtsll_sext_z(i64 %a) {
; CHECK-LABEL: test_llgtsll_sext_z:
-; CHECK: addi [[REG1:r[0-9]+]], r3, -1
-; CHECK-NEXT: nor [[REG2:r[0-9]+]], [[REG1]], r3
-; CHECK-NEXT: sradi r3, [[REG2]], 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addi r4, r3, -1
+; CHECK-NEXT: nor r3, r4, r3
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, 0
%conv1 = sext i1 %cmp to i64
@@ -71,12 +74,16 @@ entry:
define void @test_llgtsll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgtsll_store:
; CHECK: # %bb.0: # %entry
-; CHECK: sradi [[REG1:r[0-9]+]], r4, 63
-; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63
+; CHECK-NEXT: sradi r6, r4, 63
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: subfc r4, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: adde r3, r3, r6
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4
-; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
-; CHECK-NOT: neg
entry:
%cmp = icmp sgt i64 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -88,12 +95,17 @@ entry:
define void @test_llgtsll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgtsll_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK: sradi [[REG1:r[0-9]+]], r4, 63
-; CHECK: rldicl [[REG2:r[0-9]+]], r3, 1, 63
+; CHECK-NEXT: sradi r6, r4, 63
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: subfc r4, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: adde r3, r3, r6
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r5)
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4
-; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
-; CHECK: neg {{r[0-9]+}}, [[REG5]]
entry:
%cmp = icmp sgt i64 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -123,9 +135,14 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_llgtsll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_llgtsll_sext_z_store:
-; CHECK: addi [[REG1:r[0-9]+]], r3, -1
-; CHECK: nor [[REG2:r[0-9]+]], [[REG1]], r3
-; CHECK: sradi [[REG3:r[0-9]+]], [[REG2]], 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: addi r5, r3, -1
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: nor r3, r5, r3
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: std r3, 0(r4)
+; CHECK-NEXT: blr
entry:
%cmp = icmp sgt i64 %a, 0
%conv1 = sext i1 %cmp to i64
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgtuc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgtuc.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgtuc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgtuc.ll Thu Aug 22 13:26:56 2019
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@@ -10,8 +11,9 @@
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llgtuc:
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK: rldicl r3, [[REG]], 1, 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i8 %a, %b
@@ -22,8 +24,9 @@ entry:
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtuc_sext(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llgtuc_sext:
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK: sradi r3, [[REG]], 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i8 %a, %b
@@ -34,9 +37,10 @@ entry:
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtuc_z(i8 zeroext %a) {
; CHECK-LABEL: test_llgtuc_z:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
@@ -47,10 +51,11 @@ entry:
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtuc_sext_z(i8 zeroext %a) {
; CHECK-LABEL: test_llgtuc_sext_z:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: neg r3, r3
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
@@ -61,8 +66,13 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_llgtuc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llgtuc_store:
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: stb r3, 0(r5)
+; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i8 %a, %b
%conv3 = zext i1 %cmp to i8
@@ -73,8 +83,13 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_llgtuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llgtuc_sext_store:
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: stb r3, 0(r5)
+; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i8 %a, %b
%conv3 = sext i1 %cmp to i8
@@ -85,10 +100,13 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_llgtuc_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_llgtuc_z_store:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: stb r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
@@ -100,11 +118,14 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_llgtuc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_llgtuc_sext_z_store:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: neg r3, r3
-; CHECK: stb r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i8 %a, 0
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgtui.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgtui.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgtui.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgtui.ll Thu Aug 22 13:26:56 2019
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@@ -10,9 +11,10 @@
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llgtui:
-; CHECK-NOT: clrldi
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i32 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -22,8 +24,9 @@ entry:
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtui_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llgtui_sext:
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i32 %a, %b
@@ -34,7 +37,8 @@ entry:
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtui_z(i32 zeroext %a) {
; CHECK-LABEL: test_llgtui_z:
-; CHECK: cntlzw r3, r3
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
@@ -47,7 +51,8 @@ entry:
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtui_sext_z(i32 zeroext %a) {
; CHECK-LABEL: test_llgtui_sext_z:
-; CHECK: cntlzw r3, r3
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3
@@ -61,8 +66,13 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_llgtui_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llgtui_store:
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: stw r3, 0(r5)
+; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i32 %a, %b
%conv = zext i1 %cmp to i32
@@ -73,8 +83,13 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_llgtui_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llgtui_sext_store:
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: stw r3, 0(r5)
+; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i32 %a, %b
%sub = sext i1 %cmp to i32
@@ -85,10 +100,13 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_llgtui_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_llgtui_z_store:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: stw r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
@@ -100,11 +118,14 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_llgtui_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_llgtui_sext_z_store:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: xori r3, r3, 1
-; CHECK: neg r3, r3
-; CHECK: stw r3, 0(r4)
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addis r4, r2, .LC0 at toc@ha
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: ld r4, .LC0 at toc@l(r4)
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ne i32 %a, 0
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllgtus.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllgtus.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllgtus.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllgtus.ll Thu Aug 22 13:26:56 2019
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@@ -11,8 +12,8 @@
define i64 @test_llgtus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llgtus:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i16 %a, %b
@@ -24,8 +25,8 @@ entry:
define i64 @test_llgtus_sext(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llgtus_sext:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3
-; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i16 %a, %b
@@ -66,8 +67,12 @@ entry:
define void @test_llgtus_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llgtus_store:
; CHECK: # %bb.0: # %entry
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: sth r3, 0(r5)
+; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i16 %a, %b
%conv3 = zext i1 %cmp to i16
@@ -79,8 +84,12 @@ entry:
define void @test_llgtus_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llgtus_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK: sub [[REG:r[0-9]+]], r4, r3
-; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: sth r3, 0(r5)
+; CHECK-NEXT: blr
entry:
%cmp = icmp ugt i16 %a, %b
%conv3 = sext i1 %cmp to i16
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllleuc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllleuc.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllleuc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllleuc.ll Thu Aug 22 13:26:56 2019
@@ -1,116 +1,172 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleuc(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llleuc:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i8 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
-; CHECK-LABEL: test_llleuc:
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleuc_sext(i8 zeroext %a, i8 zeroext %b) {
+; CHECK-LABEL: test_llleuc_sext:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: addi r3, r3, -1
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i8 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
-; CHECK-LABEL: @test_llleuc_sext
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleuc_z(i8 zeroext %a) {
+; CHECK-LABEL: test_llleuc_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i8 %a, 0
%conv2 = zext i1 %cmp to i64
ret i64 %conv2
-; CHECK-LABEL: test_llleuc_z:
-; CHECK: cntlzw r3, r3
-; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleuc_sext_z(i8 zeroext %a) {
+; CHECK-LABEL: test_llleuc_sext_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i8 %a, 0
%conv2 = sext i1 %cmp to i64
ret i64 %conv2
-; CHECK-LABEL: @test_llleuc_sext_z
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
-; CHECK-NEXT: neg r3, [[REG2]]
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleuc_store(i8 zeroext %a, i8 zeroext %b) {
+; BE-LABEL: test_llleuc_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r4, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: not r3, r3
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: stb r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llleuc_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r4, r3
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: not r3, r3
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: stb r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i8 %a, %b
%conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob
ret void
-; CHECK-LABEL: test_llleuc_store:
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
+; BE-LABEL: test_llleuc_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r4, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: addi r3, r3, -1
+; BE-NEXT: stb r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llleuc_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r4, r3
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: addi r3, r3, -1
+; LE-NEXT: stb r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i8 %a, %b
%conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob
ret void
-; CHECK-LABEL: @test_llleuc_sext_store
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK: stb [[REG3]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleuc_z_store(i8 zeroext %a) {
+; BE-LABEL: test_llleuc_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; BE-NEXT: cntlzw r3, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; BE-NEXT: srwi r3, r3, 5
+; BE-NEXT: stb r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llleuc_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: cntlzw r3, r3
+; LE-NEXT: addis r4, r2, glob at toc@ha
+; LE-NEXT: srwi r3, r3, 5
+; LE-NEXT: stb r3, glob at toc@l(r4)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i8 %a, 0
%conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob
ret void
-; CHECK-LABEL: test_llleuc_z_store:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi {{r[0-9]}}, r3, 5
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleuc_sext_z_store(i8 zeroext %a) {
+; BE-LABEL: test_llleuc_sext_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; BE-NEXT: cntlzw r3, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; BE-NEXT: srwi r3, r3, 5
+; BE-NEXT: neg r3, r3
+; BE-NEXT: stb r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llleuc_sext_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: cntlzw r3, r3
+; LE-NEXT: addis r4, r2, glob at toc@ha
+; LE-NEXT: srwi r3, r3, 5
+; LE-NEXT: neg r3, r3
+; LE-NEXT: stb r3, glob at toc@l(r4)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i8 %a, 0
%conv2 = sext i1 %cmp to i8
store i8 %conv2, i8* @glob
ret void
-; CHECK-LABEL: @test_llleuc_sext_z_store
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
-; CHECK: neg [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: stb [[REG3]]
-; CHECK: blr
}
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllleui.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllleui.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllleui.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllleui.ll Thu Aug 22 13:26:56 2019
@@ -1,117 +1,173 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleui(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llleui:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i32 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
-; CHECK-LABEL: test_llleui:
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleui_sext(i32 zeroext %a, i32 zeroext %b) {
+; CHECK-LABEL: test_llleui_sext:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: addi r3, r3, -1
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i32 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
-; CHECK-LABEL: @test_llleui_sext
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleui_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llleui_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i32 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
-; CHECK-LABEL: test_llleui_z:
-; CHECK: cntlzw r3, r3
-; CHECK-NEXT: srwi r3, r3, 5
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleui_sext_z(i32 zeroext %a) {
+; CHECK-LABEL: test_llleui_sext_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i32 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
-; CHECK-LABEL: @test_llleui_sext_z
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
-; CHECK-NEXT: neg r3, [[REG2]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleui_store(i32 zeroext %a, i32 zeroext %b) {
+; BE-LABEL: test_llleui_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r4, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: not r3, r3
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: stw r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llleui_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r4, r3
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: not r3, r3
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: stw r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i32 %a, %b
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob
ret void
-; CHECK-LABEL: test_llleui_store:
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleui_sext_store(i32 zeroext %a, i32 zeroext %b) {
+; BE-LABEL: test_llleui_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r4, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: addi r3, r3, -1
+; BE-NEXT: stw r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llleui_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r4, r3
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: addi r3, r3, -1
+; LE-NEXT: stw r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i32 %a, %b
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob
ret void
-; CHECK-LABEL: @test_llleui_sext_store
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK: stw [[REG3]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleui_z_store(i32 zeroext %a) {
+; BE-LABEL: test_llleui_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; BE-NEXT: cntlzw r3, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; BE-NEXT: srwi r3, r3, 5
+; BE-NEXT: stw r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llleui_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: cntlzw r3, r3
+; LE-NEXT: addis r4, r2, glob at toc@ha
+; LE-NEXT: srwi r3, r3, 5
+; LE-NEXT: stw r3, glob at toc@l(r4)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i32 %a, 0
%conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob
ret void
-; CHECK-LABEL: test_llleui_z_store:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleui_sext_z_store(i32 zeroext %a) {
+; BE-LABEL: test_llleui_sext_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; BE-NEXT: cntlzw r3, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; BE-NEXT: srwi r3, r3, 5
+; BE-NEXT: neg r3, r3
+; BE-NEXT: stw r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llleui_sext_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: cntlzw r3, r3
+; LE-NEXT: addis r4, r2, glob at toc@ha
+; LE-NEXT: srwi r3, r3, 5
+; LE-NEXT: neg r3, r3
+; LE-NEXT: stw r3, glob at toc@l(r4)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i32 %a, 0
%sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob
ret void
-; CHECK-LABEL: @test_llleui_sext_z_store
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
-; CHECK: neg [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: stw [[REG3]]
-; CHECK: blr
}
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllleull.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllleull.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllleull.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllleull.ll Thu Aug 22 13:26:56 2019
@@ -1,115 +1,170 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleull(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llleull:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subfc r4, r3, r4
+; CHECK-NEXT: subfe r3, r3, r3
+; CHECK-NEXT: addi r3, r3, 1
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i64 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
-; CHECK-LABEL: test_llleull:
-; CHECK: subfc {{r[0-9]+}}, r3, r4
-; CHECK-NEXT: subfe [[REG1:r[0-9]+]], r3, r3
-; CHECK-NEXT: addi r3, [[REG1]], 1
-; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleull_sext(i64 %a, i64 %b) {
+; CHECK-LABEL: test_llleull_sext:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: subfc r4, r3, r4
+; CHECK-NEXT: subfe r3, r3, r3
+; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i64 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
-; CHECK-LABEL: @test_llleull_sext
-; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
-; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
-; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleull_z(i64 %a) {
+; CHECK-LABEL: test_llleull_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzd r3, r3
+; CHECK-NEXT: rldicl r3, r3, 58, 63
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i64 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
-; CHECK-LABEL: test_llleull_z
-; CHECK: cntlzd [[REG1:r[0-9]+]], r3
-; CHECK-NEXT: rldicl r3, [[REG1]], 58, 63
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleull_sext_z(i64 %a) {
+; CHECK-LABEL: test_llleull_sext_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addic r3, r3, -1
+; CHECK-NEXT: subfe r3, r3, r3
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i64 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
-; CHECK-LABEL: @test_llleull_sext_z
-; CHECK: addic [[REG1:r[0-9]+]], r3, -1
-; CHECK: subfe r3, [[REG1]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleull_store(i64 %a, i64 %b) {
+; BE-LABEL: test_llleull_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: subfc r4, r3, r4
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: subfe r3, r3, r3
+; BE-NEXT: addi r3, r3, 1
+; BE-NEXT: std r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llleull_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: subfc r4, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: subfe r3, r3, r3
+; LE-NEXT: addi r3, r3, 1
+; LE-NEXT: std r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
-; CHECK-LABEL: test_llleull_store:
-; CHECK: subfc {{r[0-9]+}}, r3, r4
-; CHECK: subfe [[REG1:r[0-9]+]], r3, r3
-; CHECK: addi r3, [[REG1]], 1
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleull_sext_store(i64 %a, i64 %b) {
+; BE-LABEL: test_llleull_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: subfc r4, r3, r4
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: subfe r3, r3, r3
+; BE-NEXT: not r3, r3
+; BE-NEXT: std r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llleull_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: subfc r4, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: subfe r3, r3, r3
+; LE-NEXT: not r3, r3
+; LE-NEXT: std r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
-; CHECK-LABEL: @test_llleull_sext_store
-; CHECK: subfc [[REG1:r[0-9]+]], r3, r4
-; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
-; CHECK: not [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: std [[REG3]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleull_z_store(i64 %a) {
+; BE-LABEL: test_llleull_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; BE-NEXT: cntlzd r3, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; BE-NEXT: rldicl r3, r3, 58, 63
+; BE-NEXT: std r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llleull_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: cntlzd r3, r3
+; LE-NEXT: addis r4, r2, glob at toc@ha
+; LE-NEXT: rldicl r3, r3, 58, 63
+; LE-NEXT: std r3, glob at toc@l(r4)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
-; CHECK-LABEL: test_llleull_z_store:
-; CHECK: cntlzd [[REG1:r[0-9]+]], r3
-; CHECK: rldicl {{r[0-9]+}}, [[REG1]], 58, 63
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleull_sext_z_store(i64 %a) {
+; BE-LABEL: test_llleull_sext_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; BE-NEXT: addic r3, r3, -1
+; BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; BE-NEXT: subfe r3, r3, r3
+; BE-NEXT: std r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llleull_sext_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: addic r3, r3, -1
+; LE-NEXT: addis r4, r2, glob at toc@ha
+; LE-NEXT: subfe r3, r3, r3
+; LE-NEXT: std r3, glob at toc@l(r4)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i64 %a, 0
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob
ret void
-; CHECK-LABEL: @test_llleull_sext_z_store
-; CHECK: addic [[REG1:r[0-9]+]], r3, -1
-; CHECK: subfe [[REG2:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}
-; CHECK: std [[REG2]]
-; CHECK: blr
}
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllleus.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllleus.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllleus.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllleus.ll Thu Aug 22 13:26:56 2019
@@ -1,117 +1,173 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleus(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llleus:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: not r3, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i16 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
-; CHECK-LABEL: test_llleus:
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleus_sext(i16 zeroext %a, i16 zeroext %b) {
+; CHECK-LABEL: test_llleus_sext:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub r3, r4, r3
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: addi r3, r3, -1
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i16 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
-; CHECK-LABEL: @test_llleus_sext
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleus_z(i16 zeroext %a) {
+; CHECK-LABEL: test_llleus_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i16 %a, 0
%conv2 = zext i1 %cmp to i64
ret i64 %conv2
-; CHECK-LABEL: test_llleus_z:
-; CHECK: cntlzw r3, r3
-; CHECK-NEXT: srwi r3, r3, 5
-; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llleus_sext_z(i16 zeroext %a) {
+; CHECK-LABEL: test_llleus_sext_z:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cntlzw r3, r3
+; CHECK-NEXT: srwi r3, r3, 5
+; CHECK-NEXT: neg r3, r3
+; CHECK-NEXT: blr
entry:
%cmp = icmp ule i16 %a, 0
%conv2 = sext i1 %cmp to i64
ret i64 %conv2
-; CHECK-LABEL: @test_llleus_sext_z
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
-; CHECK-NEXT: neg r3, [[REG2]]
-; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleus_store(i16 zeroext %a, i16 zeroext %b) {
+; BE-LABEL: test_llleus_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r4, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: not r3, r3
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: sth r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llleus_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r4, r3
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: not r3, r3
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: sth r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob
ret void
-; CHECK-LABEL: test_llleus_store:
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: not [[REG2:r[0-9]+]], [[REG1]]
-; CHECK-NEXT: rldicl r3, [[REG2]], 1, 63
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleus_sext_store(i16 zeroext %a, i16 zeroext %b) {
+; BE-LABEL: test_llleus_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r4, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: addi r3, r3, -1
+; BE-NEXT: sth r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llleus_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r4, r3
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: addi r3, r3, -1
+; LE-NEXT: sth r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob
ret void
-; CHECK-LABEL: @test_llleus_sext_store
-; CHECK: sub [[REG1:r[0-9]+]], r4, r3
-; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
-; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
-; CHECK: sth [[REG3]]
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleus_z_store(i16 zeroext %a) {
+; BE-LABEL: test_llleus_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; BE-NEXT: cntlzw r3, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; BE-NEXT: srwi r3, r3, 5
+; BE-NEXT: sth r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llleus_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: cntlzw r3, r3
+; LE-NEXT: addis r4, r2, glob at toc@ha
+; LE-NEXT: srwi r3, r3, 5
+; LE-NEXT: sth r3, glob at toc@l(r4)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i16 %a, 0
%conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob
ret void
-; CHECK-LABEL: test_llleus_z_store:
-; CHECK: cntlzw r3, r3
-; CHECK: srwi r3, r3, 5
-; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llleus_sext_z_store(i16 zeroext %a) {
+; BE-LABEL: test_llleus_sext_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; BE-NEXT: cntlzw r3, r3
+; BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; BE-NEXT: srwi r3, r3, 5
+; BE-NEXT: neg r3, r3
+; BE-NEXT: sth r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llleus_sext_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: cntlzw r3, r3
+; LE-NEXT: addis r4, r2, glob at toc@ha
+; LE-NEXT: srwi r3, r3, 5
+; LE-NEXT: neg r3, r3
+; LE-NEXT: sth r3, glob at toc@l(r4)
+; LE-NEXT: blr
entry:
%cmp = icmp ule i16 %a, 0
%conv2 = sext i1 %cmp to i16
store i16 %conv2, i16* @glob
ret void
-; CHECK-LABEL: @test_llleus_sext_z_store
-; CHECK: cntlzw [[REG1:r[0-9]+]], r3
-; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
-; CHECK: neg [[REG3:r[0-9]+]], [[REG2]]
-; CHECK: sth [[REG3]]
-; CHECK: blr
}
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllltsll.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllltsll.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllltsll.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllltsll.ll Thu Aug 22 13:26:56 2019
@@ -1,10 +1,12 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i64 0, align 8
@@ -12,11 +14,11 @@
define i64 @test_llltsll(i64 %a, i64 %b) {
; CHECK-LABEL: test_llltsll:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63
-; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3
-; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK-NEXT: xori r3, [[REG4]], 1
+; CHECK-NEXT: sradi r5, r3, 63
+; CHECK-NEXT: rldicl r6, r4, 1, 63
+; CHECK-NEXT: subfc r3, r4, r3
+; CHECK-NEXT: adde r3, r6, r5
+; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, %b
@@ -28,12 +30,12 @@ entry:
define i64 @test_llltsll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llltsll_sext:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63
-; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63
-; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3
-; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1
-; CHECK-NEXT: neg r3, [[REG5]]
+; CHECK-NEXT: sradi r5, r3, 63
+; CHECK-NEXT: rldicl r6, r4, 1, 63
+; CHECK-NEXT: subfc r3, r4, r3
+; CHECK-NEXT: adde r3, r6, r5
+; CHECK-NEXT: xori r3, r3, 1
+; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i64 %a, %b
@@ -55,14 +57,29 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_llltsll_store(i64 %a, i64 %b) {
-; CHECK-LABEL: test_llltsll_store:
-; CHECK: # %bb.0: # %entry
-; CHECK: sradi [[REG1:r[0-9]+]], r3, 63
-; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63
+; BE-LABEL: test_llltsll_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: sradi r6, r3, 63
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: subfc r3, r4, r3
+; BE-NEXT: rldicl r3, r4, 1, 63
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: adde r3, r3, r6
+; BE-NEXT: xori r3, r3, 1
+; BE-NEXT: std r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llltsll_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sradi r6, r3, 63
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: subfc r3, r4, r3
+; LE-NEXT: rldicl r3, r4, 1, 63
+; LE-NEXT: adde r3, r3, r6
+; LE-NEXT: xori r3, r3, 1
+; LE-NEXT: std r3, glob at toc@l(r5)
+; LE-NEXT: blr
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3
-; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
-; CHECK-NOT: neg
entry:
%cmp = icmp slt i64 %a, %b
%conv1 = zext i1 %cmp to i64
@@ -72,14 +89,31 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_llltsll_sext_store(i64 %a, i64 %b) {
-; CHECK-LABEL: test_llltsll_sext_store:
-; CHECK: # %bb.0: # %entry
-; CHECK: sradi [[REG1:r[0-9]+]], r3, 63
-; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63
+; BE-LABEL: test_llltsll_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: sradi r6, r3, 63
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: subfc r3, r4, r3
+; BE-NEXT: rldicl r3, r4, 1, 63
+; BE-NEXT: ld r4, .LC0 at toc@l(r5)
+; BE-NEXT: adde r3, r3, r6
+; BE-NEXT: xori r3, r3, 1
+; BE-NEXT: neg r3, r3
+; BE-NEXT: std r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llltsll_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sradi r6, r3, 63
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: subfc r3, r4, r3
+; LE-NEXT: rldicl r3, r4, 1, 63
+; LE-NEXT: adde r3, r3, r6
+; LE-NEXT: xori r3, r3, 1
+; LE-NEXT: neg r3, r3
+; LE-NEXT: std r3, glob at toc@l(r5)
+; LE-NEXT: blr
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3
-; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
-; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
-; CHECK: neg {{r[0-9]+}}, [[REG5]]
entry:
%cmp = icmp slt i64 %a, %b
%conv1 = sext i1 %cmp to i64
@@ -89,8 +123,20 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_llltsll_sext_z_store(i64 %a) {
-; CHECK-LABEL: test_llltsll_sext_z_store:
-; CHECK: sradi r3, r3, 63
+; BE-LABEL: test_llltsll_sext_z_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r4, r2, .LC0 at toc@ha
+; BE-NEXT: sradi r3, r3, 63
+; BE-NEXT: ld r4, .LC0 at toc@l(r4)
+; BE-NEXT: std r3, 0(r4)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llltsll_sext_z_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: addis r4, r2, glob at toc@ha
+; LE-NEXT: sradi r3, r3, 63
+; LE-NEXT: std r3, glob at toc@l(r4)
+; LE-NEXT: blr
entry:
%cmp = icmp slt i64 %a, 0
%sub = sext i1 %cmp to i64
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllltuc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllltuc.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllltuc.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllltuc.ll Thu Aug 22 13:26:56 2019
@@ -1,9 +1,12 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i8 0, align 1
@@ -11,8 +14,8 @@
define i64 @test_llltuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llltuc:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i8 %a, %b
@@ -24,8 +27,8 @@ entry:
define i64 @test_llltuc_sext(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llltuc_sext:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i8 %a, %b
@@ -35,10 +38,22 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_llltuc_store(i8 zeroext %a, i8 zeroext %b) {
-; CHECK-LABEL: test_llltuc_store:
-; CHECK: # %bb.0: # %entry
-; CHECK: sub [[REG:r[2-9]+]], r3, r4
-; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; BE-LABEL: test_llltuc_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r5, .LC0 at toc@l(r5)
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: stb r3, 0(r5)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llltuc_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: stb r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ult i8 %a, %b
%conv3 = zext i1 %cmp to i8
@@ -48,10 +63,22 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_llltuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
-; CHECK-LABEL: test_llltuc_sext_store:
-; CHECK: # %bb.0: # %entry
-; CHECK: sub [[REG:r[0-9]+]], r3, r4
-; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+; BE-LABEL: test_llltuc_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r5, .LC0 at toc@l(r5)
+; BE-NEXT: sradi r3, r3, 63
+; BE-NEXT: stb r3, 0(r5)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llltuc_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: sradi r3, r3, 63
+; LE-NEXT: stb r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ult i8 %a, %b
%conv3 = sext i1 %cmp to i8
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllltui.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllltui.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllltui.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllltui.ll Thu Aug 22 13:26:56 2019
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@@ -11,9 +12,8 @@
define i64 @test_llltui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llltui:
; CHECK: # %bb.0: # %entry
-; CHECK-NOT: clrldi
-; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i32 %a, %b
@@ -25,8 +25,8 @@ entry:
define i64 @test_llltui_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llltui_sext:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i32 %a, %b
@@ -58,9 +58,12 @@ entry:
define void @test_llltui_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llltui_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NOT: clrldi
-; CHECK: sub [[REG:r[2-9]+]], r3, r4
-; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: rldicl r3, r3, 1, 63
+; CHECK-NEXT: stw r3, 0(r5)
+; CHECK-NEXT: blr
entry:
%cmp = icmp ult i32 %a, %b
%conv = zext i1 %cmp to i32
@@ -72,9 +75,12 @@ entry:
define void @test_llltui_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llltui_sext_store:
; CHECK: # %bb.0: # %entry
-; CHECK-NOT: clrldi
-; CHECK: sub [[REG:r[0-9]+]], r3, r4
-; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+; CHECK-NEXT: addis r5, r2, .LC0 at toc@ha
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: ld r5, .LC0 at toc@l(r5)
+; CHECK-NEXT: sradi r3, r3, 63
+; CHECK-NEXT: stw r3, 0(r5)
+; CHECK-NEXT: blr
entry:
%cmp = icmp ult i32 %a, %b
%sub = sext i1 %cmp to i32
@@ -86,8 +92,10 @@ entry:
define void @test_llltui_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_llltui_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK: li [[REG:r[0-9]+]], 0
-; CHECK: stw [[REG]], 0(r3)
+; CHECK-NEXT: addis r3, r2, .LC0 at toc@ha
+; CHECK-NEXT: li r4, 0
+; CHECK-NEXT: ld r3, .LC0 at toc@l(r3)
+; CHECK-NEXT: stw r4, 0(r3)
; CHECK-NEXT: blr
entry:
store i32 0, i32* @glob, align 4
@@ -98,8 +106,10 @@ entry:
define void @test_llltui_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_llltui_sext_z_store:
; CHECK: # %bb.0: # %entry
-; CHECK: li [[REG:r[0-9]+]], 0
-; CHECK: stw [[REG]], 0(r3)
+; CHECK-NEXT: addis r3, r2, .LC0 at toc@ha
+; CHECK-NEXT: li r4, 0
+; CHECK-NEXT: ld r3, .LC0 at toc@l(r3)
+; CHECK-NEXT: stw r4, 0(r3)
; CHECK-NEXT: blr
entry:
store i32 0, i32* @glob, align 4
Modified: llvm/trunk/test/CodeGen/PowerPC/testComparesllltus.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/testComparesllltus.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/testComparesllltus.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/testComparesllltus.ll Thu Aug 22 13:26:56 2019
@@ -1,9 +1,12 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
-; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
+; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
+; RUN: --check-prefixes=CHECK,LE
@glob = common local_unnamed_addr global i16 0, align 2
@@ -11,8 +14,8 @@
define i64 @test_llltus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llltus:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT: rldicl r3, [[REG]], 1, 63
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i16 %a, %b
@@ -24,8 +27,8 @@ entry:
define i64 @test_llltus_sext(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llltus_sext:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4
-; CHECK-NEXT: sradi r3, [[REG]], 63
+; CHECK-NEXT: sub r3, r3, r4
+; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp ult i16 %a, %b
@@ -35,9 +38,22 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_llltus_store(i16 zeroext %a, i16 zeroext %b) {
-; CHECK-LABEL: test_llltus_store:
-; CHECK: sub [[REG:r[2-9]+]], r3, r4
-; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63
+; BE-LABEL: test_llltus_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r5, .LC0 at toc@l(r5)
+; BE-NEXT: rldicl r3, r3, 1, 63
+; BE-NEXT: sth r3, 0(r5)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llltus_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: rldicl r3, r3, 1, 63
+; LE-NEXT: sth r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ult i16 %a, %b
%conv3 = zext i1 %cmp to i16
@@ -47,10 +63,22 @@ entry:
; Function Attrs: norecurse nounwind
define void @test_llltus_sext_store(i16 zeroext %a, i16 zeroext %b) {
-; CHECK-LABEL: test_llltus_sext_store:
-; CHECK: # %bb.0: # %entry
-; CHECK: sub [[REG:r[0-9]+]], r3, r4
-; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
+; BE-LABEL: test_llltus_sext_store:
+; BE: # %bb.0: # %entry
+; BE-NEXT: addis r5, r2, .LC0 at toc@ha
+; BE-NEXT: sub r3, r3, r4
+; BE-NEXT: ld r5, .LC0 at toc@l(r5)
+; BE-NEXT: sradi r3, r3, 63
+; BE-NEXT: sth r3, 0(r5)
+; BE-NEXT: blr
+;
+; LE-LABEL: test_llltus_sext_store:
+; LE: # %bb.0: # %entry
+; LE-NEXT: sub r3, r3, r4
+; LE-NEXT: addis r5, r2, glob at toc@ha
+; LE-NEXT: sradi r3, r3, 63
+; LE-NEXT: sth r3, glob at toc@l(r5)
+; LE-NEXT: blr
entry:
%cmp = icmp ult i16 %a, %b
%conv3 = sext i1 %cmp to i16
Modified: llvm/trunk/test/CodeGen/PowerPC/vec_shuffle.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_shuffle.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec_shuffle.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/vec_shuffle.ll Thu Aug 22 13:26:56 2019
@@ -1,13 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: opt -mtriple=powerpc-unknown-linux-gnu < %s -instcombine | \
; RUN: llc -mtriple=ppc32-- -mcpu=g5 | not grep vperm
-; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 > %t
-; RUN: grep vsldoi %t | count 2
-; RUN: grep vmrgh %t | count 7
-; RUN: grep vmrgl %t | count 6
-; RUN: grep vpkuhum %t | count 1
-; RUN: grep vpkuwum %t | count 1
+; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | FileCheck %s
define void @VSLDOI_xy(<8 x i16>* %A, <8 x i16>* %B) {
+; CHECK-LABEL: VSLDOI_xy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: lvx 3, 0, 4
+; CHECK-NEXT: vsldoi 2, 2, 3, 5
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
%tmp = load <8 x i16>, <8 x i16>* %A ; <<8 x i16>> [#uses=1]
%tmp2 = load <8 x i16>, <8 x i16>* %B ; <<8 x i16>> [#uses=1]
@@ -51,6 +54,12 @@ entry:
}
define void @VSLDOI_xx(<8 x i16>* %A, <8 x i16>* %B) {
+; CHECK-LABEL: VSLDOI_xx:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: vsldoi 2, 2, 2, 5
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
%tmp = load <8 x i16>, <8 x i16>* %A ; <<8 x i16>> [#uses=1]
%tmp2 = load <8 x i16>, <8 x i16>* %A ; <<8 x i16>> [#uses=1]
%tmp.upgrd.5 = bitcast <8 x i16> %tmp to <16 x i8> ; <<16 x i8>> [#uses=11]
@@ -93,6 +102,14 @@ define void @VSLDOI_xx(<8 x i16>* %A, <8
}
define void @VPERM_promote(<8 x i16>* %A, <8 x i16>* %B) {
+; CHECK-LABEL: VPERM_promote:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: vspltisb 4, 14
+; CHECK-NEXT: lvx 3, 0, 4
+; CHECK-NEXT: vperm 2, 2, 3, 4
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
%tmp = load <8 x i16>, <8 x i16>* %A ; <<8 x i16>> [#uses=1]
%tmp.upgrd.9 = bitcast <8 x i16> %tmp to <4 x i32> ; <<4 x i32>> [#uses=1]
@@ -107,6 +124,13 @@ entry:
declare <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32>, <4 x i32>, <16 x i8>)
define void @tb_l(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: tb_l:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: lvx 3, 0, 4
+; CHECK-NEXT: vmrglb 2, 2, 3
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
%tmp = load <16 x i8>, <16 x i8>* %A ; <<16 x i8>> [#uses=8]
%tmp2 = load <16 x i8>, <16 x i8>* %B ; <<16 x i8>> [#uses=8]
@@ -147,6 +171,13 @@ entry:
}
define void @th_l(<8 x i16>* %A, <8 x i16>* %B) {
+; CHECK-LABEL: th_l:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: lvx 3, 0, 4
+; CHECK-NEXT: vmrglh 2, 2, 3
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
%tmp = load <8 x i16>, <8 x i16>* %A ; <<8 x i16>> [#uses=4]
%tmp2 = load <8 x i16>, <8 x i16>* %B ; <<8 x i16>> [#uses=4]
@@ -171,6 +202,13 @@ entry:
}
define void @tw_l(<4 x i32>* %A, <4 x i32>* %B) {
+; CHECK-LABEL: tw_l:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: lvx 3, 0, 4
+; CHECK-NEXT: vmrglw 2, 2, 3
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
%tmp = load <4 x i32>, <4 x i32>* %A ; <<4 x i32>> [#uses=2]
%tmp2 = load <4 x i32>, <4 x i32>* %B ; <<4 x i32>> [#uses=2]
@@ -187,6 +225,13 @@ entry:
}
define void @tb_h(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: tb_h:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: lvx 3, 0, 4
+; CHECK-NEXT: vmrghb 2, 2, 3
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
%tmp = load <16 x i8>, <16 x i8>* %A ; <<16 x i8>> [#uses=8]
%tmp2 = load <16 x i8>, <16 x i8>* %B ; <<16 x i8>> [#uses=8]
@@ -227,6 +272,13 @@ entry:
}
define void @th_h(<8 x i16>* %A, <8 x i16>* %B) {
+; CHECK-LABEL: th_h:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: lvx 3, 0, 4
+; CHECK-NEXT: vmrghh 2, 2, 3
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
%tmp = load <8 x i16>, <8 x i16>* %A ; <<8 x i16>> [#uses=4]
%tmp2 = load <8 x i16>, <8 x i16>* %B ; <<8 x i16>> [#uses=4]
@@ -251,6 +303,13 @@ entry:
}
define void @tw_h(<4 x i32>* %A, <4 x i32>* %B) {
+; CHECK-LABEL: tw_h:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: lvx 3, 0, 4
+; CHECK-NEXT: vmrghw 2, 3, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
%tmp = load <4 x i32>, <4 x i32>* %A ; <<4 x i32>> [#uses=2]
%tmp2 = load <4 x i32>, <4 x i32>* %B ; <<4 x i32>> [#uses=2]
@@ -267,6 +326,13 @@ entry:
}
define void @tw_h_flop(<4 x i32>* %A, <4 x i32>* %B) {
+; CHECK-LABEL: tw_h_flop:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: lvx 3, 0, 4
+; CHECK-NEXT: vmrghw 2, 2, 3
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
%tmp = load <4 x i32>, <4 x i32>* %A ; <<4 x i32>> [#uses=2]
%tmp2 = load <4 x i32>, <4 x i32>* %B ; <<4 x i32>> [#uses=2]
%tmp.upgrd.18 = extractelement <4 x i32> %tmp, i32 0 ; <i32> [#uses=1]
@@ -282,6 +348,12 @@ define void @tw_h_flop(<4 x i32>* %A, <4
}
define void @VMRG_UNARY_tb_l(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: VMRG_UNARY_tb_l:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: vmrglb 2, 2, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
%tmp = load <16 x i8>, <16 x i8>* %A ; <<16 x i8>> [#uses=16]
%tmp.upgrd.19 = extractelement <16 x i8> %tmp, i32 8 ; <i8> [#uses=1]
@@ -321,6 +393,12 @@ entry:
}
define void @VMRG_UNARY_th_l(<8 x i16>* %A, <8 x i16>* %B) {
+; CHECK-LABEL: VMRG_UNARY_th_l:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: vmrglh 2, 2, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
%tmp = load <8 x i16>, <8 x i16>* %A ; <<8 x i16>> [#uses=8]
%tmp.upgrd.20 = extractelement <8 x i16> %tmp, i32 4 ; <i16> [#uses=1]
@@ -344,6 +422,12 @@ entry:
}
define void @VMRG_UNARY_tw_l(<4 x i32>* %A, <4 x i32>* %B) {
+; CHECK-LABEL: VMRG_UNARY_tw_l:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: vmrglw 2, 2, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
%tmp = load <4 x i32>, <4 x i32>* %A ; <<4 x i32>> [#uses=4]
%tmp.upgrd.21 = extractelement <4 x i32> %tmp, i32 2 ; <i32> [#uses=1]
@@ -359,6 +443,12 @@ entry:
}
define void @VMRG_UNARY_tb_h(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: VMRG_UNARY_tb_h:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: vmrghb 2, 2, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
%tmp = load <16 x i8>, <16 x i8>* %A ; <<16 x i8>> [#uses=16]
%tmp.upgrd.22 = extractelement <16 x i8> %tmp, i32 0 ; <i8> [#uses=1]
@@ -398,6 +488,12 @@ entry:
}
define void @VMRG_UNARY_th_h(<8 x i16>* %A, <8 x i16>* %B) {
+; CHECK-LABEL: VMRG_UNARY_th_h:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: vmrghh 2, 2, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
%tmp = load <8 x i16>, <8 x i16>* %A ; <<8 x i16>> [#uses=8]
%tmp.upgrd.23 = extractelement <8 x i16> %tmp, i32 0 ; <i16> [#uses=1]
@@ -421,6 +517,12 @@ entry:
}
define void @VMRG_UNARY_tw_h(<4 x i32>* %A, <4 x i32>* %B) {
+; CHECK-LABEL: VMRG_UNARY_tw_h:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: vmrghw 2, 2, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
%tmp = load <4 x i32>, <4 x i32>* %A ; <<4 x i32>> [#uses=4]
%tmp.upgrd.24 = extractelement <4 x i32> %tmp, i32 0 ; <i32> [#uses=1]
@@ -436,6 +538,12 @@ entry:
}
define void @VPCKUHUM_unary(<8 x i16>* %A, <8 x i16>* %B) {
+; CHECK-LABEL: VPCKUHUM_unary:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: vpkuhum 2, 2, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
%tmp = load <8 x i16>, <8 x i16>* %A ; <<8 x i16>> [#uses=2]
%tmp.upgrd.25 = bitcast <8 x i16> %tmp to <16 x i8> ; <<16 x i8>> [#uses=8]
@@ -478,6 +586,12 @@ entry:
}
define void @VPCKUWUM_unary(<4 x i32>* %A, <4 x i32>* %B) {
+; CHECK-LABEL: VPCKUWUM_unary:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: vpkuwum 2, 2, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
%tmp = load <4 x i32>, <4 x i32>* %A ; <<4 x i32>> [#uses=2]
%tmp.upgrd.28 = bitcast <4 x i32> %tmp to <8 x i16> ; <<8 x i16>> [#uses=4]
Modified: llvm/trunk/test/CodeGen/PowerPC/vec_shuffle_le.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_shuffle_le.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec_shuffle_le.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/vec_shuffle_le.ll Thu Aug 22 13:26:56 2019
@@ -1,208 +1,272 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mcpu=pwr7 | FileCheck %s
define void @VPKUHUM_xy(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: VPKUHUM_xy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: lvx 3, 0, 4
+; CHECK-NEXT: vpkuhum 2, 3, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
-; CHECK: VPKUHUM_xy:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
-; CHECK: lvx [[REG1:[0-9]+]]
-; CHECK: lvx [[REG2:[0-9]+]]
-; CHECK: vpkuhum [[REG3:[0-9]+]], [[REG2]], [[REG1]]
store <16 x i8> %tmp3, <16 x i8>* %A
ret void
}
define void @VPKUHUM_xx(<16 x i8>* %A) {
+; CHECK-LABEL: VPKUHUM_xx:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: vpkuhum 2, 2, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
-; CHECK: VPKUHUM_xx:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
-; CHECK: vpkuhum
store <16 x i8> %tmp2, <16 x i8>* %A
ret void
}
define void @VPKUWUM_xy(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: VPKUWUM_xy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: lvx 3, 0, 4
+; CHECK-NEXT: vpkuwum 2, 3, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
-; CHECK: VPKUWUM_xy:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 16, i32 17, i32 20, i32 21, i32 24, i32 25, i32 28, i32 29>
-; CHECK: lvx [[REG1:[0-9]+]]
-; CHECK: lvx [[REG2:[0-9]+]]
-; CHECK: vpkuwum [[REG3:[0-9]+]], [[REG2]], [[REG1]]
store <16 x i8> %tmp3, <16 x i8>* %A
ret void
}
define void @VPKUWUM_xx(<16 x i8>* %A) {
+; CHECK-LABEL: VPKUWUM_xx:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: vpkuwum 2, 2, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
-; CHECK: VPKUWUM_xx:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13>
-; CHECK: vpkuwum
store <16 x i8> %tmp2, <16 x i8>* %A
ret void
}
define void @VMRGLB_xy(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: VMRGLB_xy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: lvx 3, 0, 4
+; CHECK-NEXT: vmrglb 2, 3, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
-; CHECK: VMRGLB_xy:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
-; CHECK: lvx [[REG1:[0-9]+]]
-; CHECK: lvx [[REG2:[0-9]+]]
-; CHECK: vmrglb [[REG3:[0-9]+]], [[REG2]], [[REG1]]
store <16 x i8> %tmp3, <16 x i8>* %A
ret void
}
define void @VMRGLB_xx(<16 x i8>* %A) {
+; CHECK-LABEL: VMRGLB_xx:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: vmrglb 2, 2, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
-; CHECK: VMRGLB_xx:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3, i32 4, i32 4, i32 5, i32 5, i32 6, i32 6, i32 7, i32 7>
-; CHECK: vmrglb
store <16 x i8> %tmp2, <16 x i8>* %A
ret void
}
define void @VMRGHB_xy(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: VMRGHB_xy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: lvx 3, 0, 4
+; CHECK-NEXT: vmrghb 2, 3, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
-; CHECK: VMRGHB_xy:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
-; CHECK: lvx [[REG1:[0-9]+]]
-; CHECK: lvx [[REG2:[0-9]+]]
-; CHECK: vmrghb [[REG3:[0-9]+]], [[REG2]], [[REG1]]
store <16 x i8> %tmp3, <16 x i8>* %A
ret void
}
define void @VMRGHB_xx(<16 x i8>* %A) {
+; CHECK-LABEL: VMRGHB_xx:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: vmrghb 2, 2, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
-; CHECK: VMRGHB_xx:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 8, i32 9, i32 9, i32 10, i32 10, i32 11, i32 11, i32 12, i32 12, i32 13, i32 13, i32 14, i32 14, i32 15, i32 15>
-; CHECK: vmrghb
store <16 x i8> %tmp2, <16 x i8>* %A
ret void
}
define void @VMRGLH_xy(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: VMRGLH_xy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: lvx 3, 0, 4
+; CHECK-NEXT: vmrglh 2, 3, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
-; CHECK: VMRGLH_xy:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 2, i32 3, i32 18, i32 19, i32 4, i32 5, i32 20, i32 21, i32 6, i32 7, i32 22, i32 23>
-; CHECK: lvx [[REG1:[0-9]+]]
-; CHECK: lvx [[REG2:[0-9]+]]
-; CHECK: vmrglh [[REG3:[0-9]+]], [[REG2]], [[REG1]]
store <16 x i8> %tmp3, <16 x i8>* %A
ret void
}
define void @VMRGLH_xx(<16 x i8>* %A) {
+; CHECK-LABEL: VMRGLH_xx:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: vmrglh 2, 2, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
-; CHECK: VMRGLH_xx:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 4, i32 5, i32 4, i32 5, i32 6, i32 7, i32 6, i32 7>
-; CHECK: vmrglh
store <16 x i8> %tmp2, <16 x i8>* %A
ret void
}
define void @VMRGHH_xy(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: VMRGHH_xy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: lvx 3, 0, 4
+; CHECK-NEXT: vmrghh 2, 3, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
-; CHECK: VMRGHH_xy:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 9, i32 24, i32 25, i32 10, i32 11, i32 26, i32 27, i32 12, i32 13, i32 28, i32 29, i32 14, i32 15, i32 30, i32 31>
-; CHECK: lvx [[REG1:[0-9]+]]
-; CHECK: lvx [[REG2:[0-9]+]]
-; CHECK: vmrghh [[REG3:[0-9]+]], [[REG2]], [[REG1]]
store <16 x i8> %tmp3, <16 x i8>* %A
ret void
}
define void @VMRGHH_xx(<16 x i8>* %A) {
+; CHECK-LABEL: VMRGHH_xx:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: vmrghh 2, 2, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
-; CHECK: VMRGHH_xx:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 9, i32 8, i32 9, i32 10, i32 11, i32 10, i32 11, i32 12, i32 13, i32 12, i32 13, i32 14, i32 15, i32 14, i32 15>
-; CHECK: vmrghh
store <16 x i8> %tmp2, <16 x i8>* %A
ret void
}
define void @VMRGLW_xy(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: VMRGLW_xy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: lvx 3, 0, 4
+; CHECK-NEXT: vmrglw 2, 3, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
-; CHECK: VMRGLW_xy:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23>
-; CHECK: lvx [[REG1:[0-9]+]]
-; CHECK: lvx [[REG2:[0-9]+]]
-; CHECK: vmrglw [[REG3:[0-9]+]], [[REG2]], [[REG1]]
store <16 x i8> %tmp3, <16 x i8>* %A
ret void
}
define void @VMRGLW_xx(<16 x i8>* %A) {
+; CHECK-LABEL: VMRGLW_xx:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: vmrglw 2, 2, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
-; CHECK: VMRGLW_xx:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
-; CHECK: vmrglw
store <16 x i8> %tmp2, <16 x i8>* %A
ret void
}
define void @VMRGHW_xy(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: VMRGHW_xy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: lvx 3, 0, 4
+; CHECK-NEXT: vmrghw 2, 3, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
-; CHECK: VMRGHW_xy:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 24, i32 25, i32 26, i32 27, i32 12, i32 13, i32 14, i32 15, i32 28, i32 29, i32 30, i32 31>
-; CHECK: lvx [[REG1:[0-9]+]]
-; CHECK: lvx [[REG2:[0-9]+]]
-; CHECK: vmrghw [[REG3:[0-9]+]], [[REG2]], [[REG1]]
store <16 x i8> %tmp3, <16 x i8>* %A
ret void
}
define void @VMRGHW_xx(<16 x i8>* %A) {
+; CHECK-LABEL: VMRGHW_xx:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: vmrghw 2, 2, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
-; CHECK: VMRGHW_xx:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15>
-; CHECK: vmrghw
store <16 x i8> %tmp2, <16 x i8>* %A
ret void
}
define void @VSLDOI_xy(<16 x i8>* %A, <16 x i8>* %B) {
+; CHECK-LABEL: VSLDOI_xy:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: lvx 3, 0, 4
+; CHECK-NEXT: vsldoi 2, 3, 2, 4
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
-; CHECK: VSLDOI_xy:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27>
-; CHECK: lvx [[REG1:[0-9]+]]
-; CHECK: lvx [[REG2:[0-9]+]]
-; CHECK: vsldoi [[REG3:[0-9]+]], [[REG2]], [[REG1]], 4
store <16 x i8> %tmp3, <16 x i8>* %A
ret void
}
define void @VSLDOI_xx(<16 x i8>* %A) {
+; CHECK-LABEL: VSLDOI_xx:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: vsldoi 2, 2, 2, 4
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
-; CHECK: VSLDOI_xx:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
-; CHECK: vsldoi {{[0-9]+}}, [[REG1:[0-9]+]], [[REG1]], 4
store <16 x i8> %tmp2, <16 x i8>* %A
ret void
}
Modified: llvm/trunk/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll Thu Aug 22 13:26:56 2019
@@ -1,7 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -mattr=+power8-vector < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck -check-prefix=CHECK-PWR7 %s
define void @VPKUDUM_unary(<2 x i64>* %A) {
+; CHECK-LABEL: VPKUDUM_unary:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lxvw4x 34, 0, 3
+; CHECK-NEXT: vpkudum 2, 2, 2
+; CHECK-NEXT: stxvw4x 34, 0, 3
+; CHECK-NEXT: blr
+;
+; CHECK-PWR7-LABEL: VPKUDUM_unary:
+; CHECK-PWR7: # %bb.0: # %entry
+; CHECK-PWR7-NEXT: lxvw4x 34, 0, 3
+; CHECK-PWR7-NEXT: vmrglw 3, 2, 2
+; CHECK-PWR7-NEXT: vmrghw 2, 2, 2
+; CHECK-PWR7-NEXT: vmrglw 2, 2, 3
+; CHECK-PWR7-NEXT: stxvw4x 34, 0, 3
+; CHECK-PWR7-NEXT: blr
entry:
%tmp = load <2 x i64>, <2 x i64>* %A
%tmp2 = bitcast <2 x i64> %tmp to <4 x i32>
@@ -16,16 +32,24 @@ entry:
ret void
}
-; CHECK-LABEL: @VPKUDUM_unary
-; CHECK-NOT: vperm
-; CHECK-NOT: vmrglw
-; CHECK-NOT: vmrghw
-; CHECK: vpkudum
-; CHECK-PWR7: vmrglw
-; CHECK-PWR7: vmrghw
-; CHECK-PWR7: vmrglw
-
define void @VPKUDUM(<2 x i64>* %A, <2 x i64>* %B) {
+; CHECK-LABEL: VPKUDUM:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lxvw4x 34, 0, 3
+; CHECK-NEXT: lxvw4x 35, 0, 4
+; CHECK-NEXT: vpkudum 2, 2, 3
+; CHECK-NEXT: stxvw4x 34, 0, 3
+; CHECK-NEXT: blr
+;
+; CHECK-PWR7-LABEL: VPKUDUM:
+; CHECK-PWR7: # %bb.0: # %entry
+; CHECK-PWR7-NEXT: lxvw4x 34, 0, 3
+; CHECK-PWR7-NEXT: lxvw4x 35, 0, 4
+; CHECK-PWR7-NEXT: vmrglw 4, 2, 3
+; CHECK-PWR7-NEXT: vmrghw 2, 2, 3
+; CHECK-PWR7-NEXT: vmrglw 2, 2, 4
+; CHECK-PWR7-NEXT: stxvw4x 34, 0, 3
+; CHECK-PWR7-NEXT: blr
entry:
%tmp = load <2 x i64>, <2 x i64>* %A
%tmp2 = bitcast <2 x i64> %tmp to <4 x i32>
@@ -44,11 +68,3 @@ entry:
ret void
}
-; CHECK-LABEL: @VPKUDUM
-; CHECK-NOT: vperm
-; CHECK-NOT: vmrglw
-; CHECK-NOT: vmrghw
-; CHECK: vpkudum
-; CHECK-PWR7: vmrglw
-; CHECK-PWR7: vmrghw
-; CHECK-PWR7: vmrglw
Modified: llvm/trunk/test/CodeGen/PowerPC/vec_shuffle_p8vector_le.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_shuffle_p8vector_le.ll?rev=369700&r1=369699&r2=369700&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec_shuffle_p8vector_le.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/vec_shuffle_p8vector_le.ll Thu Aug 22 13:26:56 2019
@@ -1,6 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -mattr=+power8-vector < %s | FileCheck %s
define void @VPKUDUM_unary(<2 x i64>* %A) {
+; CHECK-LABEL: VPKUDUM_unary:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: vpkudum 2, 2, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
%tmp = load <2 x i64>, <2 x i64>* %A
%tmp2 = bitcast <2 x i64> %tmp to <4 x i32>
@@ -15,11 +22,14 @@ entry:
ret void
}
-; CHECK-LABEL: @VPKUDUM_unary
-; CHECK-NOT: vperm
-; CHECK: vpkudum
-
define void @VPKUDUM(<2 x i64>* %A, <2 x i64>* %B) {
+; CHECK-LABEL: VPKUDUM:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lvx 2, 0, 3
+; CHECK-NEXT: lvx 3, 0, 4
+; CHECK-NEXT: vpkudum 2, 3, 2
+; CHECK-NEXT: stvx 2, 0, 3
+; CHECK-NEXT: blr
entry:
%tmp = load <2 x i64>, <2 x i64>* %A
%tmp2 = bitcast <2 x i64> %tmp to <4 x i32>
@@ -38,6 +48,3 @@ entry:
ret void
}
-; CHECK-LABEL: @VPKUDUM
-; CHECK-NOT: vperm
-; CHECK: vpkudum
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